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/ * bitops. S : S p a r c64 a t o m i c b i t o p e r a t i o n s .
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*
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* Copyright ( C ) 2 0 0 0 , 2 0 0 7 D a v i d S . M i l l e r ( d a v e m @davemloft.net)
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* /
# include < a s m / a s i . h >
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# include < a s m / b a c k o f f . h >
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
.text
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.globl test_and_set_bit
.type test_ a n d _ s e t _ b i t ,#f u n c t i o n
test_and_set_bit : /* %o0=nr, %o1=addr */
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BACKOFF_ S E T U P ( % o 3 )
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srlx % o 0 , 6 , % g 1
mov 1 , % o 2
sllx % g 1 , 3 , % g 3
and % o 0 , 6 3 , % g 2
sllx % o 2 , % g 2 , % o 2
add % o 1 , % g 3 , % o 1
1 : ldx [ % o 1 ] , % g 7
or % g 7 , % o 2 , % g 1
casx [ % o 1 ] , % g 7 , % g 1
cmp % g 7 , % g 1
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bne,p n % x c c , B A C K O F F _ L A B E L ( 2 f , 1 b )
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and % g 7 , % o 2 , % g 2
clr % o 0
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
movrne % g 2 , 1 , % o 0
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retl
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
nop
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2 : BACKOFF_ S P I N ( % o 3 , % o 4 , 1 b )
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.size test_ a n d _ s e t _ b i t , . - t e s t _ a n d _ s e t _ b i t
.globl test_and_clear_bit
.type test_ a n d _ c l e a r _ b i t ,#f u n c t i o n
test_and_clear_bit : /* %o0=nr, %o1=addr */
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BACKOFF_ S E T U P ( % o 3 )
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srlx % o 0 , 6 , % g 1
mov 1 , % o 2
sllx % g 1 , 3 , % g 3
and % o 0 , 6 3 , % g 2
sllx % o 2 , % g 2 , % o 2
add % o 1 , % g 3 , % o 1
1 : ldx [ % o 1 ] , % g 7
andn % g 7 , % o 2 , % g 1
casx [ % o 1 ] , % g 7 , % g 1
cmp % g 7 , % g 1
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bne,p n % x c c , B A C K O F F _ L A B E L ( 2 f , 1 b )
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and % g 7 , % o 2 , % g 2
clr % o 0
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
movrne % g 2 , 1 , % o 0
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retl
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
nop
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2 : BACKOFF_ S P I N ( % o 3 , % o 4 , 1 b )
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.size test_ a n d _ c l e a r _ b i t , . - t e s t _ a n d _ c l e a r _ b i t
.globl test_and_change_bit
.type test_ a n d _ c h a n g e _ b i t ,#f u n c t i o n
test_and_change_bit : /* %o0=nr, %o1=addr */
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BACKOFF_ S E T U P ( % o 3 )
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srlx % o 0 , 6 , % g 1
mov 1 , % o 2
sllx % g 1 , 3 , % g 3
and % o 0 , 6 3 , % g 2
sllx % o 2 , % g 2 , % o 2
add % o 1 , % g 3 , % o 1
1 : ldx [ % o 1 ] , % g 7
xor % g 7 , % o 2 , % g 1
casx [ % o 1 ] , % g 7 , % g 1
cmp % g 7 , % g 1
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bne,p n % x c c , B A C K O F F _ L A B E L ( 2 f , 1 b )
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and % g 7 , % o 2 , % g 2
clr % o 0
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
movrne % g 2 , 1 , % o 0
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retl
[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 15:42:04 -07:00
nop
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2 : BACKOFF_ S P I N ( % o 3 , % o 4 , 1 b )
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.size test_ a n d _ c h a n g e _ b i t , . - t e s t _ a n d _ c h a n g e _ b i t
.globl set_bit
.type set_ b i t ,#f u n c t i o n
set_bit : /* %o0=nr, %o1=addr */
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BACKOFF_ S E T U P ( % o 3 )
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srlx % o 0 , 6 , % g 1
mov 1 , % o 2
sllx % g 1 , 3 , % g 3
and % o 0 , 6 3 , % g 2
sllx % o 2 , % g 2 , % o 2
add % o 1 , % g 3 , % o 1
1 : ldx [ % o 1 ] , % g 7
or % g 7 , % o 2 , % g 1
casx [ % o 1 ] , % g 7 , % g 1
cmp % g 7 , % g 1
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bne,p n % x c c , B A C K O F F _ L A B E L ( 2 f , 1 b )
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nop
retl
nop
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2 : BACKOFF_ S P I N ( % o 3 , % o 4 , 1 b )
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.size set_ b i t , . - s e t _ b i t
.globl clear_bit
.type clear_ b i t ,#f u n c t i o n
clear_bit : /* %o0=nr, %o1=addr */
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BACKOFF_ S E T U P ( % o 3 )
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srlx % o 0 , 6 , % g 1
mov 1 , % o 2
sllx % g 1 , 3 , % g 3
and % o 0 , 6 3 , % g 2
sllx % o 2 , % g 2 , % o 2
add % o 1 , % g 3 , % o 1
1 : ldx [ % o 1 ] , % g 7
andn % g 7 , % o 2 , % g 1
casx [ % o 1 ] , % g 7 , % g 1
cmp % g 7 , % g 1
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bne,p n % x c c , B A C K O F F _ L A B E L ( 2 f , 1 b )
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nop
retl
nop
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2 : BACKOFF_ S P I N ( % o 3 , % o 4 , 1 b )
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.size clear_ b i t , . - c l e a r _ b i t
.globl change_bit
.type change_ b i t ,#f u n c t i o n
change_bit : /* %o0=nr, %o1=addr */
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BACKOFF_ S E T U P ( % o 3 )
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srlx % o 0 , 6 , % g 1
mov 1 , % o 2
sllx % g 1 , 3 , % g 3
and % o 0 , 6 3 , % g 2
sllx % o 2 , % g 2 , % o 2
add % o 1 , % g 3 , % o 1
1 : ldx [ % o 1 ] , % g 7
xor % g 7 , % o 2 , % g 1
casx [ % o 1 ] , % g 7 , % g 1
cmp % g 7 , % g 1
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bne,p n % x c c , B A C K O F F _ L A B E L ( 2 f , 1 b )
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nop
retl
nop
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2 : BACKOFF_ S P I N ( % o 3 , % o 4 , 1 b )
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.size change_ b i t , . - c h a n g e _ b i t