2010-10-26 04:58:04 +04:00
/*
* sp5100_tco : TCO timer driver for sp5100 chipsets
*
* ( c ) Copyright 2009 Google Inc . , All Rights Reserved .
*
* Based on i8xx_tco . c :
* ( c ) Copyright 2000 kernel concepts < nils @ kernelconcepts . de > , All Rights
* Reserved .
* http : //www.kernelconcepts.de
*
* This program is free software ; you can redistribute it and / or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation ; either version
* 2 of the License , or ( at your option ) any later version .
*
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
* See AMD Publication 43009 " AMD SB700/710/750 Register Reference Guide " ,
* AMD Publication 45482 " AMD SB800-Series Southbridges Register
* Reference Guide "
2017-12-25 00:04:17 +03:00
* AMD Publication 48751 " BIOS and Kernel Developer’ s Guide (BKDG)
* for AMD Family 16 h Models 00 h - 0F h Processors "
* AMD Publication 51192 " AMD Bolton FCH Register Reference Guide "
* AMD Publication 52740 " BIOS and Kernel Developer’ s Guide (BKDG)
* for AMD Family 16 h Models 30 h - 3F h Processors "
2010-10-26 04:58:04 +04:00
*/
/*
* Includes , defines , variables , module parameters , . . .
*/
2012-02-16 03:06:19 +04:00
# define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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# include <linux/init.h>
# include <linux/io.h>
# include <linux/ioport.h>
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# include <linux/module.h>
# include <linux/moduleparam.h>
# include <linux/pci.h>
# include <linux/platform_device.h>
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# include <linux/types.h>
# include <linux/watchdog.h>
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# include "sp5100_tco.h"
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# define TCO_DRIVER_NAME "sp5100-tco"
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/* internal variables */
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2017-12-25 00:04:17 +03:00
enum tco_reg_layout {
sp5100 , sb800 , efch
} ;
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struct sp5100_tco {
struct watchdog_device wdd ;
void __iomem * tcobase ;
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enum tco_reg_layout tco_reg_layout ;
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} ;
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/* the watchdog platform device */
static struct platform_device * sp5100_tco_platform_device ;
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/* the associated PCI device */
static struct pci_dev * sp5100_tco_pci ;
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/* module parameters */
# define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
static int heartbeat = WATCHDOG_HEARTBEAT ; /* in seconds */
module_param ( heartbeat , int , 0 ) ;
MODULE_PARM_DESC ( heartbeat , " Watchdog heartbeat in seconds. (default= "
__MODULE_STRING ( WATCHDOG_HEARTBEAT ) " ) " ) ;
2012-03-05 19:51:11 +04:00
static bool nowayout = WATCHDOG_NOWAYOUT ;
module_param ( nowayout , bool , 0 ) ;
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
MODULE_PARM_DESC ( nowayout , " Watchdog cannot be stopped once started. "
2010-10-26 04:58:04 +04:00
" (default= " __MODULE_STRING ( WATCHDOG_NOWAYOUT ) " ) " ) ;
/*
* Some TCO specific functions
*/
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2017-12-25 00:04:17 +03:00
static enum tco_reg_layout tco_reg_layout ( struct pci_dev * dev )
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{
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if ( dev - > vendor = = PCI_VENDOR_ID_ATI & &
dev - > device = = PCI_DEVICE_ID_ATI_SBX00_SMBUS & &
dev - > revision < 0x40 ) {
return sp5100 ;
} else if ( dev - > vendor = = PCI_VENDOR_ID_AMD & &
( ( dev - > device = = PCI_DEVICE_ID_AMD_HUDSON2_SMBUS & &
dev - > revision > = 0x41 ) | |
( dev - > device = = PCI_DEVICE_ID_AMD_KERNCZ_SMBUS & &
dev - > revision > = 0x49 ) ) ) {
return efch ;
}
return sb800 ;
2016-05-03 20:15:58 +03:00
}
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static int tco_timer_start ( struct watchdog_device * wdd )
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{
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struct sp5100_tco * tco = watchdog_get_drvdata ( wdd ) ;
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u32 val ;
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val = readl ( SP5100_WDT_CONTROL ( tco - > tcobase ) ) ;
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val | = SP5100_WDT_START_STOP_BIT ;
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writel ( val , SP5100_WDT_CONTROL ( tco - > tcobase ) ) ;
return 0 ;
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}
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static int tco_timer_stop ( struct watchdog_device * wdd )
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{
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struct sp5100_tco * tco = watchdog_get_drvdata ( wdd ) ;
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u32 val ;
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val = readl ( SP5100_WDT_CONTROL ( tco - > tcobase ) ) ;
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val & = ~ SP5100_WDT_START_STOP_BIT ;
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writel ( val , SP5100_WDT_CONTROL ( tco - > tcobase ) ) ;
return 0 ;
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}
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static int tco_timer_ping ( struct watchdog_device * wdd )
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{
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struct sp5100_tco * tco = watchdog_get_drvdata ( wdd ) ;
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u32 val ;
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val = readl ( SP5100_WDT_CONTROL ( tco - > tcobase ) ) ;
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val | = SP5100_WDT_TRIGGER_BIT ;
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writel ( val , SP5100_WDT_CONTROL ( tco - > tcobase ) ) ;
return 0 ;
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}
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static int tco_timer_set_timeout ( struct watchdog_device * wdd ,
unsigned int t )
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{
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struct sp5100_tco * tco = watchdog_get_drvdata ( wdd ) ;
2010-10-26 04:58:04 +04:00
/* Write new heartbeat to watchdog */
2017-12-25 00:04:14 +03:00
writel ( t , SP5100_WDT_COUNT ( tco - > tcobase ) ) ;
wdd - > timeout = t ;
2010-10-26 04:58:04 +04:00
return 0 ;
}
2017-12-25 00:04:06 +03:00
static u8 sp5100_tco_read_pm_reg8 ( u8 index )
{
outb ( index , SP5100_IO_PM_INDEX_REG ) ;
return inb ( SP5100_IO_PM_DATA_REG ) ;
}
static void sp5100_tco_update_pm_reg8 ( u8 index , u8 reset , u8 set )
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
{
2017-12-25 00:04:06 +03:00
u8 val ;
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
2017-12-25 00:04:06 +03:00
outb ( index , SP5100_IO_PM_INDEX_REG ) ;
val = inb ( SP5100_IO_PM_DATA_REG ) ;
val & = reset ;
val | = set ;
outb ( val , SP5100_IO_PM_DATA_REG ) ;
}
2017-12-25 00:04:17 +03:00
static void tco_timer_enable ( struct sp5100_tco * tco )
2017-12-25 00:04:06 +03:00
{
2017-12-25 00:04:17 +03:00
u32 val ;
switch ( tco - > tco_reg_layout ) {
case sb800 :
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
/* For SB800 or later */
/* Set the Watchdog timer resolution to 1 sec */
2017-12-25 00:04:06 +03:00
sp5100_tco_update_pm_reg8 ( SB800_PM_WATCHDOG_CONFIG ,
0xff , SB800_PM_WATCHDOG_SECOND_RES ) ;
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
/* Enable watchdog decode bit and watchdog timer */
2017-12-25 00:04:06 +03:00
sp5100_tco_update_pm_reg8 ( SB800_PM_WATCHDOG_CONTROL ,
~ SB800_PM_WATCHDOG_DISABLE ,
SB800_PCI_WATCHDOG_DECODE_EN ) ;
2017-12-25 00:04:17 +03:00
break ;
case sp5100 :
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
/* For SP5100 or SB7x0 */
/* Enable watchdog decode bit */
pci_read_config_dword ( sp5100_tco_pci ,
SP5100_PCI_WATCHDOG_MISC_REG ,
& val ) ;
val | = SP5100_PCI_WATCHDOG_DECODE_EN ;
pci_write_config_dword ( sp5100_tco_pci ,
SP5100_PCI_WATCHDOG_MISC_REG ,
val ) ;
/* Enable Watchdog timer and set the resolution to 1 sec */
2017-12-25 00:04:06 +03:00
sp5100_tco_update_pm_reg8 ( SP5100_PM_WATCHDOG_CONTROL ,
~ SP5100_PM_WATCHDOG_DISABLE ,
SP5100_PM_WATCHDOG_SECOND_RES ) ;
2017-12-25 00:04:17 +03:00
break ;
case efch :
/* Set the Watchdog timer resolution to 1 sec and enable */
sp5100_tco_update_pm_reg8 ( EFCH_PM_DECODEEN3 ,
~ EFCH_PM_WATCHDOG_DISABLE ,
EFCH_PM_DECODEEN_SECOND_RES ) ;
break ;
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
}
}
2017-12-25 00:04:14 +03:00
static u32 sp5100_tco_read_pm_reg32 ( u8 index )
2017-12-25 00:04:06 +03:00
{
u32 val = 0 ;
int i ;
for ( i = 3 ; i > = 0 ; i - - )
val = ( val < < 8 ) + sp5100_tco_read_pm_reg8 ( index + i ) ;
return val ;
}
2017-12-25 00:04:14 +03:00
static int sp5100_tco_setupdevice ( struct device * dev ,
struct watchdog_device * wdd )
2010-10-26 04:58:04 +04:00
{
2017-12-25 00:04:14 +03:00
struct sp5100_tco * tco = watchdog_get_drvdata ( wdd ) ;
const char * dev_name ;
2017-12-25 00:04:17 +03:00
u32 mmio_addr = 0 , val ;
2017-12-25 00:04:09 +03:00
int ret ;
2010-10-26 04:58:04 +04:00
/* Request the IO ports used by this driver */
2017-12-25 00:04:08 +03:00
if ( ! request_muxed_region ( SP5100_IO_PM_INDEX_REG ,
2017-12-25 00:04:17 +03:00
SP5100_PM_IOPORTS_SIZE , " sp5100_tco " ) ) {
2017-12-25 00:04:12 +03:00
dev_err ( dev , " I/O address 0x%04x already in use \n " ,
SP5100_IO_PM_INDEX_REG ) ;
2017-12-25 00:04:09 +03:00
return - EBUSY ;
2010-10-26 04:58:04 +04:00
}
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
/*
2017-12-25 00:04:17 +03:00
* Determine type of southbridge chipset .
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
*/
2017-12-25 00:04:17 +03:00
switch ( tco - > tco_reg_layout ) {
case sp5100 :
dev_name = SP5100_DEVNAME ;
mmio_addr = sp5100_tco_read_pm_reg32 ( SP5100_PM_WATCHDOG_BASE ) &
0xfffffff8 ;
break ;
case sb800 :
dev_name = SB800_DEVNAME ;
mmio_addr = sp5100_tco_read_pm_reg32 ( SB800_PM_WATCHDOG_BASE ) &
0xfffffff8 ;
break ;
case efch :
dev_name = SB800_DEVNAME ;
val = sp5100_tco_read_pm_reg8 ( EFCH_PM_DECODEEN ) ;
if ( val & EFCH_PM_DECODEEN_WDT_TMREN )
mmio_addr = EFCH_PM_WDT_ADDR ;
break ;
default :
return - ENODEV ;
}
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
/* Check MMIO address conflict */
2017-12-25 00:04:17 +03:00
if ( ! mmio_addr | |
! devm_request_mem_region ( dev , mmio_addr , SP5100_WDT_MEM_MAP_SIZE ,
2017-12-25 00:04:14 +03:00
dev_name ) ) {
2017-12-25 00:04:17 +03:00
if ( mmio_addr )
dev_dbg ( dev , " MMIO address 0x%08x already in use \n " ,
mmio_addr ) ;
switch ( tco - > tco_reg_layout ) {
case sp5100 :
/*
* Secondly , Find the watchdog timer MMIO address
* from SBResource_MMIO register .
*/
2017-12-25 00:04:10 +03:00
/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
pci_read_config_dword ( sp5100_tco_pci ,
SP5100_SB_RESOURCE_MMIO_BASE ,
2017-12-25 00:04:17 +03:00
& mmio_addr ) ;
if ( ( mmio_addr & ( SB800_ACPI_MMIO_DECODE_EN |
SB800_ACPI_MMIO_SEL ) ) ! =
SB800_ACPI_MMIO_DECODE_EN ) {
ret = - ENODEV ;
goto unreg_region ;
}
mmio_addr & = ~ 0xFFF ;
mmio_addr + = SB800_PM_WDT_MMIO_OFFSET ;
break ;
case sb800 :
2017-12-25 00:04:10 +03:00
/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
2017-12-25 00:04:17 +03:00
mmio_addr =
sp5100_tco_read_pm_reg32 ( SB800_PM_ACPI_MMIO_EN ) ;
if ( ( mmio_addr & ( SB800_ACPI_MMIO_DECODE_EN |
SB800_ACPI_MMIO_SEL ) ) ! =
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
SB800_ACPI_MMIO_DECODE_EN ) {
2017-12-25 00:04:17 +03:00
ret = - ENODEV ;
goto unreg_region ;
}
mmio_addr & = ~ 0xFFF ;
mmio_addr + = SB800_PM_WDT_MMIO_OFFSET ;
break ;
case efch :
val = sp5100_tco_read_pm_reg8 ( EFCH_PM_ISACONTROL ) ;
if ( ! ( val & EFCH_PM_ISACONTROL_MMIOEN ) ) {
ret = - ENODEV ;
goto unreg_region ;
}
mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
EFCH_PM_ACPI_MMIO_WDT_OFFSET ;
break ;
2017-12-25 00:04:10 +03:00
}
2017-12-25 00:04:17 +03:00
dev_dbg ( dev , " Got 0x%08x from SBResource_MMIO register \n " ,
mmio_addr ) ;
if ( ! devm_request_mem_region ( dev , mmio_addr ,
SP5100_WDT_MEM_MAP_SIZE ,
2017-12-25 00:04:14 +03:00
dev_name ) ) {
2017-12-25 00:04:17 +03:00
dev_dbg ( dev , " MMIO address 0x%08x already in use \n " ,
mmio_addr ) ;
2017-12-25 00:04:10 +03:00
ret = - EBUSY ;
goto unreg_region ;
}
}
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
2017-12-25 00:04:17 +03:00
tco - > tcobase = devm_ioremap ( dev , mmio_addr , SP5100_WDT_MEM_MAP_SIZE ) ;
2017-12-25 00:04:14 +03:00
if ( ! tco - > tcobase ) {
2017-12-25 00:04:12 +03:00
dev_err ( dev , " failed to get tcobase address \n " ) ;
2017-12-25 00:04:09 +03:00
ret = - ENOMEM ;
2017-12-25 00:04:14 +03:00
goto unreg_region ;
2010-10-26 04:58:04 +04:00
}
2017-12-25 00:04:17 +03:00
dev_info ( dev , " Using 0x%08x for watchdog MMIO address \n " , mmio_addr ) ;
2010-10-26 04:58:04 +04:00
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
/* Setup the watchdog timer */
2017-12-25 00:04:17 +03:00
tco_timer_enable ( tco ) ;
2010-10-26 04:58:04 +04:00
2017-12-25 00:04:14 +03:00
val = readl ( SP5100_WDT_CONTROL ( tco - > tcobase ) ) ;
2017-12-25 00:04:16 +03:00
if ( val & SP5100_WDT_DISABLED ) {
dev_err ( dev , " Watchdog hardware is disabled \n " ) ;
ret = - ENODEV ;
goto unreg_region ;
}
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
/*
* Save WatchDogFired status , because WatchDogFired flag is
* cleared here .
*/
2017-12-25 00:04:14 +03:00
if ( val & SP5100_WDT_FIRED )
wdd - > bootstatus = WDIOF_CARDRESET ;
2017-12-25 00:04:16 +03:00
/* Set watchdog action to reset the system */
2017-12-25 00:04:13 +03:00
val & = ~ SP5100_WDT_ACTION_RESET ;
2017-12-25 00:04:14 +03:00
writel ( val , SP5100_WDT_CONTROL ( tco - > tcobase ) ) ;
2010-10-26 04:58:04 +04:00
/* Set a reasonable heartbeat before we stop the timer */
2017-12-25 00:04:14 +03:00
tco_timer_set_timeout ( wdd , wdd - > timeout ) ;
2010-10-26 04:58:04 +04:00
/*
* Stop the TCO before we change anything so we don ' t race with
* a zeroed timer .
*/
2017-12-25 00:04:14 +03:00
tco_timer_stop ( wdd ) ;
2010-10-26 04:58:04 +04:00
2017-12-25 00:04:08 +03:00
release_region ( SP5100_IO_PM_INDEX_REG , SP5100_PM_IOPORTS_SIZE ) ;
2017-12-25 00:04:10 +03:00
2017-12-25 00:04:09 +03:00
return 0 ;
2010-10-26 04:58:04 +04:00
unreg_region :
2017-12-25 00:04:06 +03:00
release_region ( SP5100_IO_PM_INDEX_REG , SP5100_PM_IOPORTS_SIZE ) ;
2017-12-25 00:04:09 +03:00
return ret ;
2010-10-26 04:58:04 +04:00
}
2017-12-25 00:04:14 +03:00
static struct watchdog_info sp5100_tco_wdt_info = {
. identity = " SP5100 TCO timer " ,
. options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE ,
} ;
static const struct watchdog_ops sp5100_tco_wdt_ops = {
. owner = THIS_MODULE ,
. start = tco_timer_start ,
. stop = tco_timer_stop ,
. ping = tco_timer_ping ,
. set_timeout = tco_timer_set_timeout ,
} ;
2017-12-25 00:04:13 +03:00
static int sp5100_tco_probe ( struct platform_device * pdev )
2010-10-26 04:58:04 +04:00
{
2017-12-25 00:04:12 +03:00
struct device * dev = & pdev - > dev ;
2017-12-25 00:04:14 +03:00
struct watchdog_device * wdd ;
struct sp5100_tco * tco ;
2010-10-26 04:58:04 +04:00
int ret ;
2017-12-25 00:04:14 +03:00
tco = devm_kzalloc ( dev , sizeof ( * tco ) , GFP_KERNEL ) ;
if ( ! tco )
return - ENOMEM ;
2017-12-25 00:04:17 +03:00
tco - > tco_reg_layout = tco_reg_layout ( sp5100_tco_pci ) ;
2017-12-25 00:04:14 +03:00
wdd = & tco - > wdd ;
wdd - > parent = dev ;
wdd - > info = & sp5100_tco_wdt_info ;
wdd - > ops = & sp5100_tco_wdt_ops ;
wdd - > timeout = WATCHDOG_HEARTBEAT ;
wdd - > min_timeout = 1 ;
wdd - > max_timeout = 0xffff ;
if ( watchdog_init_timeout ( wdd , heartbeat , NULL ) )
dev_info ( dev , " timeout value invalid, using %d \n " ,
wdd - > timeout ) ;
watchdog_set_nowayout ( wdd , nowayout ) ;
watchdog_stop_on_reboot ( wdd ) ;
watchdog_stop_on_unregister ( wdd ) ;
watchdog_set_drvdata ( wdd , tco ) ;
ret = sp5100_tco_setupdevice ( dev , wdd ) ;
2017-12-25 00:04:09 +03:00
if ( ret )
return ret ;
2010-10-26 04:58:04 +04:00
2017-12-25 00:04:14 +03:00
ret = devm_watchdog_register_device ( dev , wdd ) ;
if ( ret ) {
dev_err ( dev , " cannot register watchdog device (err=%d) \n " , ret ) ;
return ret ;
2010-10-26 04:58:04 +04:00
}
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
/* Show module parameters */
2017-12-25 00:04:14 +03:00
dev_info ( dev , " initialized. heartbeat=%d sec (nowayout=%d) \n " ,
wdd - > timeout , nowayout ) ;
2010-10-26 04:58:04 +04:00
return 0 ;
}
static struct platform_driver sp5100_tco_driver = {
2017-12-25 00:04:13 +03:00
. probe = sp5100_tco_probe ,
2010-10-26 04:58:04 +04:00
. driver = {
2017-12-25 00:04:14 +03:00
. name = TCO_DRIVER_NAME ,
2010-10-26 04:58:04 +04:00
} ,
} ;
2017-12-25 00:04:11 +03:00
/*
* Data for PCI driver interface
*
* This data only exists for exporting the supported
* PCI ids via MODULE_DEVICE_TABLE . We do not actually
* register a pci_driver , because someone else might
* want to register another driver on the same PCI id .
*/
static const struct pci_device_id sp5100_tco_pci_tbl [ ] = {
{ PCI_VENDOR_ID_ATI , PCI_DEVICE_ID_ATI_SBX00_SMBUS , PCI_ANY_ID ,
PCI_ANY_ID , } ,
{ PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_HUDSON2_SMBUS , PCI_ANY_ID ,
PCI_ANY_ID , } ,
{ PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_KERNCZ_SMBUS , PCI_ANY_ID ,
PCI_ANY_ID , } ,
{ 0 , } , /* End of list */
} ;
MODULE_DEVICE_TABLE ( pci , sp5100_tco_pci_tbl ) ;
2017-12-25 00:04:13 +03:00
static int __init sp5100_tco_init ( void )
2010-10-26 04:58:04 +04:00
{
2017-12-25 00:04:11 +03:00
struct pci_dev * dev = NULL ;
2010-10-26 04:58:04 +04:00
int err ;
2017-12-25 00:04:11 +03:00
/* Match the PCI device */
for_each_pci_dev ( dev ) {
if ( pci_match_id ( sp5100_tco_pci_tbl , dev ) ! = NULL ) {
sp5100_tco_pci = dev ;
break ;
}
}
if ( ! sp5100_tco_pci )
return - ENODEV ;
2017-12-25 00:04:14 +03:00
pr_info ( " SP5100/SB800 TCO WatchDog Timer Driver \n " ) ;
2010-10-26 04:58:04 +04:00
err = platform_driver_register ( & sp5100_tco_driver ) ;
if ( err )
return err ;
2017-12-25 00:04:14 +03:00
sp5100_tco_platform_device =
platform_device_register_simple ( TCO_DRIVER_NAME , - 1 , NULL , 0 ) ;
2010-10-26 04:58:04 +04:00
if ( IS_ERR ( sp5100_tco_platform_device ) ) {
err = PTR_ERR ( sp5100_tco_platform_device ) ;
goto unreg_platform_driver ;
}
return 0 ;
unreg_platform_driver :
platform_driver_unregister ( & sp5100_tco_driver ) ;
return err ;
}
2017-12-25 00:04:13 +03:00
static void __exit sp5100_tco_exit ( void )
2010-10-26 04:58:04 +04:00
{
platform_device_unregister ( sp5100_tco_platform_device ) ;
platform_driver_unregister ( & sp5100_tco_driver ) ;
}
2017-12-25 00:04:13 +03:00
module_init ( sp5100_tco_init ) ;
module_exit ( sp5100_tco_exit ) ;
2010-10-26 04:58:04 +04:00
MODULE_AUTHOR ( " Priyanka Gupta " ) ;
watchdog: sp5100_tco: Add SB8x0 chipset support
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2012-12-02 09:33:18 +04:00
MODULE_DESCRIPTION ( " TCO timer driver for SP5100/SB800 chipset " ) ;
2010-10-26 04:58:04 +04:00
MODULE_LICENSE ( " GPL " ) ;