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linux/arch/mips/include/asm/irq_gt641xx.h

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option [no]_[pad]_[ctrl] any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 176 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154040.652910950@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 15:51:31 +02:00
/* SPDX-License-Identifier: GPL-2.0-or-later */
[MIPS] Add GT641xx IRQ routines. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-13 23:51:26 +09:00
/*
* Galileo/Marvell GT641xx IRQ definitions.
*
Update Yoichi Yuasa's e-mail address Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03 00:39:38 +09:00
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
[MIPS] Add GT641xx IRQ routines. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-13 23:51:26 +09:00
*/
#ifndef _ASM_IRQ_GT641XX_H
#define _ASM_IRQ_GT641XX_H
#ifndef GT641XX_IRQ_BASE
#define GT641XX_IRQ_BASE 8
#endif
#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1)
#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2)
#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3)
#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4)
#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5)
#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6)
#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7)
#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8)
#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9)
#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10)
#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11)
#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12)
#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13)
#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14)
#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15)
#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16)
#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17)
#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18)
#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19)
#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20)
#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21)
#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22)
#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23)
#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24)
#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25)
#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26)
#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27)
#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28)
#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29)
extern void gt641xx_irq_dispatch(void);
extern void gt641xx_irq_init(void);
#endif /* _ASM_IRQ_GT641XX_H */
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