[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
/*
2008-03-27 21:51:41 +03:00
* arch / arm / mach - orion5x / common . c
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
*
2008-03-27 21:51:41 +03:00
* Core functions for Marvell Orion 5 x SoCs
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
*
* Maintainer : Tzachi Perelstein < tzachi @ marvell . com >
*
2008-03-27 21:51:41 +03:00
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed " as is " without any
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
* warranty of any kind , whether express or implied .
*/
# include <linux/kernel.h>
# include <linux/init.h>
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# include <linux/platform_device.h>
# include <linux/serial_8250.h>
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# include <linux/mbus.h>
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# include <linux/mv643xx_eth.h>
2007-11-12 10:51:36 +03:00
# include <linux/mv643xx_i2c.h>
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# include <linux/ata_platform.h>
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
# include <asm/page.h>
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# include <asm/setup.h>
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# include <asm/timex.h>
2008-02-29 23:12:57 +03:00
# include <asm/mach/arch.h>
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
# include <asm/mach/map.h>
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# include <asm/mach/time.h>
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# include <asm/arch/hardware.h>
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# include <asm/arch/orion5x.h>
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# include <asm/plat-orion/ehci-orion.h>
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# include <asm/plat-orion/orion_nand.h>
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# include <asm/plat-orion/time.h>
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
# include "common.h"
/*****************************************************************************
* I / O Address Mapping
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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static struct map_desc orion5x_io_desc [ ] __initdata = {
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
{
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. virtual = ORION5X_REGS_VIRT_BASE ,
. pfn = __phys_to_pfn ( ORION5X_REGS_PHYS_BASE ) ,
. length = ORION5X_REGS_SIZE ,
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
. type = MT_DEVICE
} ,
{
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. virtual = ORION5X_PCIE_IO_VIRT_BASE ,
. pfn = __phys_to_pfn ( ORION5X_PCIE_IO_PHYS_BASE ) ,
. length = ORION5X_PCIE_IO_SIZE ,
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
. type = MT_DEVICE
} ,
{
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. virtual = ORION5X_PCI_IO_VIRT_BASE ,
. pfn = __phys_to_pfn ( ORION5X_PCI_IO_PHYS_BASE ) ,
. length = ORION5X_PCI_IO_SIZE ,
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
. type = MT_DEVICE
} ,
{
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. virtual = ORION5X_PCIE_WA_VIRT_BASE ,
. pfn = __phys_to_pfn ( ORION5X_PCIE_WA_PHYS_BASE ) ,
. length = ORION5X_PCIE_WA_SIZE ,
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
. type = MT_DEVICE
} ,
} ;
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void __init orion5x_map_io ( void )
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
{
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iotable_init ( orion5x_io_desc , ARRAY_SIZE ( orion5x_io_desc ) ) ;
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
}
2007-10-23 23:14:42 +04:00
2007-10-23 23:14:42 +04:00
/*****************************************************************************
* UART
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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static struct resource orion5x_uart_resources [ ] = {
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{
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. start = UART0_PHYS_BASE ,
. end = UART0_PHYS_BASE + 0xff ,
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. flags = IORESOURCE_MEM ,
} ,
{
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. start = IRQ_ORION5X_UART0 ,
. end = IRQ_ORION5X_UART0 ,
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. flags = IORESOURCE_IRQ ,
} ,
{
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. start = UART1_PHYS_BASE ,
. end = UART1_PHYS_BASE + 0xff ,
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. flags = IORESOURCE_MEM ,
} ,
{
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. start = IRQ_ORION5X_UART1 ,
. end = IRQ_ORION5X_UART1 ,
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. flags = IORESOURCE_IRQ ,
} ,
} ;
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static struct plat_serial8250_port orion5x_uart_data [ ] = {
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{
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. mapbase = UART0_PHYS_BASE ,
. membase = ( char * ) UART0_VIRT_BASE ,
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. irq = IRQ_ORION5X_UART0 ,
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. flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF ,
. iotype = UPIO_MEM ,
. regshift = 2 ,
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. uartclk = ORION5X_TCLK ,
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} ,
{
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. mapbase = UART1_PHYS_BASE ,
. membase = ( char * ) UART1_VIRT_BASE ,
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. irq = IRQ_ORION5X_UART1 ,
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. flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF ,
. iotype = UPIO_MEM ,
. regshift = 2 ,
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. uartclk = ORION5X_TCLK ,
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} ,
{ } ,
} ;
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static struct platform_device orion5x_uart = {
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. name = " serial8250 " ,
. id = PLAT8250_DEV_PLATFORM ,
. dev = {
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. platform_data = orion5x_uart_data ,
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} ,
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. resource = orion5x_uart_resources ,
. num_resources = ARRAY_SIZE ( orion5x_uart_resources ) ,
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} ;
/*******************************************************************************
* USB Controller - 2 interfaces
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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static struct resource orion5x_ehci0_resources [ ] = {
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{
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. start = ORION5X_USB0_PHYS_BASE ,
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. end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1 ,
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. flags = IORESOURCE_MEM ,
} ,
{
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. start = IRQ_ORION5X_USB0_CTRL ,
. end = IRQ_ORION5X_USB0_CTRL ,
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. flags = IORESOURCE_IRQ ,
} ,
} ;
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static struct resource orion5x_ehci1_resources [ ] = {
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{
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. start = ORION5X_USB1_PHYS_BASE ,
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. end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1 ,
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. flags = IORESOURCE_MEM ,
} ,
{
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. start = IRQ_ORION5X_USB1_CTRL ,
. end = IRQ_ORION5X_USB1_CTRL ,
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. flags = IORESOURCE_IRQ ,
} ,
} ;
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static struct orion_ehci_data orion5x_ehci_data = {
. dram = & orion5x_mbus_dram_info ,
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} ;
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static u64 ehci_dmamask = 0xffffffffUL ;
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static struct platform_device orion5x_ehci0 = {
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. name = " orion-ehci " ,
. id = 0 ,
. dev = {
. dma_mask = & ehci_dmamask ,
. coherent_dma_mask = 0xffffffff ,
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. platform_data = & orion5x_ehci_data ,
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} ,
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. resource = orion5x_ehci0_resources ,
. num_resources = ARRAY_SIZE ( orion5x_ehci0_resources ) ,
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} ;
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static struct platform_device orion5x_ehci1 = {
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. name = " orion-ehci " ,
. id = 1 ,
. dev = {
. dma_mask = & ehci_dmamask ,
. coherent_dma_mask = 0xffffffff ,
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. platform_data = & orion5x_ehci_data ,
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} ,
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. resource = orion5x_ehci1_resources ,
. num_resources = ARRAY_SIZE ( orion5x_ehci1_resources ) ,
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} ;
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/*****************************************************************************
* Gigabit Ethernet port
* ( The Orion and Discovery ( MV643xx ) families use the same Ethernet driver )
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
. dram = & orion5x_mbus_dram_info ,
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. t_clk = ORION5X_TCLK ,
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} ;
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static struct resource orion5x_eth_shared_resources [ ] = {
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{
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. start = ORION5X_ETH_PHYS_BASE + 0x2000 ,
. end = ORION5X_ETH_PHYS_BASE + 0x3fff ,
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. flags = IORESOURCE_MEM ,
} ,
} ;
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static struct platform_device orion5x_eth_shared = {
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. name = MV643XX_ETH_SHARED_NAME ,
. id = 0 ,
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. dev = {
. platform_data = & orion5x_eth_shared_data ,
} ,
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. num_resources = 1 ,
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. resource = orion5x_eth_shared_resources ,
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} ;
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static struct resource orion5x_eth_resources [ ] = {
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{
. name = " eth irq " ,
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. start = IRQ_ORION5X_ETH_SUM ,
. end = IRQ_ORION5X_ETH_SUM ,
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. flags = IORESOURCE_IRQ ,
}
} ;
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static struct platform_device orion5x_eth = {
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. name = MV643XX_ETH_NAME ,
. id = 0 ,
. num_resources = 1 ,
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. resource = orion5x_eth_resources ,
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} ;
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void __init orion5x_eth_init ( struct mv643xx_eth_platform_data * eth_data )
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{
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eth_data - > shared = & orion5x_eth_shared ;
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orion5x_eth . dev . platform_data = eth_data ;
2008-04-24 03:27:02 +04:00
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platform_device_register ( & orion5x_eth_shared ) ;
platform_device_register ( & orion5x_eth ) ;
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}
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/*****************************************************************************
* I2C controller
* ( The Orion and Discovery ( MV643xx ) families share the same I2C controller )
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
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. freq_m = 8 , /* assumes 166 MHz TCLK */
. freq_n = 3 ,
. timeout = 1000 , /* Default timeout of 1 second */
} ;
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static struct resource orion5x_i2c_resources [ ] = {
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{
. name = " i2c base " ,
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. start = I2C_PHYS_BASE ,
. end = I2C_PHYS_BASE + 0x20 - 1 ,
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. flags = IORESOURCE_MEM ,
} ,
{
. name = " i2c irq " ,
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. start = IRQ_ORION5X_I2C ,
. end = IRQ_ORION5X_I2C ,
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. flags = IORESOURCE_IRQ ,
} ,
} ;
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static struct platform_device orion5x_i2c = {
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. name = MV64XXX_I2C_CTLR_NAME ,
. id = 0 ,
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. num_resources = ARRAY_SIZE ( orion5x_i2c_resources ) ,
. resource = orion5x_i2c_resources ,
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. dev = {
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. platform_data = & orion5x_i2c_pdata ,
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} ,
} ;
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/*****************************************************************************
* Sata port
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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static struct resource orion5x_sata_resources [ ] = {
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{
. name = " sata base " ,
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. start = ORION5X_SATA_PHYS_BASE ,
. end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1 ,
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. flags = IORESOURCE_MEM ,
} ,
{
. name = " sata irq " ,
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. start = IRQ_ORION5X_SATA ,
. end = IRQ_ORION5X_SATA ,
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. flags = IORESOURCE_IRQ ,
} ,
} ;
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static struct platform_device orion5x_sata = {
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. name = " sata_mv " ,
. id = 0 ,
. dev = {
. coherent_dma_mask = 0xffffffff ,
} ,
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. num_resources = ARRAY_SIZE ( orion5x_sata_resources ) ,
. resource = orion5x_sata_resources ,
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} ;
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void __init orion5x_sata_init ( struct mv_sata_platform_data * sata_data )
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{
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sata_data - > dram = & orion5x_mbus_dram_info ;
orion5x_sata . dev . platform_data = sata_data ;
platform_device_register ( & orion5x_sata ) ;
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}
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/*****************************************************************************
* Time handling
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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static void orion5x_timer_init ( void )
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{
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orion_time_init ( IRQ_ORION5X_BRIDGE , ORION5X_TCLK ) ;
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}
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struct sys_timer orion5x_timer = {
. init = orion5x_timer_init ,
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} ;
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/*****************************************************************************
* General
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/*
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* Identify device ID and rev from PCIe configuration header space ' 0 ' .
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*/
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static void __init orion5x_id ( u32 * dev , u32 * rev , char * * dev_name )
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{
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orion5x_pcie_id ( dev , rev ) ;
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if ( * dev = = MV88F5281_DEV_ID ) {
if ( * rev = = MV88F5281_REV_D2 ) {
* dev_name = " MV88F5281-D2 " ;
} else if ( * rev = = MV88F5281_REV_D1 ) {
* dev_name = " MV88F5281-D1 " ;
} else {
* dev_name = " MV88F5281-Rev-Unsupported " ;
}
} else if ( * dev = = MV88F5182_DEV_ID ) {
if ( * rev = = MV88F5182_REV_A2 ) {
* dev_name = " MV88F5182-A2 " ;
} else {
* dev_name = " MV88F5182-Rev-Unsupported " ;
}
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} else if ( * dev = = MV88F5181_DEV_ID ) {
if ( * rev = = MV88F5181_REV_B1 ) {
* dev_name = " MV88F5181-Rev-B1 " ;
} else {
* dev_name = " MV88F5181-Rev-Unsupported " ;
}
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} else {
* dev_name = " Device-Unknown " ;
}
}
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void __init orion5x_init ( void )
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{
char * dev_name ;
u32 dev , rev ;
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orion5x_id ( & dev , & rev , & dev_name ) ;
printk ( KERN_INFO " Orion ID: %s. TCLK=%d. \n " , dev_name , ORION5X_TCLK ) ;
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/*
* Setup Orion address map
*/
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orion5x_setup_cpu_mbus_bridge ( ) ;
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/*
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* Register devices .
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*/
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platform_device_register ( & orion5x_uart ) ;
platform_device_register ( & orion5x_ehci0 ) ;
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if ( dev = = MV88F5182_DEV_ID )
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platform_device_register ( & orion5x_ehci1 ) ;
platform_device_register ( & orion5x_i2c ) ;
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}
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/*
* Many orion - based systems have buggy bootloader implementations .
* This is a common fixup for bogus memory tags .
*/
void __init tag_fixup_mem32 ( struct machine_desc * mdesc , struct tag * t ,
char * * from , struct meminfo * meminfo )
{
for ( ; t - > hdr . size ; t = tag_next ( t ) )
if ( t - > hdr . tag = = ATAG_MEM & &
( ! t - > u . mem . size | | t - > u . mem . size & ~ PAGE_MASK | |
t - > u . mem . start & ~ PAGE_MASK ) ) {
printk ( KERN_WARNING
" Clearing invalid memory bank %dKB@0x%08x \n " ,
t - > u . mem . size / 1024 , t - > u . mem . start ) ;
t - > hdr . tag = 0 ;
}
}