2008-03-18 10:02:50 +02:00
# ifndef __ARCH_ASM_MACH_OMAP2_CM_H
# define __ARCH_ASM_MACH_OMAP2_CM_H
/*
* OMAP2 / 3 Clock Management ( CM ) register definitions
*
2009-12-08 18:24:50 -07:00
* Copyright ( C ) 2007 - 2009 Texas Instruments , Inc .
* Copyright ( C ) 2007 - 2009 Nokia Corporation
2008-03-18 10:02:50 +02:00
*
* Written by Paul Walmsley
*
* This program is free software ; you can redistribute it and / or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation .
*/
# include "prcm-common.h"
# define OMAP2420_CM_REGADDR(module, reg) \
2009-10-19 15:25:31 -07:00
OMAP2_L4_IO_ADDRESS ( OMAP2420_CM_BASE + ( module ) + ( reg ) )
2008-03-18 10:02:50 +02:00
# define OMAP2430_CM_REGADDR(module, reg) \
2009-10-19 15:25:31 -07:00
OMAP2_L4_IO_ADDRESS ( OMAP2430_CM_BASE + ( module ) + ( reg ) )
2008-03-18 10:02:50 +02:00
# define OMAP34XX_CM_REGADDR(module, reg) \
2009-10-19 15:25:31 -07:00
OMAP2_L4_IO_ADDRESS ( OMAP3430_CM_BASE + ( module ) + ( reg ) )
2009-12-08 18:24:50 -07:00
# define OMAP44XX_CM1_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS ( OMAP4430_CM1_BASE + ( module ) + ( reg ) )
# define OMAP44XX_CM2_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS ( OMAP4430_CM2_BASE + ( module ) + ( reg ) )
# include "cm44xx.h"
2008-03-18 10:02:50 +02:00
/*
* Architecture - specific global CM registers
* Use cm_ { read , write } _reg ( ) with these registers .
* These registers appear once per CM module .
*/
2009-06-09 11:45:30 -07:00
# define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
# define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
# define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
2008-03-18 10:02:50 +02:00
2009-05-25 11:26:42 -07:00
# define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
2008-03-18 10:02:50 +02:00
# define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
/*
* Module specific CM registers from CM_BASE + domain offset
* Use cm_ { read , write } _mod_reg ( ) with these registers .
* These register offsets generally appear in more than one PRCM submodule .
*/
/* Common between 24xx and 34xx */
# define CM_FCLKEN 0x0000
# define CM_FCLKEN1 CM_FCLKEN
# define CM_CLKEN CM_FCLKEN
# define CM_ICLKEN 0x0010
# define CM_ICLKEN1 CM_ICLKEN
# define CM_ICLKEN2 0x0014
# define CM_ICLKEN3 0x0018
# define CM_IDLEST 0x0020
# define CM_IDLEST1 CM_IDLEST
# define CM_IDLEST2 0x0024
# define CM_AUTOIDLE 0x0030
# define CM_AUTOIDLE1 CM_AUTOIDLE
# define CM_AUTOIDLE2 0x0034
# define CM_AUTOIDLE3 0x0038
# define CM_CLKSEL 0x0040
# define CM_CLKSEL1 CM_CLKSEL
# define CM_CLKSEL2 0x0044
2010-01-26 20:12:53 -07:00
# define OMAP2_CM_CLKSTCTRL 0x0048
# define OMAP4_CM_CLKSTCTRL 0x0000
2008-03-18 10:02:50 +02:00
/* Architecture-specific registers */
# define OMAP24XX_CM_FCLKEN2 0x0004
# define OMAP24XX_CM_ICLKEN4 0x001c
# define OMAP24XX_CM_AUTOIDLE4 0x003c
# define OMAP2430_CM_IDLEST3 0x0028
# define OMAP3430_CM_CLKEN_PLL 0x0004
# define OMAP3430ES2_CM_CLKEN2 0x0004
# define OMAP3430ES2_CM_FCLKEN3 0x0008
# define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
# define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
2008-07-03 12:24:45 +03:00
# define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
2008-03-18 10:02:50 +02:00
# define OMAP3430_CM_CLKSEL1 CM_CLKSEL
# define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
# define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
# define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
2010-01-26 20:12:53 -07:00
# define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
2008-03-18 10:02:50 +02:00
# define OMAP3430_CM_CLKSTST 0x004c
# define OMAP3430ES2_CM_CLKSEL4 0x004c
# define OMAP3430ES2_CM_CLKSEL5 0x0050
# define OMAP3430_CM_CLKSEL2_EMU 0x0050
# define OMAP3430_CM_CLKSEL3_EMU 0x0054
2009-12-08 18:24:50 -07:00
/* CM2.CEFUSE_CM2 register offsets */
2008-03-18 10:02:50 +02:00
2009-12-09 00:01:44 +05:30
/* OMAP4 modulemode control */
# define OMAP4430_MODULEMODE_HWCTRL 0
# define OMAP4430_MODULEMODE_SWCTRL 1
2008-03-18 10:02:50 +02:00
/* Clock management domain register get/set */
# ifndef __ASSEMBLER__
2008-07-03 12:24:44 +03:00
extern u32 cm_read_mod_reg ( s16 module , u16 idx ) ;
extern void cm_write_mod_reg ( u32 val , s16 module , u16 idx ) ;
2008-07-03 12:24:44 +03:00
extern u32 cm_rmw_mod_reg_bits ( u32 mask , u32 bits , s16 module , s16 idx ) ;
2009-09-03 20:14:02 +03:00
extern int omap2_cm_wait_module_ready ( s16 prcm_mod , u8 idlest_id ,
u8 idlest_shift ) ;
2010-05-20 12:31:08 -06:00
extern int omap4_cm_wait_module_ready ( void __iomem * clkctrl_reg ) ;
2009-09-03 20:14:02 +03:00
2008-07-03 12:24:44 +03:00
static inline u32 cm_set_mod_reg_bits ( u32 bits , s16 module , s16 idx )
{
return cm_rmw_mod_reg_bits ( bits , bits , module , idx ) ;
}
static inline u32 cm_clear_mod_reg_bits ( u32 bits , s16 module , s16 idx )
{
return cm_rmw_mod_reg_bits ( bits , 0x0 , module , idx ) ;
}
2008-07-03 12:24:44 +03:00
2008-03-18 10:02:50 +02:00
# endif
/* CM register bits shared between 24XX and 3430 */
/* CM_CLKSEL_GFX */
# define OMAP_CLKSEL_GFX_SHIFT 0
# define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
/* CM_ICLKEN_GFX */
# define OMAP_EN_GFX_SHIFT 0
2010-05-18 18:40:23 -06:00
# define OMAP_EN_GFX_MASK (1 << 0)
2008-03-18 10:02:50 +02:00
/* CM_IDLEST_GFX */
2010-05-18 18:40:23 -06:00
# define OMAP_ST_GFX_MASK (1 << 0)
2008-03-18 10:02:50 +02:00
2010-02-24 12:05:54 -07:00
/* CM_IDLEST indicator */
# define OMAP24XX_CM_IDLEST_VAL 0
# define OMAP34XX_CM_IDLEST_VAL 1
2008-03-18 10:02:50 +02:00
2010-05-20 12:31:08 -06:00
/*
* MAX_MODULE_READY_TIME : max duration in microseconds to wait for the
* PRCM to request that a module exit the inactive state in the case of
* OMAP2 & 3.
* In the case of OMAP4 this is the max duration in microseconds for the
* module to reach the functionnal state from an inactive state .
*/
# define MAX_MODULE_READY_TIME 2000
2008-03-18 10:02:50 +02:00
# endif