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/*
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* arch / arm / mach - ixp4xx / include / mach / io . h
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*
* Author : Deepak Saxena < dsaxena @ plexity . net >
*
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* Copyright ( C ) 2002 - 2005 MontaVista Software , Inc .
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*
* This program is free software ; you can redistribute it and / or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation .
*/
# ifndef __ASM_ARM_ARCH_IO_H
# define __ASM_ARM_ARCH_IO_H
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# include <linux/bitops.h>
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# include <mach/hardware.h>
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extern int ( * ixp4xx_pci_read ) ( u32 addr , u32 cmd , u32 * data ) ;
extern int ixp4xx_pci_write ( u32 addr , u32 cmd , u32 data ) ;
/*
* IXP4xx provides two methods of accessing PCI memory space :
*
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* 1 ) A direct mapped window from 0x48000000 to 0x4BFFFFFF ( 64 MB ) .
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* To access PCI via this space , we simply ioremap ( ) the BAR
* into the kernel and we can use the standard read [ bwl ] / write [ bwl ]
* macros . This is the preffered method due to speed but it
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* limits the system to just 64 MB of PCI memory . This can be
* problematic if using video cards and other memory - heavy targets .
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*
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* 2 ) If > 64 MB of memory space is required , the IXP4xx can use indirect
* registers to access the whole 4 GB of PCI memory space ( as we do below
* for I / O transactions ) . This allows currently for up to 1 GB ( 0x10000000
* to 0x4FFFFFFF ) of memory on the bus . The disadvantage of this is that
* every PCI access requires three local register accesses plus a spinlock ,
* but in some cases the performance hit is acceptable . In addition , you
* cannot mmap ( ) PCI devices in this case .
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*/
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# ifdef CONFIG_IXP4XX_INDIRECT_PCI
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/*
* In the case of using indirect PCI , we simply return the actual PCI
* address and our read / write implementation use that to drive the
* access registers . If something outside of PCI is ioremap ' d , we
* fallback to the default .
*/
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static inline int is_pci_memory ( u32 addr )
{
return ( addr > = PCIBIOS_MIN_MEM ) & & ( addr < = 0x4FFFFFFF ) ;
}
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# define writeb(v, p) __indirect_writeb(v, p)
# define writew(v, p) __indirect_writew(v, p)
# define writel(v, p) __indirect_writel(v, p)
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# define writesb(p, v, l) __indirect_writesb(p, v, l)
# define writesw(p, v, l) __indirect_writesw(p, v, l)
# define writesl(p, v, l) __indirect_writesl(p, v, l)
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# define readb(p) __indirect_readb(p)
# define readw(p) __indirect_readw(p)
# define readl(p) __indirect_readl(p)
# define readsb(p, v, l) __indirect_readsb(p, v, l)
# define readsw(p, v, l) __indirect_readsw(p, v, l)
# define readsl(p, v, l) __indirect_readsl(p, v, l)
static inline void __indirect_writeb ( u8 value , volatile void __iomem * p )
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{
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u32 addr = ( u32 ) p ;
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u32 n , byte_enables , data ;
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if ( ! is_pci_memory ( addr ) ) {
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__raw_writeb ( value , addr ) ;
return ;
}
n = addr % 4 ;
byte_enables = ( 0xf & ~ BIT ( n ) ) < < IXP4XX_PCI_NP_CBE_BESL ;
data = value < < ( 8 * n ) ;
ixp4xx_pci_write ( addr , byte_enables | NP_CMD_MEMWRITE , data ) ;
}
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static inline void __indirect_writesb ( volatile void __iomem * bus_addr ,
const u8 * vaddr , int count )
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{
while ( count - - )
writeb ( * vaddr + + , bus_addr ) ;
}
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static inline void __indirect_writew ( u16 value , volatile void __iomem * p )
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{
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u32 addr = ( u32 ) p ;
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u32 n , byte_enables , data ;
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if ( ! is_pci_memory ( addr ) ) {
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__raw_writew ( value , addr ) ;
return ;
}
n = addr % 4 ;
byte_enables = ( 0xf & ~ ( BIT ( n ) | BIT ( n + 1 ) ) ) < < IXP4XX_PCI_NP_CBE_BESL ;
data = value < < ( 8 * n ) ;
ixp4xx_pci_write ( addr , byte_enables | NP_CMD_MEMWRITE , data ) ;
}
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static inline void __indirect_writesw ( volatile void __iomem * bus_addr ,
const u16 * vaddr , int count )
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{
while ( count - - )
writew ( * vaddr + + , bus_addr ) ;
}
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static inline void __indirect_writel ( u32 value , volatile void __iomem * p )
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{
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u32 addr = ( __force u32 ) p ;
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if ( ! is_pci_memory ( addr ) ) {
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__raw_writel ( value , p ) ;
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return ;
}
ixp4xx_pci_write ( addr , NP_CMD_MEMWRITE , value ) ;
}
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static inline void __indirect_writesl ( volatile void __iomem * bus_addr ,
const u32 * vaddr , int count )
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{
while ( count - - )
writel ( * vaddr + + , bus_addr ) ;
}
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static inline unsigned char __indirect_readb ( const volatile void __iomem * p )
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{
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u32 addr = ( u32 ) p ;
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u32 n , byte_enables , data ;
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if ( ! is_pci_memory ( addr ) )
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return __raw_readb ( addr ) ;
n = addr % 4 ;
byte_enables = ( 0xf & ~ BIT ( n ) ) < < IXP4XX_PCI_NP_CBE_BESL ;
if ( ixp4xx_pci_read ( addr , byte_enables | NP_CMD_MEMREAD , & data ) )
return 0xff ;
return data > > ( 8 * n ) ;
}
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static inline void __indirect_readsb ( const volatile void __iomem * bus_addr ,
u8 * vaddr , u32 count )
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{
while ( count - - )
* vaddr + + = readb ( bus_addr ) ;
}
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static inline unsigned short __indirect_readw ( const volatile void __iomem * p )
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{
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u32 addr = ( u32 ) p ;
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u32 n , byte_enables , data ;
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if ( ! is_pci_memory ( addr ) )
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return __raw_readw ( addr ) ;
n = addr % 4 ;
byte_enables = ( 0xf & ~ ( BIT ( n ) | BIT ( n + 1 ) ) ) < < IXP4XX_PCI_NP_CBE_BESL ;
if ( ixp4xx_pci_read ( addr , byte_enables | NP_CMD_MEMREAD , & data ) )
return 0xffff ;
return data > > ( 8 * n ) ;
}
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static inline void __indirect_readsw ( const volatile void __iomem * bus_addr ,
u16 * vaddr , u32 count )
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{
while ( count - - )
* vaddr + + = readw ( bus_addr ) ;
}
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static inline unsigned long __indirect_readl ( const volatile void __iomem * p )
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{
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u32 addr = ( __force u32 ) p ;
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u32 data ;
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if ( ! is_pci_memory ( addr ) )
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return __raw_readl ( p ) ;
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if ( ixp4xx_pci_read ( addr , NP_CMD_MEMREAD , & data ) )
return 0xffffffff ;
return data ;
}
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static inline void __indirect_readsl ( const volatile void __iomem * bus_addr ,
u32 * vaddr , u32 count )
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{
while ( count - - )
* vaddr + + = readl ( bus_addr ) ;
}
/*
* We can use the built - in functions b / c they end up calling writeb / readb
*/
# define memset_io(c,v,l) _memset_io((c),(v),(l))
# define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
# define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
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# endif /* CONFIG_IXP4XX_INDIRECT_PCI */
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# ifndef CONFIG_PCI
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# define __io(v) __typesafe_io(v)
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# else
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/*
* IXP4xx does not have a transparent cpu - > PCI I / O translation
* window . Instead , it has a set of registers that must be tweaked
* with the proper byte lanes , command types , and address for the
* transaction . This means that we need to override the default
* I / O functions .
*/
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static inline void outb ( u8 value , u32 addr )
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{
u32 n , byte_enables , data ;
n = addr % 4 ;
byte_enables = ( 0xf & ~ BIT ( n ) ) < < IXP4XX_PCI_NP_CBE_BESL ;
data = value < < ( 8 * n ) ;
ixp4xx_pci_write ( addr , byte_enables | NP_CMD_IOWRITE , data ) ;
}
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static inline void outsb ( u32 io_addr , const u8 * vaddr , u32 count )
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{
while ( count - - )
outb ( * vaddr + + , io_addr ) ;
}
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static inline void outw ( u16 value , u32 addr )
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{
u32 n , byte_enables , data ;
n = addr % 4 ;
byte_enables = ( 0xf & ~ ( BIT ( n ) | BIT ( n + 1 ) ) ) < < IXP4XX_PCI_NP_CBE_BESL ;
data = value < < ( 8 * n ) ;
ixp4xx_pci_write ( addr , byte_enables | NP_CMD_IOWRITE , data ) ;
}
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static inline void outsw ( u32 io_addr , const u16 * vaddr , u32 count )
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{
while ( count - - )
outw ( cpu_to_le16 ( * vaddr + + ) , io_addr ) ;
}
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static inline void outl ( u32 value , u32 addr )
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{
ixp4xx_pci_write ( addr , NP_CMD_IOWRITE , value ) ;
}
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static inline void outsl ( u32 io_addr , const u32 * vaddr , u32 count )
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{
while ( count - - )
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outl ( cpu_to_le32 ( * vaddr + + ) , io_addr ) ;
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}
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static inline u8 inb ( u32 addr )
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{
u32 n , byte_enables , data ;
n = addr % 4 ;
byte_enables = ( 0xf & ~ BIT ( n ) ) < < IXP4XX_PCI_NP_CBE_BESL ;
if ( ixp4xx_pci_read ( addr , byte_enables | NP_CMD_IOREAD , & data ) )
return 0xff ;
return data > > ( 8 * n ) ;
}
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static inline void insb ( u32 io_addr , u8 * vaddr , u32 count )
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{
while ( count - - )
* vaddr + + = inb ( io_addr ) ;
}
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static inline u16 inw ( u32 addr )
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{
u32 n , byte_enables , data ;
n = addr % 4 ;
byte_enables = ( 0xf & ~ ( BIT ( n ) | BIT ( n + 1 ) ) ) < < IXP4XX_PCI_NP_CBE_BESL ;
if ( ixp4xx_pci_read ( addr , byte_enables | NP_CMD_IOREAD , & data ) )
return 0xffff ;
return data > > ( 8 * n ) ;
}
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static inline void insw ( u32 io_addr , u16 * vaddr , u32 count )
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{
while ( count - - )
* vaddr + + = le16_to_cpu ( inw ( io_addr ) ) ;
}
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static inline u32 inl ( u32 addr )
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{
u32 data ;
if ( ixp4xx_pci_read ( addr , NP_CMD_IOREAD , & data ) )
return 0xffffffff ;
return data ;
}
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static inline void insl ( u32 io_addr , u32 * vaddr , u32 count )
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{
while ( count - - )
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* vaddr + + = le32_to_cpu ( inl ( io_addr ) ) ;
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}
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# define PIO_OFFSET 0x10000UL
# define PIO_MASK 0x0ffffUL
# define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
( ( unsigned long ) p < = ( PIO_MASK + PIO_OFFSET ) ) )
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# define ioread8(p) ioread8(p)
static inline unsigned int ioread8 ( const void __iomem * addr )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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return ( unsigned int ) inb ( port & PIO_MASK ) ;
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else
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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return ( unsigned int ) __raw_readb ( addr ) ;
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# else
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return ( unsigned int ) __indirect_readb ( addr ) ;
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# endif
}
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# define ioread8_rep(p, v, c) ioread8_rep(p, v, c)
static inline void ioread8_rep ( const void __iomem * addr , void * vaddr , u32 count )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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insb ( port & PIO_MASK , vaddr , count ) ;
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else
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_readsb ( addr , vaddr , count ) ;
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# else
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__indirect_readsb ( addr , vaddr , count ) ;
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# endif
}
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# define ioread16(p) ioread16(p)
static inline unsigned int ioread16 ( const void __iomem * addr )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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return ( unsigned int ) inw ( port & PIO_MASK ) ;
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else
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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return le16_to_cpu ( ( __force __le16 ) __raw_readw ( addr ) ) ;
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# else
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return ( unsigned int ) __indirect_readw ( addr ) ;
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# endif
}
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# define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
static inline void ioread16_rep ( const void __iomem * addr , void * vaddr ,
u32 count )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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insw ( port & PIO_MASK , vaddr , count ) ;
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else
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_readsw ( addr , vaddr , count ) ;
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# else
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__indirect_readsw ( addr , vaddr , count ) ;
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# endif
}
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# define ioread32(p) ioread32(p)
static inline unsigned int ioread32 ( const void __iomem * addr )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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return ( unsigned int ) inl ( port & PIO_MASK ) ;
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else {
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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return le32_to_cpu ( ( __force __le32 ) __raw_readl ( addr ) ) ;
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# else
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return ( unsigned int ) __indirect_readl ( addr ) ;
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# endif
}
}
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# define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
static inline void ioread32_rep ( const void __iomem * addr , void * vaddr ,
u32 count )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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insl ( port & PIO_MASK , vaddr , count ) ;
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else
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_readsl ( addr , vaddr , count ) ;
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# else
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__indirect_readsl ( addr , vaddr , count ) ;
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# endif
}
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# define iowrite8(v, p) iowrite8(v, p)
static inline void iowrite8 ( u8 value , void __iomem * addr )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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outb ( value , port & PIO_MASK ) ;
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else
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_writeb ( value , addr ) ;
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# else
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__indirect_writeb ( value , addr ) ;
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# endif
}
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# define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c)
static inline void iowrite8_rep ( void __iomem * addr , const void * vaddr ,
u32 count )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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outsb ( port & PIO_MASK , vaddr , count ) ;
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else
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# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_writesb ( addr , vaddr , count ) ;
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# else
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__indirect_writesb ( addr , vaddr , count ) ;
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# endif
}
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# define iowrite16(v, p) iowrite16(v, p)
static inline void iowrite16 ( u16 value , void __iomem * addr )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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outw ( value , port & PIO_MASK ) ;
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else
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_writew ( cpu_to_le16 ( value ) , addr ) ;
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# else
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__indirect_writew ( value , addr ) ;
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# endif
}
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# define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
static inline void iowrite16_rep ( void __iomem * addr , const void * vaddr ,
u32 count )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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outsw ( port & PIO_MASK , vaddr , count ) ;
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else
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# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_writesw ( addr , vaddr , count ) ;
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# else
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__indirect_writesw ( addr , vaddr , count ) ;
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# endif
}
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# define iowrite32(v, p) iowrite32(v, p)
static inline void iowrite32 ( u32 value , void __iomem * addr )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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outl ( value , port & PIO_MASK ) ;
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else
# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_writel ( ( u32 __force ) cpu_to_le32 ( value ) , addr ) ;
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# else
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__indirect_writel ( value , addr ) ;
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# endif
}
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# define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
static inline void iowrite32_rep ( void __iomem * addr , const void * vaddr ,
u32 count )
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{
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unsigned long port = ( unsigned long __force ) addr ;
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if ( __is_io_address ( port ) )
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outsl ( port & PIO_MASK , vaddr , count ) ;
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else
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# ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_writesl ( addr , vaddr , count ) ;
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# else
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__indirect_writesl ( addr , vaddr , count ) ;
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# endif
}
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# define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
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# define ioport_unmap(addr)
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# endif /* CONFIG_PCI */
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# endif /* __ASM_ARM_ARCH_IO_H */