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perf/x86/lbr: Switch to new Intel CPU model defines

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New CPU #defines encode vendor and family as well as model.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/all/20240424181500.41519-1-tony.luck%40intel.com
This commit is contained in:
Tony Luck 2024-04-24 11:15:00 -07:00 committed by Dave Hansen
parent 5ee800945a
commit 0011a51d73
1 changed files with 2 additions and 1 deletions
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3
arch/x86/events/intel/lbr.c
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@ -2,6 +2,7 @@
#include <linux/perf_event.h>
#include <linux/types.h>
#include <asm/cpu_device_id.h>
#include <asm/perf_event.h>
#include <asm/msr.h>
@ -1457,7 +1458,7 @@ void __init intel_pmu_lbr_init_atom(void)
* to have an operational LBR which can freeze
* on PMU interrupt
*/
if (boot_cpu_data.x86_model == 28
if (boot_cpu_data.x86_vfm == INTEL_ATOM_BONNELL
&& boot_cpu_data.x86_stepping < 10) {
pr_cont("LBR disabled due to erratum");
return;