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SoC related changes for omaps for v3.17 merge window:

Browse Source 
- Add device tree and hwmod data for various devices
   for new SoCs
 
 - Remove legacy mailbox hwmod data that's no longer
   needed for SoCs that are DT only. Note that this may
   cause a minor merge conflict in mach-omap2/devices.c
   with omap_init_mbox() and omap_init_hdmi_audio(), both
   are legacy code that is getting removed
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Merge tag 'omap-for-v3.17/soc-new' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Merge "SoC related changes for omaps for v3.17 merge window"
from Tony Lindgren:

- Add device tree and hwmod data for various devices
  for new SoCs

- Remove legacy mailbox hwmod data that's no longer
  needed for SoCs that are DT only. Note that this may
  cause a minor merge conflict in mach-omap2/devices.c
  with omap_init_mbox() and omap_init_hdmi_audio(), both
  are legacy code that is getting removed

* tag 'omap-for-v3.17/soc-new' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: DRA7: hwmod: Add data for RTC
  arm: dra7xx: Add hwmod data for MDIO and CPSW
  arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
  arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy
  ARM: DRA7: hwmod: Add OCP2SCP3 module
  ARM: DRA7: hwmod: remove interrupts for DMA
  ARM: OMAP2+: DMA: remove requirement of irq for platform-dma driver
  ARM: AM33xx: hwmod_data: Remove legacy mailbox addrs
  ARM: OMAP4: hwmod_data: Remove legacy mailbox addrs
  ARM: OMAP2: hwmod_data: Remove legacy mailbox data and addrs
  ARM: OMAP2+: Avoid mailbox legacy device creation for DT-boot
  ARM: DRA7: hwmod_data: Add mailbox hwmod data
  ARM: dts: DRA7: Add mailbox nodes
  ARM: dts: AM4372: Correct mailbox node data
  ARM: dts: AM33xx: Add mailbox node
  ARM: dts: OMAP4: Add mailbox node
  ARM: dts: OMAP2+: Add mailbox fifo and user information
  ARM: AM43xx: hwmod: add DSS hwmod data

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-07-26 11:33:34 +02:00
commit 0081b77d98
26 changed files with 881 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/boot/dts/am33xx.dtsi
View File

@ -347,6 +347,15 @@
status = "disabled";
};
mailbox: mailbox@480C8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <77>;
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
};
timer1: timer@44e31000 {
compatible = "ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>;

3
arch/arm/boot/dts/am4372.dtsi
View File

@ -168,9 +168,6 @@
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
ti,mbox-names = "wkup_m3";
ti,mbox-data = <0 0 0 0>;
status = "disabled";
};
timer1: timer@44e31000 {

117
arch/arm/boot/dts/dra7.dtsi
View File

@ -338,6 +338,123 @@
status = "disabled";
};
mailbox1: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
ti,hwmods = "mailbox1";
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
status = "disabled";
};
mailbox2: mailbox@4883a000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883a000 0x200>;
ti,hwmods = "mailbox2";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox3: mailbox@4883c000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883c000 0x200>;
ti,hwmods = "mailbox3";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox4: mailbox@4883e000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883e000 0x200>;
ti,hwmods = "mailbox4";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox5: mailbox@48840000 {
compatible = "ti,omap4-mailbox";
reg = <0x48840000 0x200>;
ti,hwmods = "mailbox5";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox6: mailbox@48842000 {
compatible = "ti,omap4-mailbox";
reg = <0x48842000 0x200>;
ti,hwmods = "mailbox6";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox7: mailbox@48844000 {
compatible = "ti,omap4-mailbox";
reg = <0x48844000 0x200>;
ti,hwmods = "mailbox7";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox8: mailbox@48846000 {
compatible = "ti,omap4-mailbox";
reg = <0x48846000 0x200>;
ti,hwmods = "mailbox8";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox9: mailbox@4885e000 {
compatible = "ti,omap4-mailbox";
reg = <0x4885e000 0x200>;
ti,hwmods = "mailbox9";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox10: mailbox@48860000 {
compatible = "ti,omap4-mailbox";
reg = <0x48860000 0x200>;
ti,hwmods = "mailbox10";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox11: mailbox@48862000 {
compatible = "ti,omap4-mailbox";
reg = <0x48862000 0x200>;
ti,hwmods = "mailbox11";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox12: mailbox@48864000 {
compatible = "ti,omap4-mailbox";
reg = <0x48864000 0x200>;
ti,hwmods = "mailbox12";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox13: mailbox@48802000 {
compatible = "ti,omap4-mailbox";
reg = <0x48802000 0x200>;
ti,hwmods = "mailbox13";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
timer1: timer@4ae18000 {
compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>;

2
arch/arm/boot/dts/omap2420.dtsi
View File

@ -157,6 +157,8 @@
interrupts = <26>, <34>;
interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
};
timer1: timer@48028000 {

2
arch/arm/boot/dts/omap2430.dtsi
View File

@ -247,6 +247,8 @@
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
};
timer1: timer@49018000 {

2
arch/arm/boot/dts/omap3.dtsi
View File

@ -332,6 +332,8 @@
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,mbox-num-users = <2>;
ti,mbox-num-fifos = <2>;
};
mcspi1: spi@48098000 {

9
arch/arm/boot/dts/omap4.dtsi
View File

@ -649,6 +649,15 @@
};
};
mailbox: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
};
timer1: timer@4a318000 {
compatible = "ti,omap3430-timer";
reg = <0x4a318000 0x80>;

2
arch/arm/boot/dts/omap5.dtsi
View File

@ -640,6 +640,8 @@
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
};
timer1: timer@4ae18000 {

1
arch/arm/mach-omap2/Makefile
View File

@ -202,6 +202,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
# hwmod data
obj-y += omap_hwmod_common_ipblock_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o

4
arch/arm/mach-omap2/cm2_7xx.h
View File

@ -357,6 +357,10 @@
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0
#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8
#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8

2
arch/arm/mach-omap2/devices.c
View File

@ -432,9 +432,9 @@ static int __init omap2_init_devices(void)
*/
omap_init_audio();
omap_init_camera();
omap_init_mbox();
/* If dtb is there, the devices will be created dynamically */
if (!of_have_populated_dt()) {
omap_init_mbox();
omap_init_mcspi();
omap_init_sham();
omap_init_aes();

3
arch/arm/mach-omap2/dma.c
View File

@ -259,6 +259,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
d->dev_caps |= HS_CHANNELS_RESERVED;
if (platform_get_irq_byname(pdev, "0") < 0)
d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
/* Check the capabilities register for descriptor loading feature */
if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
dma_common_ch_end = CCDN;

14
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -16,7 +16,6 @@
#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>
#include "omap_hwmod.h"
@ -163,18 +162,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
};
/* mailbox */
static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
{ .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
{ .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
};
static struct omap_mbox_pdata omap2420_mailbox_attrs = {
.num_users = 4,
.num_fifos = 6,
.info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
.info = omap2420_mailbox_info,
};
static struct omap_hwmod omap2420_mailbox_hwmod = {
.name = "mailbox",
.class = &omap2xxx_mailbox_hwmod_class,
@ -188,7 +175,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
},
},
.dev_attr = &omap2420_mailbox_attrs,
};
/*

13
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -17,7 +17,6 @@
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>
#include "omap_hwmod.h"
@ -161,17 +160,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
};
/* mailbox */
static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
{ .name = "dsp", .tx_id = 0, .rx_id = 1 },
};
static struct omap_mbox_pdata omap2430_mailbox_attrs = {
.num_users = 4,
.num_fifos = 6,
.info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
.info = omap2430_mailbox_info,
};
static struct omap_hwmod omap2430_mailbox_hwmod = {
.name = "mailbox",
.class = &omap2xxx_mailbox_hwmod_class,
@ -185,7 +173,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
},
},
.dev_attr = &omap2430_mailbox_attrs,
};
/* mcspi3 */

9
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
View File

@ -152,15 +152,6 @@ struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
{ }
};
struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
{
.pa_start = 0x48094000,
.pa_end = 0x48094000 + SZ_512 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
{
.name = "mpu",

40
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
View File

@ -36,46 +36,6 @@ struct omap_hwmod_class omap2_uart_class = {
.sysc = &omap2_uart_sysc,
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2_dss_sysc,
.reset = omap_dss_reset,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2_rfbi_sysc,
};
/*
* 'venc' class
* video encoder

10
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View File

@ -317,21 +317,11 @@ struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
{
.pa_start = 0x480C8000,
.pa_end = 0x480C8000 + (SZ_4K - 1),
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4 ls -> mailbox */
struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_mailbox_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_mailbox_addrs,
.user = OCP_USER_MPU,
};

100
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View File

@ -19,6 +19,8 @@
#include "omap_hwmod.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
#include "omap_hwmod_common_data.h"
/* IP blocks */
static struct omap_hwmod am43xx_l4_hs_hwmod = {
@ -415,6 +417,72 @@ static struct omap_hwmod am43xx_qspi_hwmod = {
},
};
/* dss */
static struct omap_hwmod am43xx_dss_core_hwmod = {
.name = "dss_core",
.class = &omap2_dss_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "disp_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* dispc */
struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
.manager_count = 1,
.has_framedonetv_irq = 0
};
static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
.name = "dispc",
.sysc = &am43xx_dispc_sysc,
};
static struct omap_hwmod am43xx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &am43xx_dispc_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "disp_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
},
},
.dev_attr = &am43xx_dss_dispc_dev_attr,
};
/* rfbi */
static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap2_rfbi_hwmod_class,
.clkdm_name = "dss_clkdm",
.main_clk = "disp_clk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
},
},
};
/* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
.master = &am33xx_l3_main_hwmod,
@ -654,6 +722,34 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
.master = &am43xx_dss_core_hwmod,
.slave = &am33xx_l3_main_hwmod,
.clk = "l3_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_dss_core_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_dss_dispc_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_dss_rfbi_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__synctimer,
&am43xx_l4_ls__timer8,
@ -748,6 +844,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am43xx_l4_ls__ocp2scp1,
&am43xx_l3_s__usbotgss0,
&am43xx_l3_s__usbotgss1,
&am43xx_dss__l3_main,
&am43xx_l4_ls__dss,
&am43xx_l4_ls__dss_dispc,
&am43xx_l4_ls__dss_rfbi,
NULL,
};

10
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -4142,21 +4142,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
{
.pa_start = 0x4a0f4000,
.pa_end = 0x4a0f41ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> mailbox */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_mailbox_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mailbox_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

574
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -272,6 +272,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
},
};
/*
* 'gmac' class
* cpsw/gmac sub system
*/
static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
.name = "gmac",
.sysc = &dra7xx_gmac_sysc,
};
static struct omap_hwmod dra7xx_gmac_hwmod = {
.name = "gmac",
.class = &dra7xx_gmac_hwmod_class,
.clkdm_name = "gmac_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "dpll_gmac_ck",
.mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mdio' class
*/
static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
.name = "davinci_mdio",
};
static struct omap_hwmod dra7xx_mdio_hwmod = {
.name = "davinci_mdio",
.class = &dra7xx_mdio_hwmod_class,
.clkdm_name = "gmac_clkdm",
.main_clk = "dpll_gmac_ck",
};
/*
* 'dcan' class
*
@ -343,19 +393,10 @@ static struct omap_dma_dev_attr dma_dev_attr = {
};
/* dma_system */
static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
{ .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
{ .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
{ .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
{ .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod dra7xx_dma_system_hwmod = {
.name = "dma_system",
.class = &dra7xx_dma_hwmod_class,
.clkdm_name = "dma_clkdm",
.mpu_irqs = dra7xx_dma_system_irqs,
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
@ -938,6 +979,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = {
.dev_attr = &i2c_dev_attr,
};
/*
* 'mailbox' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &dra7xx_mailbox_sysc,
};
/* mailbox1 */
static struct omap_hwmod dra7xx_mailbox1_hwmod = {
.name = "mailbox1",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
},
},
};
/* mailbox2 */
static struct omap_hwmod dra7xx_mailbox2_hwmod = {
.name = "mailbox2",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
},
},
};
/* mailbox3 */
static struct omap_hwmod dra7xx_mailbox3_hwmod = {
.name = "mailbox3",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
},
},
};
/* mailbox4 */
static struct omap_hwmod dra7xx_mailbox4_hwmod = {
.name = "mailbox4",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
},
},
};
/* mailbox5 */
static struct omap_hwmod dra7xx_mailbox5_hwmod = {
.name = "mailbox5",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
},
},
};
/* mailbox6 */
static struct omap_hwmod dra7xx_mailbox6_hwmod = {
.name = "mailbox6",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
},
},
};
/* mailbox7 */
static struct omap_hwmod dra7xx_mailbox7_hwmod = {
.name = "mailbox7",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
},
},
};
/* mailbox8 */
static struct omap_hwmod dra7xx_mailbox8_hwmod = {
.name = "mailbox8",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
},
},
};
/* mailbox9 */
static struct omap_hwmod dra7xx_mailbox9_hwmod = {
.name = "mailbox9",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
},
},
};
/* mailbox10 */
static struct omap_hwmod dra7xx_mailbox10_hwmod = {
.name = "mailbox10",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
},
},
};
/* mailbox11 */
static struct omap_hwmod dra7xx_mailbox11_hwmod = {
.name = "mailbox11",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
},
},
};
/* mailbox12 */
static struct omap_hwmod dra7xx_mailbox12_hwmod = {
.name = "mailbox12",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
},
},
};
/* mailbox13 */
static struct omap_hwmod dra7xx_mailbox13_hwmod = {
.name = "mailbox13",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
},
},
};
/*
* 'mcspi' class
*
@ -1215,6 +1444,97 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
},
};
/* ocp2scp3 */
static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
.name = "ocp2scp3",
.class = &dra7xx_ocp2scp_hwmod_class,
.clkdm_name = "l3init_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'PCIE' class
*
*/
static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
.name = "pcie",
};
/* pcie1 */
static struct omap_hwmod dra7xx_pcie1_hwmod = {
.name = "pcie1",
.class = &dra7xx_pcie_hwmod_class,
.clkdm_name = "pcie_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* pcie2 */
static struct omap_hwmod dra7xx_pcie2_hwmod = {
.name = "pcie2",
.class = &dra7xx_pcie_hwmod_class,
.clkdm_name = "pcie_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'PCIE PHY' class
*
*/
static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
.name = "pcie-phy",
};
/* pcie1 phy */
static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
.name = "pcie1-phy",
.class = &dra7xx_pcie_phy_hwmod_class,
.clkdm_name = "l3init_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* pcie2 phy */
static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
.name = "pcie2-phy",
.class = &dra7xx_pcie_phy_hwmod_class,
.clkdm_name = "l3init_clkdm",
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'qspi' class
*
@ -1248,6 +1568,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = {
},
};
/*
* 'rtcss' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
.sysc_offs = 0x0078,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
.name = "rtcss",
.sysc = &dra7xx_rtcss_sysc,
};
/* rtcss */
static struct omap_hwmod dra7xx_rtcss_hwmod = {
.name = "rtcss",
.class = &dra7xx_rtcss_hwmod_class,
.clkdm_name = "rtc_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'sata' class
*
@ -2007,6 +2359,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_gmac_hwmod,
.clk = "dpll_gmac_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
.master = &dra7xx_gmac_hwmod,
.slave = &dra7xx_mdio_hwmod,
.user = OCP_USER_MPU,
};
/* l4_wkup -> dcan1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
.master = &dra7xx_l4_wkup_hwmod,
@ -2254,6 +2619,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mailbox1 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_mailbox1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox3_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox4_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox5_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox6_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox7_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox8_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox9 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox9_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox10 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox10_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox11 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox11_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox12 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox12_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox13 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox13_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> mcspi1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
.master = &dra7xx_l4_per1_hwmod,
@ -2334,6 +2803,62 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> ocp2scp3 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_ocp2scp3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> pcie1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_pcie1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> pcie1 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_pcie1_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> pcie2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_pcie2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> pcie2 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_pcie2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_pcie1_phy_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> pcie2 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_pcie2_phy_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start = 0x4b300000,
@ -2352,6 +2877,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> rtcss */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_rtcss_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
{
.name = "sysc",
@ -2650,6 +3183,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_wkup__ctrl_module_wkup,
&dra7xx_l4_wkup__dcan1,
&dra7xx_l4_per2__dcan2,
&dra7xx_l4_per2__cpgmac0,
&dra7xx_gmac__mdio,
&dra7xx_l4_cfg__dma_system,
&dra7xx_l3_main_1__dss,
&dra7xx_l3_main_1__dispc,
@ -2670,6 +3205,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per1__i2c3,
&dra7xx_l4_per1__i2c4,
&dra7xx_l4_per1__i2c5,
&dra7xx_l4_cfg__mailbox1,
&dra7xx_l4_per3__mailbox2,
&dra7xx_l4_per3__mailbox3,
&dra7xx_l4_per3__mailbox4,
&dra7xx_l4_per3__mailbox5,
&dra7xx_l4_per3__mailbox6,
&dra7xx_l4_per3__mailbox7,
&dra7xx_l4_per3__mailbox8,
&dra7xx_l4_per3__mailbox9,
&dra7xx_l4_per3__mailbox10,
&dra7xx_l4_per3__mailbox11,
&dra7xx_l4_per3__mailbox12,
&dra7xx_l4_per3__mailbox13,
&dra7xx_l4_per1__mcspi1,
&dra7xx_l4_per1__mcspi2,
&dra7xx_l4_per1__mcspi3,
@ -2680,7 +3228,15 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per1__mmc4,
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
&dra7xx_l3_main_1__pcie1,
&dra7xx_l4_cfg__pcie1,
&dra7xx_l3_main_1__pcie2,
&dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_per3__rtcss,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
&dra7xx_l4_cfg__smartreflex_mpu,

1
arch/arm/mach-omap2/omap_hwmod_common_data.h
View File

@ -33,7 +33,6 @@ extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];

55
arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c Normal file
View File

@ -0,0 +1,55 @@
/*
* omap_hwmod_common_ipblock_data.c - common IP block data for OMAP2+
*
* Copyright (C) 2011 Nokia Corporation
* Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2_dss_sysc,
.reset = omap_dss_reset,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2_rfbi_sysc,
};

1
arch/arm/mach-omap2/prcm43xx.h
View File

@ -142,5 +142,6 @@
#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8
#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268
#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
#endif

4
arch/arm/mach-omap2/prm7xx.h
View File

@ -374,6 +374,10 @@
#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0
#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4
#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8
#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc
#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec

5
arch/arm/plat-omap/dma.c
View File

@ -2100,7 +2100,7 @@ static int omap_system_dma_probe(struct platform_device *pdev)
omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
DMA_DEFAULT_FIFO_DEPTH, 0);
if (dma_omap2plus()) {
if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
strcpy(irq_name, "0");
dma_irq = platform_get_irq_byname(pdev, irq_name);
if (dma_irq < 0) {
@ -2145,7 +2145,8 @@ static int omap_system_dma_remove(struct platform_device *pdev)
char irq_name[4];
strcpy(irq_name, "0");
dma_irq = platform_get_irq_byname(pdev, irq_name);
remove_irq(dma_irq, &omap24xx_dma_irq);
if (dma_irq >= 0)
remove_irq(dma_irq, &omap24xx_dma_irq);
} else {
int irq_rel = 0;
for ( ; irq_rel < dma_chan_count; irq_rel++) {

1
include/linux/omap-dma.h
View File

@ -130,6 +130,7 @@
#define IS_WORD_16 BIT(0xd)
#define ENABLE_16XX_MODE BIT(0xe)
#define HS_CHANNELS_RESERVED BIT(0xf)
#define DMA_ENGINE_HANDLE_IRQ BIT(0x10)
/* Defines for DMA Capabilities */
#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)