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bna: CheckPatch Cleanup

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Change details:
 - Driver cleanup as per new checkpatch v0.31

Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rasesh Mody 2011-07-22 08:07:41 +00:00 committed by David S. Miller
parent 5aad00118f
commit 0120b99c8d
13 changed files with 215 additions and 215 deletions
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4
drivers/net/bna/bfa_defs.h
View File

@ -80,7 +80,7 @@ struct bfa_adapter_attr {
enum {
BFA_IOC_DRIVER_LEN = 16,
BFA_IOC_CHIP_REV_LEN = 8,
BFA_IOC_CHIP_REV_LEN = 8,
};
/**
@ -174,7 +174,7 @@ enum bfa_ioc_type {
*/
struct bfa_ioc_attr {
enum bfa_ioc_type ioc_type;
enum bfa_ioc_state state; /*!< IOC state */
enum bfa_ioc_state state; /*!< IOC state */
struct bfa_adapter_attr adapter_attr; /*!< HBA attributes */
struct bfa_ioc_driver_attr driver_attr; /*!< driver attr */
struct bfa_ioc_pci_attr pci_attr;

20
drivers/net/bna/bfa_defs_mfg_comm.h
View File

@ -192,14 +192,14 @@ do { \
* VPD vendor tag
*/
enum {
BFA_MFG_VPD_UNKNOWN = 0, /*!< vendor unknown */
BFA_MFG_VPD_IBM = 1, /*!< vendor IBM */
BFA_MFG_VPD_HP = 2, /*!< vendor HP */
BFA_MFG_VPD_DELL = 3, /*!< vendor DELL */
BFA_MFG_VPD_PCI_IBM = 0x08, /*!< PCI VPD IBM */
BFA_MFG_VPD_PCI_HP = 0x10, /*!< PCI VPD HP */
BFA_MFG_VPD_PCI_DELL = 0x20, /*!< PCI VPD DELL */
BFA_MFG_VPD_PCI_BRCD = 0xf8, /*!< PCI VPD Brocade */
BFA_MFG_VPD_UNKNOWN = 0, /*!< vendor unknown */
BFA_MFG_VPD_IBM = 1, /*!< vendor IBM */
BFA_MFG_VPD_HP = 2, /*!< vendor HP */
BFA_MFG_VPD_DELL = 3, /*!< vendor DELL */
BFA_MFG_VPD_PCI_IBM = 0x08, /*!< PCI VPD IBM */
BFA_MFG_VPD_PCI_HP = 0x10, /*!< PCI VPD HP */
BFA_MFG_VPD_PCI_DELL = 0x20, /*!< PCI VPD DELL */
BFA_MFG_VPD_PCI_BRCD = 0xf8, /*!< PCI VPD Brocade */
};
/**
@ -212,8 +212,8 @@ struct bfa_mfg_vpd {
u8 vpd_sig[3]; /*!< characters 'V', 'P', 'D' */
u8 chksum; /*!< u8 checksum */
u8 vendor; /*!< vendor */
u8 len; /*!< vpd data length excluding header */
u8 rsv;
u8 len; /*!< vpd data length excluding header */
u8 rsv;
u8 data[BFA_MFG_VPD_LEN]; /*!< vpd data */
};

134
drivers/net/bna/bfa_defs_status.h
View File

@ -25,95 +25,95 @@
* comments are supported
*/
enum bfa_status {
BFA_STATUS_OK = 0,
BFA_STATUS_FAILED = 1,
BFA_STATUS_EINVAL = 2,
BFA_STATUS_ENOMEM = 3,
BFA_STATUS_ENOSYS = 4,
BFA_STATUS_ETIMER = 5,
BFA_STATUS_EPROTOCOL = 6,
BFA_STATUS_ENOFCPORTS = 7,
BFA_STATUS_NOFLASH = 8,
BFA_STATUS_BADFLASH = 9,
BFA_STATUS_SFP_UNSUPP = 10,
BFA_STATUS_OK = 0,
BFA_STATUS_FAILED = 1,
BFA_STATUS_EINVAL = 2,
BFA_STATUS_ENOMEM = 3,
BFA_STATUS_ENOSYS = 4,
BFA_STATUS_ETIMER = 5,
BFA_STATUS_EPROTOCOL = 6,
BFA_STATUS_ENOFCPORTS = 7,
BFA_STATUS_NOFLASH = 8,
BFA_STATUS_BADFLASH = 9,
BFA_STATUS_SFP_UNSUPP = 10,
BFA_STATUS_UNKNOWN_VFID = 11,
BFA_STATUS_DATACORRUPTED = 12,
BFA_STATUS_DEVBUSY = 13,
BFA_STATUS_ABORTED = 14,
BFA_STATUS_NODEV = 15,
BFA_STATUS_HDMA_FAILED = 16,
BFA_STATUS_DEVBUSY = 13,
BFA_STATUS_ABORTED = 14,
BFA_STATUS_NODEV = 15,
BFA_STATUS_HDMA_FAILED = 16,
BFA_STATUS_FLASH_BAD_LEN = 17,
BFA_STATUS_UNKNOWN_LWWN = 18,
BFA_STATUS_UNKNOWN_RWWN = 19,
BFA_STATUS_FCPT_LS_RJT = 20,
BFA_STATUS_FCPT_LS_RJT = 20,
BFA_STATUS_VPORT_EXISTS = 21,
BFA_STATUS_VPORT_MAX = 22,
BFA_STATUS_VPORT_MAX = 22,
BFA_STATUS_UNSUPP_SPEED = 23,
BFA_STATUS_INVLD_DFSZ = 24,
BFA_STATUS_CNFG_FAILED = 25,
BFA_STATUS_CMD_NOTSUPP = 26,
BFA_STATUS_NO_ADAPTER = 27,
BFA_STATUS_LINKDOWN = 28,
BFA_STATUS_FABRIC_RJT = 29,
BFA_STATUS_INVLD_DFSZ = 24,
BFA_STATUS_CNFG_FAILED = 25,
BFA_STATUS_CMD_NOTSUPP = 26,
BFA_STATUS_NO_ADAPTER = 27,
BFA_STATUS_LINKDOWN = 28,
BFA_STATUS_FABRIC_RJT = 29,
BFA_STATUS_UNKNOWN_VWWN = 30,
BFA_STATUS_NSLOGIN_FAILED = 31,
BFA_STATUS_NO_RPORTS = 32,
BFA_STATUS_NO_RPORTS = 32,
BFA_STATUS_NSQUERY_FAILED = 33,
BFA_STATUS_PORT_OFFLINE = 34,
BFA_STATUS_RPORT_OFFLINE = 35,
BFA_STATUS_TGTOPEN_FAILED = 36,
BFA_STATUS_BAD_LUNS = 37,
BFA_STATUS_IO_FAILURE = 38,
BFA_STATUS_NO_FABRIC = 39,
BFA_STATUS_EBADF = 40,
BFA_STATUS_EINTR = 41,
BFA_STATUS_EIO = 42,
BFA_STATUS_ENOTTY = 43,
BFA_STATUS_ENXIO = 44,
BFA_STATUS_EFOPEN = 45,
BFA_STATUS_BAD_LUNS = 37,
BFA_STATUS_IO_FAILURE = 38,
BFA_STATUS_NO_FABRIC = 39,
BFA_STATUS_EBADF = 40,
BFA_STATUS_EINTR = 41,
BFA_STATUS_EIO = 42,
BFA_STATUS_ENOTTY = 43,
BFA_STATUS_ENXIO = 44,
BFA_STATUS_EFOPEN = 45,
BFA_STATUS_VPORT_WWN_BP = 46,
BFA_STATUS_PORT_NOT_DISABLED = 47,
BFA_STATUS_BADFRMHDR = 48,
BFA_STATUS_BADFRMSZ = 49,
BFA_STATUS_MISSINGFRM = 50,
BFA_STATUS_LINKTIMEOUT = 51,
BFA_STATUS_BADFRMHDR = 48,
BFA_STATUS_BADFRMSZ = 49,
BFA_STATUS_MISSINGFRM = 50,
BFA_STATUS_LINKTIMEOUT = 51,
BFA_STATUS_NO_FCPIM_NEXUS = 52,
BFA_STATUS_CHECKSUM_FAIL = 53,
BFA_STATUS_GZME_FAILED = 54,
BFA_STATUS_GZME_FAILED = 54,
BFA_STATUS_SCSISTART_REQD = 55,
BFA_STATUS_IOC_FAILURE = 56,
BFA_STATUS_INVALID_WWN = 57,
BFA_STATUS_MISMATCH = 58,
BFA_STATUS_IOC_ENABLED = 59,
BFA_STATUS_IOC_FAILURE = 56,
BFA_STATUS_INVALID_WWN = 57,
BFA_STATUS_MISMATCH = 58,
BFA_STATUS_IOC_ENABLED = 59,
BFA_STATUS_ADAPTER_ENABLED = 60,
BFA_STATUS_IOC_NON_OP = 61,
BFA_STATUS_IOC_NON_OP = 61,
BFA_STATUS_ADDR_MAP_FAILURE = 62,
BFA_STATUS_SAME_NAME = 63,
BFA_STATUS_PENDING = 64,
BFA_STATUS_8G_SPD = 65,
BFA_STATUS_4G_SPD = 66,
BFA_STATUS_SAME_NAME = 63,
BFA_STATUS_PENDING = 64,
BFA_STATUS_8G_SPD = 65,
BFA_STATUS_4G_SPD = 66,
BFA_STATUS_AD_IS_ENABLE = 67,
BFA_STATUS_EINVAL_TOV = 68,
BFA_STATUS_EINVAL_TOV = 68,
BFA_STATUS_EINVAL_QDEPTH = 69,
BFA_STATUS_VERSION_FAIL = 70,
BFA_STATUS_DIAG_BUSY = 71,
BFA_STATUS_BEACON_ON = 72,
BFA_STATUS_BEACON_OFF = 73,
BFA_STATUS_LBEACON_ON = 74,
BFA_STATUS_LBEACON_OFF = 75,
BFA_STATUS_DIAG_BUSY = 71,
BFA_STATUS_BEACON_ON = 72,
BFA_STATUS_BEACON_OFF = 73,
BFA_STATUS_LBEACON_ON = 74,
BFA_STATUS_LBEACON_OFF = 75,
BFA_STATUS_PORT_NOT_INITED = 76,
BFA_STATUS_RPSC_ENABLED = 77,
BFA_STATUS_ENOFSAVE = 78,
BFA_STATUS_BAD_FILE = 79,
BFA_STATUS_RLIM_EN = 80,
BFA_STATUS_RLIM_DIS = 81,
BFA_STATUS_IOC_DISABLED = 82,
BFA_STATUS_ADAPTER_DISABLED = 83,
BFA_STATUS_BIOS_DISABLED = 84,
BFA_STATUS_AUTH_ENABLED = 85,
BFA_STATUS_AUTH_DISABLED = 86,
BFA_STATUS_ERROR_TRL_ENABLED = 87,
BFA_STATUS_ERROR_QOS_ENABLED = 88,
BFA_STATUS_ENOFSAVE = 78,
BFA_STATUS_BAD_FILE = 79,
BFA_STATUS_RLIM_EN = 80,
BFA_STATUS_RLIM_DIS = 81,
BFA_STATUS_IOC_DISABLED = 82,
BFA_STATUS_ADAPTER_DISABLED = 83,
BFA_STATUS_BIOS_DISABLED = 84,
BFA_STATUS_AUTH_ENABLED = 85,
BFA_STATUS_AUTH_DISABLED = 86,
BFA_STATUS_ERROR_TRL_ENABLED = 87,
BFA_STATUS_ERROR_QOS_ENABLED = 88,
BFA_STATUS_NO_SFP_DEV = 89,
BFA_STATUS_MEMTEST_FAILED = 90,
BFA_STATUS_INVALID_DEVID = 91,
@ -190,7 +190,7 @@ enum bfa_status {
BFA_STATUS_FLASH_CKFAIL = 162,
BFA_STATUS_TRUNK_UNSUPP = 163,
BFA_STATUS_TRUNK_ENABLED = 164,
BFA_STATUS_TRUNK_DISABLED = 165,
BFA_STATUS_TRUNK_DISABLED = 165,
BFA_STATUS_TRUNK_ERROR_TRL_ENABLED = 166,
BFA_STATUS_BOOT_CODE_UPDATED = 167,
BFA_STATUS_BOOT_VERSION = 168,
@ -198,8 +198,8 @@ enum bfa_status {
BFA_STATUS_INVALID_CARDTYPE = 170,
BFA_STATUS_NO_TOPOLOGY_FOR_CNA = 171,
BFA_STATUS_IM_VLAN_OVER_TEAM_DELETE_FAILED = 172,
BFA_STATUS_ETHBOOT_ENABLED = 173,
BFA_STATUS_ETHBOOT_DISABLED = 174,
BFA_STATUS_ETHBOOT_ENABLED = 173,
BFA_STATUS_ETHBOOT_DISABLED = 174,
BFA_STATUS_IOPROFILE_OFF = 175,
BFA_STATUS_NO_PORT_INSTANCE = 176,
BFA_STATUS_BOOT_CODE_TIMEDOUT = 177,

2
drivers/net/bna/bfa_ioc.c
View File

@ -156,7 +156,7 @@ enum iocpf_event {
IOCPF_E_ENABLE = 1, /*!< IOCPF enable request */
IOCPF_E_DISABLE = 2, /*!< IOCPF disable request */
IOCPF_E_STOP = 3, /*!< stop on driver detach */
IOCPF_E_FWREADY = 4, /*!< f/w initialization done */
IOCPF_E_FWREADY = 4, /*!< f/w initialization done */
IOCPF_E_FWRSP_ENABLE = 5, /*!< enable f/w response */
IOCPF_E_FWRSP_DISABLE = 6, /*!< disable f/w response */
IOCPF_E_FAIL = 7, /*!< failure notice by ioc sm */

16
drivers/net/bna/bfa_ioc.h
View File

@ -155,11 +155,11 @@ struct bfa_iocpf {
struct bfa_ioc {
bfa_fsm_t fsm;
struct bfa *bfa;
struct bfa_pcidev pcidev;
struct timer_list ioc_timer;
struct timer_list iocpf_timer;
struct timer_list sem_timer;
struct bfa *bfa;
struct bfa_pcidev pcidev;
struct timer_list ioc_timer;
struct timer_list iocpf_timer;
struct timer_list sem_timer;
struct timer_list hb_timer;
u32 hb_count;
struct list_head hb_notify_q;
@ -167,13 +167,13 @@ struct bfa_ioc {
int dbg_fwsave_len;
bool dbg_fwsave_once;
enum bfi_mclass ioc_mc;
struct bfa_ioc_regs ioc_regs;
struct bfa_ioc_regs ioc_regs;
struct bfa_ioc_drv_stats stats;
bool fcmode;
bool ctdev;
bool cna;
bool pllinit;
bool stats_busy; /*!< outstanding stats */
bool stats_busy; /*!< outstanding stats */
u8 port_id;
struct bfa_dma attr_dma;
@ -219,7 +219,7 @@ struct bfa_ioc_hwif {
#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
#define BFA_IOC_FWIMG_TYPE(__ioc) \
(((__ioc)->ctdev) ? \
(((__ioc)->ctdev) ? \
(((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \
BFI_IMAGE_CB_FC)
#define BFA_IOC_FW_SMEM_SIZE(__ioc) \

14
drivers/net/bna/bfi.h
View File

@ -51,13 +51,13 @@ struct bfi_mhdr {
};
#define bfi_h2i_set(_mh, _mc, _op, _lpuid) do { \
(_mh).msg_class = (_mc); \
(_mh).msg_class = (_mc); \
(_mh).msg_id = (_op); \
(_mh).mtag.h2i.lpu_id = (_lpuid); \
} while (0)
#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
(_mh).msg_class = (_mc); \
(_mh).msg_class = (_mc); \
(_mh).msg_id = (_op); \
(_mh).mtag.i2htok = (_i2htok); \
} while (0)
@ -66,7 +66,7 @@ struct bfi_mhdr {
* Message opcodes: 0-127 to firmware, 128-255 to host
*/
#define BFI_I2H_OPCODE_BASE 128
#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
/**
****************************************************************************
@ -186,7 +186,7 @@ enum bfi_mclass {
#define BFI_BOOT_TYPE_OFF 8
#define BFI_BOOT_LOADER_OFF 12
#define BFI_BOOT_TYPE_NORMAL 0
#define BFI_BOOT_TYPE_NORMAL 0
#define BFI_BOOT_TYPE_FLASH 1
#define BFI_BOOT_TYPE_MEMTEST 2
@ -211,9 +211,9 @@ enum bfi_ioc_h2i_msgs {
enum bfi_ioc_i2h_msgs {
BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
BFI_IOC_I2H_READY_EVENT = BFA_I2HM(4),
BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
BFI_IOC_I2H_READY_EVENT = BFA_I2HM(4),
BFI_IOC_I2H_HBEAT = BFA_I2HM(5),
};

16
drivers/net/bna/bna.h
View File

@ -88,7 +88,7 @@ do { \
} while (0)
#define containing_rec(addr, type, field) \
((type *)((unsigned char *)(addr) - \
((type *)((unsigned char *)(addr) - \
(unsigned char *)(&((type *)0)->field)))
#define BNA_TXQ_WI_NEEDED(_vectors) (((_vectors) + 3) >> 2)
@ -101,8 +101,8 @@ do { \
{ \
unsigned int page_index; /* index within a page */ \
void *page_addr; \
page_index = (_qe_idx) & (BNA_TXQ_PAGE_INDEX_MAX - 1); \
(_qe_ptr_range) = (BNA_TXQ_PAGE_INDEX_MAX - page_index); \
page_index = (_qe_idx) & (BNA_TXQ_PAGE_INDEX_MAX - 1); \
(_qe_ptr_range) = (BNA_TXQ_PAGE_INDEX_MAX - page_index); \
page_addr = (_qpt_ptr)[((_qe_idx) >> BNA_TXQ_PAGE_INDEX_MAX_SHIFT)];\
(_qe_ptr) = &((struct bna_txq_entry *)(page_addr))[page_index]; \
}
@ -166,25 +166,25 @@ do { \
(((_q_ptr)->q.producer_index + (_num)) & \
((_q_ptr)->q.q_depth - 1))
#define BNA_Q_CI_ADD(_q_ptr, _num) \
#define BNA_Q_CI_ADD(_q_ptr, _num) \
(_q_ptr)->q.consumer_index = \
(((_q_ptr)->q.consumer_index + (_num)) \
(((_q_ptr)->q.consumer_index + (_num)) \
& ((_q_ptr)->q.q_depth - 1))
#define BNA_Q_FREE_COUNT(_q_ptr) \
(BNA_QE_FREE_CNT(&((_q_ptr)->q), (_q_ptr)->q.q_depth))
#define BNA_Q_IN_USE_COUNT(_q_ptr) \
#define BNA_Q_IN_USE_COUNT(_q_ptr) \
(BNA_QE_IN_USE_CNT(&(_q_ptr)->q, (_q_ptr)->q.q_depth))
/* These macros build the data portion of the TxQ/RxQ doorbell */
#define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi))
#define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi))
#define BNA_DOORBELL_Q_STOP (0x40000000)
/* These macros build the data portion of the IB doorbell */
#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \
(0x80000000 | ((_timeout) << 16) | (_events))
#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
/* Set the coalescing timer for the given ib */
#define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer) \

92
drivers/net/bna/bna_hw.h
View File

@ -67,7 +67,7 @@ static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \
/**
* There are 2 free RIT segment pools:
* Pool1: 192 segments of 1 RIT entry each
* Pool1: 192 segments of 1 RIT entry each
* Pool2: 1 segment of 64 RIT entry
*/
#define BFI_RIT_SEG_POOL1_SIZE 192
@ -357,14 +357,14 @@ static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
* To clear set the value to 0.
* Range : 0x20 to 0x5c
*/
#define PSS_SEM_LOCK_REG(_num) \
#define PSS_SEM_LOCK_REG(_num) \
(PSS_BLK_REG_ADDR + 0x020 + ((_num) << 2))
/**
* PSS Semaphore Status Registers,
* corresponding to the lock registers above
*/
#define PSS_SEM_STATUS_REG(_num) \
#define PSS_SEM_STATUS_REG(_num) \
(PSS_BLK_REG_ADDR + 0x060 + ((_num) << 2))
/**
@ -1044,7 +1044,7 @@ static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
__LPU12HOST_MBOX1_STATUS_BITS))
#define BNA_IS_MBOX_INTR(_intr_status) \
((_intr_status) & \
((_intr_status) & \
(__LPU02HOST_MBOX0_STATUS_BITS | \
__LPU02HOST_MBOX1_STATUS_BITS | \
__LPU12HOST_MBOX0_STATUS_BITS | \
@ -1070,11 +1070,11 @@ static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
__HALT_MASK_BITS)
#define BNA_IS_ERR_INTR(_intr_status) \
((_intr_status) & \
(__EMC_ERROR_STATUS_BITS | \
__LPU0_ERROR_STATUS_BITS | \
__LPU1_ERROR_STATUS_BITS | \
__PSS_ERROR_STATUS_BITS | \
((_intr_status) & \
(__EMC_ERROR_STATUS_BITS | \
__LPU0_ERROR_STATUS_BITS | \
__LPU1_ERROR_STATUS_BITS | \
__PSS_ERROR_STATUS_BITS | \
__HALT_STATUS_BITS))
#define BNA_IS_MBOX_ERR_INTR(_intr_status) \
@ -1087,9 +1087,9 @@ static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
#define BNA_INTR_STATUS_MBOX_CLR(_intr_status) \
do { \
(_intr_status) &= ~(__LPU02HOST_MBOX0_STATUS_BITS | \
__LPU02HOST_MBOX1_STATUS_BITS | \
__LPU12HOST_MBOX0_STATUS_BITS | \
__LPU12HOST_MBOX1_STATUS_BITS); \
__LPU02HOST_MBOX1_STATUS_BITS | \
__LPU12HOST_MBOX0_STATUS_BITS | \
__LPU12HOST_MBOX1_STATUS_BITS); \
} while (0)
#define BNA_INTR_STATUS_ERR_CLR(_intr_status) \
@ -1107,7 +1107,7 @@ do { \
writel(0xffffffff, (_bna)->regs.fn_int_mask);\
}
#define bna_intx_enable(bna, new_mask) \
#define bna_intx_enable(bna, new_mask) \
writel((new_mask), (bna)->regs.fn_int_mask)
#define bna_mbox_intr_disable(bna) \
@ -1179,18 +1179,18 @@ do {\
#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
/* TxQ Entry Opcodes */
#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */
#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */
#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */
#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */
#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */
/* TxQ Entry Control Flags */
#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8)
#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5)
#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4)
#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3)
#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2)
#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1)
#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0)
#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8)
#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5)
#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4)
#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3)
#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2)
#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1)
#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0)
#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
(((_hdr_size) << 10) | ((_offset) & 0x3FF))
@ -1199,30 +1199,30 @@ do {\
* Completion Q defines
*/
/* CQ Entry Flags */
#define BNA_CQ_EF_MAC_ERROR (1 << 0)
#define BNA_CQ_EF_FCS_ERROR (1 << 1)
#define BNA_CQ_EF_TOO_LONG (1 << 2)
#define BNA_CQ_EF_FC_CRC_OK (1 << 3)
#define BNA_CQ_EF_MAC_ERROR (1 << 0)
#define BNA_CQ_EF_FCS_ERROR (1 << 1)
#define BNA_CQ_EF_TOO_LONG (1 << 2)
#define BNA_CQ_EF_FC_CRC_OK (1 << 3)
#define BNA_CQ_EF_RSVD1 (1 << 4)
#define BNA_CQ_EF_RSVD1 (1 << 4)
#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5)
#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6)
#define BNA_CQ_EF_HDS_HEADER (1 << 7)
#define BNA_CQ_EF_UDP (1 << 8)
#define BNA_CQ_EF_TCP (1 << 9)
#define BNA_CQ_EF_UDP (1 << 8)
#define BNA_CQ_EF_TCP (1 << 9)
#define BNA_CQ_EF_IP_OPTIONS (1 << 10)
#define BNA_CQ_EF_IPV6 (1 << 11)
#define BNA_CQ_EF_IPV6 (1 << 11)
#define BNA_CQ_EF_IPV4 (1 << 12)
#define BNA_CQ_EF_VLAN (1 << 13)
#define BNA_CQ_EF_RSS (1 << 14)
#define BNA_CQ_EF_RSVD2 (1 << 15)
#define BNA_CQ_EF_IPV4 (1 << 12)
#define BNA_CQ_EF_VLAN (1 << 13)
#define BNA_CQ_EF_RSS (1 << 14)
#define BNA_CQ_EF_RSVD2 (1 << 15)
#define BNA_CQ_EF_MCAST_MATCH (1 << 16)
#define BNA_CQ_EF_MCAST (1 << 17)
#define BNA_CQ_EF_BCAST (1 << 18)
#define BNA_CQ_EF_REMOTE (1 << 19)
#define BNA_CQ_EF_MCAST (1 << 17)
#define BNA_CQ_EF_BCAST (1 << 18)
#define BNA_CQ_EF_REMOTE (1 << 19)
#define BNA_CQ_EF_LOCAL (1 << 20)
@ -1257,10 +1257,10 @@ enum ib_flags {
};
enum rss_hash_type {
BFI_RSS_T_V4_TCP = (1 << 11),
BFI_RSS_T_V4_IP = (1 << 10),
BFI_RSS_T_V6_TCP = (1 << 9),
BFI_RSS_T_V6_IP = (1 << 8)
BFI_RSS_T_V4_TCP = (1 << 11),
BFI_RSS_T_V4_IP = (1 << 10),
BFI_RSS_T_V6_TCP = (1 << 9),
BFI_RSS_T_V6_IP = (1 << 8)
};
enum hds_header_type {
BNA_HDS_T_V4_TCP = (1 << 11),
@ -1298,7 +1298,7 @@ struct bna_txq_mem {
u32 reserved2;
u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
/* 15:0 ->producer pointer (index?) */
u32 entry_n_pg_size; /* 31:16->entry size */
u32 entry_n_pg_size; /* 31:16->entry size */
/* 15:0 ->page size */
u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */
/* 23:16->Int Blk Offset */
@ -1326,7 +1326,7 @@ struct bna_rxq_mem {
u32 sg_n_cq_n_cns_ptr; /* 31:28->reserved; 27:24->sg count */
/* 23:16->CQ; */
/* 15:0->consumer pointer(index?) */
u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */
u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */
u32 next_qid; /* 17:10->next QId */
u32 reserved3;
u32 reserved4[4];
@ -1426,8 +1426,8 @@ struct bna_dma_addr {
};
struct bna_txq_wi_vector {
u16 reserved;
u16 length; /* Only 14 LSB are valid */
u16 reserved;
u16 length; /* Only 14 LSB are valid */
struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
};
@ -1465,7 +1465,7 @@ struct bna_txq_entry {
} hdr;
struct bna_txq_wi_vector vector[4];
};
#define wi_hdr hdr.wi
#define wi_hdr hdr.wi
#define wi_ext_hdr hdr.wi_ext
/* RxQ Entry Structure */

4
drivers/net/bna/bna_txrx.c
View File

@ -734,7 +734,7 @@ bna_rxf_sm_cam_fltr_clr_wait_entry(struct bna_rxf *rxf)
/**
* Note: Do not add rxf_clear_packet_filter here.
* It will overstep mbox when this transition happens:
* cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event
* cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event
*/
}
@ -771,7 +771,7 @@ bna_rxf_sm_stop_wait_entry(struct bna_rxf *rxf)
/**
* NOTE: Do not add rxf_disable here.
* It will overstep mbox when this transition happens:
* start_wait -> stop_wait on RXF_E_STOP event
* start_wait -> stop_wait on RXF_E_STOP event
*/
}

58
drivers/net/bna/bna_types.h
View File

@ -50,12 +50,12 @@ enum bna_status {
};
enum bna_cleanup_type {
BNA_HARD_CLEANUP = 0,
BNA_SOFT_CLEANUP = 1
BNA_HARD_CLEANUP = 0,
BNA_SOFT_CLEANUP = 1
};
enum bna_cb_status {
BNA_CB_SUCCESS = 0,
BNA_CB_SUCCESS = 0,
BNA_CB_FAIL = 1,
BNA_CB_INTERRUPT = 2,
BNA_CB_BUSY = 3,
@ -72,8 +72,8 @@ enum bna_res_type {
};
enum bna_mem_type {
BNA_MEM_T_KVA = 1,
BNA_MEM_T_DMA = 2
BNA_MEM_T_KVA = 1,
BNA_MEM_T_DMA = 2
};
enum bna_intr_type {
@ -82,10 +82,10 @@ enum bna_intr_type {
};
enum bna_res_req_type {
BNA_RES_MEM_T_COM = 0,
BNA_RES_MEM_T_ATTR = 1,
BNA_RES_MEM_T_FWTRC = 2,
BNA_RES_MEM_T_STATS = 3,
BNA_RES_MEM_T_COM = 0,
BNA_RES_MEM_T_ATTR = 1,
BNA_RES_MEM_T_FWTRC = 2,
BNA_RES_MEM_T_STATS = 3,
BNA_RES_MEM_T_SWSTATS = 4,
BNA_RES_MEM_T_IBIDX = 5,
BNA_RES_MEM_T_IB_ARRAY = 6,
@ -107,9 +107,9 @@ enum bna_res_req_type {
enum bna_tx_res_req_type {
BNA_TX_RES_MEM_T_TCB = 0,
BNA_TX_RES_MEM_T_UNMAPQ = 1,
BNA_TX_RES_MEM_T_QPT = 2,
BNA_TX_RES_MEM_T_QPT = 2,
BNA_TX_RES_MEM_T_SWQPT = 3,
BNA_TX_RES_MEM_T_PAGE = 4,
BNA_TX_RES_MEM_T_PAGE = 4,
BNA_TX_RES_INTR_T_TXCMPL = 5,
BNA_TX_RES_T_MAX,
};
@ -158,14 +158,14 @@ enum bna_rx_type {
};
enum bna_rxp_type {
BNA_RXP_SINGLE = 1,
BNA_RXP_SLR = 2,
BNA_RXP_HDS = 3
BNA_RXP_SINGLE = 1,
BNA_RXP_SLR = 2,
BNA_RXP_HDS = 3
};
enum bna_rxmode {
BNA_RXMODE_PROMISC = 1,
BNA_RXMODE_ALLMULTI = 2
BNA_RXMODE_PROMISC = 1,
BNA_RXMODE_ALLMULTI = 2
};
enum bna_rx_event {
@ -202,7 +202,7 @@ enum bna_rxf_oper_state {
};
enum bna_rxf_flags {
BNA_RXF_FL_STOP_PENDING = 0x01,
BNA_RXF_FL_STOP_PENDING = 0x01,
BNA_RXF_FL_FAILED = 0x02,
BNA_RXF_FL_RSS_CONFIG_PENDING = 0x04,
BNA_RXF_FL_OPERSTATE_CHANGED = 0x08,
@ -244,11 +244,11 @@ enum bna_port_type {
enum bna_link_status {
BNA_LINK_DOWN = 0,
BNA_LINK_UP = 1,
BNA_CEE_UP = 2
BNA_CEE_UP = 2
};
enum bna_llport_flags {
BNA_LLPORT_F_ADMIN_UP = 1,
BNA_LLPORT_F_ADMIN_UP = 1,
BNA_LLPORT_F_PORT_ENABLED = 2,
BNA_LLPORT_F_RX_STARTED = 4
};
@ -304,7 +304,7 @@ struct bna_mem_descr {
struct bna_mem_info {
enum bna_mem_type mem_type;
u32 len;
u32 num;
u32 num;
u32 align_sz; /* 0/1 = no alignment */
struct bna_mem_descr *mdl;
void *cookie; /* For bnad to unmap dma later */
@ -371,10 +371,10 @@ struct bna_mbox_qe {
struct list_head qe;
struct bfa_mbox_cmd cmd;
u32 cmd_len;
u32 cmd_len;
/* Callback for port, tx, rx, rxf */
void (*cbfn)(void *arg, int status);
void *cbarg;
void *cbarg;
};
struct bna_mbox_mod {
@ -480,7 +480,7 @@ struct bna_ib_dbell {
/* Interrupt timer configuration */
struct bna_ib_config {
u8 coalescing_timeo; /* Unit is 5usec. */
u8 coalescing_timeo; /* Unit is 5usec. */
int interpkt_count;
int interpkt_timeo;
@ -576,8 +576,8 @@ struct bna_txq {
struct bna_tx *tx;
u64 tx_packets;
u64 tx_bytes;
u64 tx_packets;
u64 tx_bytes;
};
/* TxF structure (hardware Tx Function) */
@ -739,10 +739,10 @@ struct bna_rxq {
struct bna_rxp *rxp;
struct bna_rx *rx;
u64 rx_packets;
u64 rx_packets;
u64 rx_bytes;
u64 rx_packets_with_error;
u64 rxbuf_alloc_failed;
u64 rx_packets_with_error;
u64 rxbuf_alloc_failed;
};
/* RxQ pair */
@ -902,7 +902,7 @@ struct bna_rxf {
* callback for:
* bna_rxf_ucast_set()
* bna_rxf_{ucast/mcast}_add(),
* bna_rxf_{ucast/mcast}_del(),
* bna_rxf_{ucast/mcast}_del(),
* bna_rxf_mode_set()
*/
void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx,

44
drivers/net/bna/bnad.c
View File

@ -60,7 +60,7 @@ static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
#define BNAD_GET_MBOX_IRQ(_bnad) \
(((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \
((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \
((_bnad)->pcidev->irq))
#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
@ -112,10 +112,10 @@ static void
bnad_free_all_txbufs(struct bnad *bnad,
struct bna_tcb *tcb)
{
u32 unmap_cons;
u32 unmap_cons;
struct bnad_unmap_q *unmap_q = tcb->unmap_q;
struct bnad_skb_unmap *unmap_array;
struct sk_buff *skb = NULL;
struct sk_buff *skb = NULL;
int i;
unmap_array = unmap_q->unmap_array;
@ -165,11 +165,11 @@ static u32
bnad_free_txbufs(struct bnad *bnad,
struct bna_tcb *tcb)
{
u32 sent_packets = 0, sent_bytes = 0;
u16 wis, unmap_cons, updated_hw_cons;
u32 sent_packets = 0, sent_bytes = 0;
u16 wis, unmap_cons, updated_hw_cons;
struct bnad_unmap_q *unmap_q = tcb->unmap_q;
struct bnad_skb_unmap *unmap_array;
struct sk_buff *skb;
struct sk_buff *skb;
int i;
/*
@ -247,7 +247,7 @@ bnad_tx_free_tasklet(unsigned long bnad_ptr)
{
struct bnad *bnad = (struct bnad *)bnad_ptr;
struct bna_tcb *tcb;
u32 acked = 0;
u32 acked = 0;
int i, j;
for (i = 0; i < bnad->num_tx; i++) {
@ -1102,10 +1102,10 @@ static int
bnad_mbox_irq_alloc(struct bnad *bnad,
struct bna_intr_info *intr_info)
{
int err = 0;
unsigned long irq_flags, flags;
int err = 0;
unsigned long irq_flags, flags;
u32 irq;
irq_handler_t irq_handler;
irq_handler_t irq_handler;
/* Mbox should use only 1 vector */
@ -1447,7 +1447,7 @@ bnad_iocpf_sem_timeout(unsigned long data)
/*
* All timer routines use bnad->bna_lock to protect against
* the following race, which may occur in case of no locking:
* Time CPU m CPU n
* Time CPU m CPU n
* 0 1 = test_bit
* 1 clear_bit
* 2 del_timer_sync
@ -1912,7 +1912,7 @@ void
bnad_rx_coalescing_timeo_set(struct bnad *bnad)
{
struct bnad_rx_info *rx_info;
int i;
int i;
for (i = 0; i < bnad->num_rx; i++) {
rx_info = &bnad->rx_info[i];
@ -2426,18 +2426,18 @@ bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
{
struct bnad *bnad = netdev_priv(netdev);
u16 txq_prod, vlan_tag = 0;
u32 unmap_prod, wis, wis_used, wi_range;
u32 vectors, vect_id, i, acked;
u16 txq_prod, vlan_tag = 0;
u32 unmap_prod, wis, wis_used, wi_range;
u32 vectors, vect_id, i, acked;
u32 tx_id;
int err;
int err;
struct bnad_tx_info *tx_info;
struct bna_tcb *tcb;
struct bnad_unmap_q *unmap_q;
dma_addr_t dma_addr;
dma_addr_t dma_addr;
struct bna_txq_entry *txqent;
bna_txq_wi_ctrl_flag_t flags;
bna_txq_wi_ctrl_flag_t flags;
if (unlikely
(skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
@ -3033,8 +3033,8 @@ static int __devinit
bnad_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *pcidev_id)
{
bool using_dac = false;
int err;
bool using_dac = false;
int err;
struct bnad *bnad;
struct bna *bna;
struct net_device *netdev;
@ -3066,7 +3066,7 @@ bnad_pci_probe(struct pci_dev *pdev,
/*
* PCI initialization
* Output : using_dac = 1 for 64 bit DMA
* Output : using_dac = 1 for 64 bit DMA
* = 0 for 32 bit DMA
*/
err = bnad_pci_init(bnad, pdev, &using_dac);
@ -3209,7 +3209,7 @@ bnad_pci_remove(struct pci_dev *pdev)
free_netdev(netdev);
}
static const struct pci_device_id bnad_pci_id_table[] = {
static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = {
{
PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
PCI_DEVICE_ID_BROCADE_CT),

24
drivers/net/bna/bnad.h
View File

@ -70,8 +70,8 @@ struct bnad_rx_ctrl {
#define BNAD_MAILBOX_MSIX_VECTORS 1
#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
#define BNAD_MAX_Q_DEPTH 0x10000
#define BNAD_MIN_Q_DEPTH 0x200
@ -102,12 +102,12 @@ enum bnad_intr_source {
enum bnad_link_state {
BNAD_LS_DOWN = 0,
BNAD_LS_UP = 1
BNAD_LS_UP = 1
};
struct bnad_completion {
struct completion ioc_comp;
struct completion ucast_comp;
struct completion ioc_comp;
struct completion ucast_comp;
struct completion mcast_comp;
struct completion tx_comp;
struct completion rx_comp;
@ -125,7 +125,7 @@ struct bnad_completion {
/* Tx Rx Control Stats */
struct bnad_drv_stats {
u64 netif_queue_stop;
u64 netif_queue_stop;
u64 netif_queue_wakeup;
u64 netif_queue_stopped;
u64 tso4;
@ -188,7 +188,7 @@ struct bnad_skb_unmap {
struct bnad_unmap_q {
u32 producer_index;
u32 consumer_index;
u32 q_depth;
u32 q_depth;
/* This should be the last one */
struct bnad_skb_unmap unmap_array[1];
};
@ -211,7 +211,7 @@ struct bnad_unmap_q {
#define BNAD_RF_RX_SHUTDOWN_DELAYED 7
struct bnad {
struct net_device *netdev;
struct net_device *netdev;
/* Data path */
struct bnad_tx_info tx_info[BNAD_MAX_TXS];
@ -245,7 +245,7 @@ struct bnad {
u32 cfg_flags;
unsigned long run_flags;
struct pci_dev *pcidev;
struct pci_dev *pcidev;
u64 mmio_start;
u64 mmio_len;
@ -278,7 +278,7 @@ struct bnad {
struct bnad_diag *diag;
char adapter_name[BNAD_NAME_LEN];
char port_name[BNAD_NAME_LEN];
char port_name[BNAD_NAME_LEN];
char mbox_irq_name[BNAD_NAME_LEN];
};
@ -286,7 +286,7 @@ struct bnad {
* EXTERN VARIABLES
*/
extern struct firmware *bfi_fw;
extern u32 bnad_rxqs_per_cq;
extern u32 bnad_rxqs_per_cq;
/*
* EXTERN PROTOTYPES
@ -332,7 +332,7 @@ extern void bnad_netdev_hwstats_fill(struct bnad *bnad,
}
#define bnad_dim_timer_running(_bnad) \
(((_bnad)->cfg_flags & BNAD_CF_DIM_ENABLED) && \
(((_bnad)->cfg_flags & BNAD_CF_DIM_ENABLED) && \
(test_bit(BNAD_RF_DIM_TIMER_RUNNING, &((_bnad)->run_flags))))
#endif /* __BNAD_H__ */

2
drivers/net/bna/bnad_ethtool.c
View File

@ -295,7 +295,7 @@ get_regs(struct bnad *bnad, u32 * regs)
u32 reg_addr;
unsigned long flags;
#define BNAD_GET_REG(addr) \
#define BNAD_GET_REG(addr) \
do { \
if (regs) \
regs[num++] = readl(bnad->bar0 + (addr)); \