Hexagon: Provide basic implementation and/or stubs for I/O routines.
Signed-off-by: Richard Kuo <rkuo@codeaurora.org> Signed-off-by: Linas Vepstas <linas@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Richard Kuo
Linus Torvalds
parent
7567746e1c
commit
013bf24c38
326
arch/hexagon/include/asm/io.h
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326
arch/hexagon/include/asm/io.h
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/*
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* IO definitions for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/vmalloc.h>
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#include <asm/string.h>
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#include <asm/mem-layout.h>
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#include <asm/iomap.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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/*
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* We don't have PCI yet.
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* _IO_BASE is pointing at what should be unused virtual space.
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*/
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#define IO_SPACE_LIMIT 0xffff
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#define _IO_BASE ((void __iomem *)0xfe000000)
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extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
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unsigned long end, unsigned long flags);
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extern void __iounmap(const volatile void __iomem *addr);
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/* Defined in lib/io.c, needed for smc91x driver. */
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extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
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extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
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extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen);
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extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen);
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#define readsw(p, d, l) __raw_readsw(p, d, l)
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#define writesw(p, d, l) __raw_writesw(p, d, l)
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#define readsl(p, d, l) __raw_readsl(p, d, l)
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#define writesl(p, d, l) __raw_writesl(p, d, l)
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/*
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* virt_to_phys - map virtual address to physical
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* @address: address to map
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*/
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static inline unsigned long virt_to_phys(volatile void *address)
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{
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return __pa(address);
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}
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/*
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* phys_to_virt - map physical address to virtual
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* @address: address to map
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*/
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static inline void *phys_to_virt(unsigned long address)
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{
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return __va(address);
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}
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/*
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* convert a physical pointer to a virtual kernel pointer for
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* /dev/mem access.
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*/
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#define xlate_dev_kmem_ptr(p) __va(p)
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* IO port access primitives. Hexagon doesn't have special IO access
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* instructions; all I/O is memory mapped.
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*
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* in/out are used for "ports", but we don't have "port instructions",
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* so these are really just memory mapped too.
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*/
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/*
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* readb - read byte from memory mapped device
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* @addr: pointer to memory
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*
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* Operates on "I/O bus memory space"
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*/
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static inline u8 readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile(
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"%0 = memb(%1);"
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: "=&r" (val)
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: "r" (addr)
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);
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return val;
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}
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static inline u16 readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile(
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"%0 = memh(%1);"
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: "=&r" (val)
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: "r" (addr)
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);
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return val;
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}
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static inline u32 readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile(
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"%0 = memw(%1);"
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: "=&r" (val)
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: "r" (addr)
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);
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return val;
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}
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/*
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* writeb - write a byte to a memory location
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* @data: data to write to
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* @addr: pointer to memory
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*
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*/
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static inline void writeb(u8 data, volatile void __iomem *addr)
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{
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asm volatile(
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"memb(%0) = %1;"
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:
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: "r" (addr), "r" (data)
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: "memory"
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);
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}
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static inline void writew(u16 data, volatile void __iomem *addr)
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{
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asm volatile(
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"memh(%0) = %1;"
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:
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: "r" (addr), "r" (data)
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: "memory"
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);
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}
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static inline void writel(u32 data, volatile void __iomem *addr)
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{
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asm volatile(
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"memw(%0) = %1;"
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:
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: "r" (addr), "r" (data)
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: "memory"
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);
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}
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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/*
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* Need an mtype somewhere in here, for cache type deals?
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* This is probably too long for an inline.
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*/
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void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size);
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static inline void __iomem *ioremap(unsigned long phys_addr, unsigned long size)
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{
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return ioremap_nocache(phys_addr, size);
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}
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static inline void iounmap(volatile void __iomem *addr)
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{
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__iounmap(addr);
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}
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#define __raw_writel writel
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static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
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int count)
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{
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memcpy(dst, (void *) src, count);
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}
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static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
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int count)
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{
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memcpy((void *) dst, src, count);
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}
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#define PCI_IO_ADDR (volatile void __iomem *)
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/*
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* inb - read byte from I/O port or something
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* @port: address in I/O space
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*
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* Operates on "I/O bus I/O space"
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*/
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static inline u8 inb(unsigned long port)
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{
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return readb(_IO_BASE + (port & IO_SPACE_LIMIT));
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}
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static inline u16 inw(unsigned long port)
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{
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return readw(_IO_BASE + (port & IO_SPACE_LIMIT));
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}
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static inline u32 inl(unsigned long port)
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{
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return readl(_IO_BASE + (port & IO_SPACE_LIMIT));
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}
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/*
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* outb - write a byte to a memory location
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* @data: data to write to
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* @addr: address in I/O space
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*/
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static inline void outb(u8 data, unsigned long port)
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{
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writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT));
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}
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static inline void outw(u16 data, unsigned long port)
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{
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writew(data, _IO_BASE + (port & IO_SPACE_LIMIT));
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}
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static inline void outl(u32 data, unsigned long port)
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{
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writel(data, _IO_BASE + (port & IO_SPACE_LIMIT));
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}
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#define outb_p outb
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#define outw_p outw
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#define outl_p outl
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#define inb_p inb
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#define inw_p inw
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#define inl_p inl
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static inline void insb(unsigned long port, void *buffer, int count)
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{
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if (count) {
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u8 *buf = buffer;
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do {
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u8 x = inb(port);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void insw(unsigned long port, void *buffer, int count)
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{
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if (count) {
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u16 *buf = buffer;
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do {
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u16 x = inw(port);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void insl(unsigned long port, void *buffer, int count)
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{
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if (count) {
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u32 *buf = buffer;
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do {
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u32 x = inw(port);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void outsb(unsigned long port, const void *buffer, int count)
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{
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if (count) {
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const u8 *buf = buffer;
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do {
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outb(*buf++, port);
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} while (--count);
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}
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}
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static inline void outsw(unsigned long port, const void *buffer, int count)
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{
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if (count) {
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const u16 *buf = buffer;
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do {
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outw(*buf++, port);
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} while (--count);
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}
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}
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static inline void outsl(unsigned long port, const void *buffer, int count)
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{
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if (count) {
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const u32 *buf = buffer;
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do {
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outl(*buf++, port);
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} while (--count);
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}
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}
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#define flush_write_buffers() do { } while (0)
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#endif /* __KERNEL__ */
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#endif
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91
arch/hexagon/lib/io.c
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91
arch/hexagon/lib/io.c
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@ -0,0 +1,91 @@
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/*
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* I/O access functions for Hexagon
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*
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <asm/io.h>
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/* These are all FIFO routines! */
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/*
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* __raw_readsw - read words a short at a time
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* @addr: source address
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* @data: data address
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* @len: number of shorts to read
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*/
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void __raw_readsw(const void __iomem *addr, void *data, int len)
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{
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const volatile short int *src = (short int *) addr;
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short int *dst = (short int *) data;
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if ((u32)data & 0x1)
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panic("unaligned pointer to readsw");
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while (len-- > 0)
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*dst++ = *src;
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}
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/*
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* __raw_writesw - read words a short at a time
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* @addr: source address
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* @data: data address
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* @len: number of shorts to read
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*/
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void __raw_writesw(void __iomem *addr, const void *data, int len)
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{
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const short int *src = (short int *)data;
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volatile short int *dst = (short int *)addr;
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if ((u32)data & 0x1)
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panic("unaligned pointer to writesw");
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while (len-- > 0)
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*dst = *src++;
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}
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/* Pretty sure len is pre-adjusted for the length of the access already */
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void __raw_readsl(const void __iomem *addr, void *data, int len)
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{
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const volatile long *src = (long *) addr;
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long *dst = (long *) data;
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if ((u32)data & 0x3)
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panic("unaligned pointer to readsl");
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while (len-- > 0)
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*dst++ = *src;
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}
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void __raw_writesl(void __iomem *addr, const void *data, int len)
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{
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const long *src = (long *)data;
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volatile long *dst = (long *)addr;
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if ((u32)data & 0x3)
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panic("unaligned pointer to writesl");
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while (len-- > 0)
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*dst = *src++;
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}
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