mtd: spi-nor: Move Spansion bits out of core.c
Create a SPI NOR manufacturer driver for Spansion chips, and move the Spansion definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This commit is contained in:
Boris Brezillon
Tudor Ambarus
parent
15f5c7e54e
commit
0173c32a0e
@ -11,4 +11,5 @@ spi-nor-objs += intel.o
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spi-nor-objs += issi.o
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spi-nor-objs += macronix.o
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spi-nor-objs += micron-st.o
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spi-nor-objs += spansion.o
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obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
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@ -1995,44 +1995,6 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
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* old entries may be missing 4K flag.
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*/
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static const struct flash_info spi_nor_ids[] = {
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/* Spansion/Cypress -- single (large) sector size only, at least
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* for the chips listed here (without boot sectors).
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*/
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
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{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | USE_CLSR) },
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{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
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{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
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{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
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{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
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{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
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{ "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
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{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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{ "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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/* SST -- large erase sizes are "overlays", "sectors" are 4K */
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{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
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{ "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
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@ -2151,6 +2113,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
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&spi_nor_macronix,
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&spi_nor_micron,
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&spi_nor_st,
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&spi_nor_spansion,
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};
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static const struct flash_info *
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@ -3084,17 +3047,6 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
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spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
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}
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static void spansion_post_sfdp_fixups(struct spi_nor *nor)
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{
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if (nor->params.size <= SZ_16M)
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return;
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nor->flags |= SNOR_F_4B_OPCODES;
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/* No small sector erase for 4-byte command set */
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nor->erase_opcode = SPINOR_OP_SE;
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nor->mtd.erasesize = nor->info->sector_size;
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}
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static void s3an_post_sfdp_fixups(struct spi_nor *nor)
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{
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nor->params.setup = s3an_nor_setup;
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@ -3112,15 +3064,6 @@ static void s3an_post_sfdp_fixups(struct spi_nor *nor)
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*/
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static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
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{
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switch (JEDEC_MFR(nor->info)) {
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case SNOR_MFR_SPANSION:
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spansion_post_sfdp_fixups(nor);
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break;
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default:
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break;
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}
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if (nor->info->flags & SPI_S3AN)
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s3an_post_sfdp_fixups(nor);
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@ -178,6 +178,7 @@ extern const struct spi_nor_manufacturer spi_nor_issi;
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extern const struct spi_nor_manufacturer spi_nor_macronix;
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extern const struct spi_nor_manufacturer spi_nor_micron;
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extern const struct spi_nor_manufacturer spi_nor_st;
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extern const struct spi_nor_manufacturer spi_nor_spansion;
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int spi_nor_write_enable(struct spi_nor *nor);
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int spi_nor_write_disable(struct spi_nor *nor);
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95
drivers/mtd/spi-nor/spansion.c
Normal file
95
drivers/mtd/spi-nor/spansion.c
Normal file
@ -0,0 +1,95 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static const struct flash_info spansion_parts[] = {
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/* Spansion/Cypress -- single (large) sector size only, at least
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* for the chips listed here (without boot sectors).
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*/
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
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{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | USE_CLSR) },
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{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
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{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
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{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
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{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
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{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
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{ "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
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{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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};
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static void spansion_post_sfdp_fixups(struct spi_nor *nor)
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{
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if (nor->params.size <= SZ_16M)
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return;
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nor->flags |= SNOR_F_4B_OPCODES;
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/* No small sector erase for 4-byte command set */
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nor->erase_opcode = SPINOR_OP_SE;
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nor->mtd.erasesize = nor->info->sector_size;
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}
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static const struct spi_nor_fixups spansion_fixups = {
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.post_sfdp = spansion_post_sfdp_fixups,
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};
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const struct spi_nor_manufacturer spi_nor_spansion = {
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.name = "spansion",
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.parts = spansion_parts,
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.nparts = ARRAY_SIZE(spansion_parts),
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.fixups = &spansion_fixups,
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};
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