selftests/bpf: verifier/div0.c converted to inline assembly
Test verifier/div0.c automatically converted to use inline assembly. Signed-off-by: Eduard Zingerman <eddyz87@gmail.com> Link: https://lore.kernel.org/r/20230325025524.144043-19-eddyz87@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
This commit is contained in:
Eduard Zingerman
Alexei Starovoitov
parent
84988478fb
commit
01a0925531
@ -15,6 +15,7 @@
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#include "verifier_const_or.skel.h"
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#include "verifier_ctx_sk_msg.skel.h"
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#include "verifier_direct_stack_access_wraparound.skel.h"
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#include "verifier_div0.skel.h"
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__maybe_unused
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static void run_tests_aux(const char *skel_name, skel_elf_bytes_fn elf_bytes_factory)
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@ -52,3 +53,4 @@ void test_verifier_cgroup_storage(void) { RUN(verifier_cgroup_storage); }
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void test_verifier_const_or(void) { RUN(verifier_const_or); }
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void test_verifier_ctx_sk_msg(void) { RUN(verifier_ctx_sk_msg); }
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void test_verifier_direct_stack_access_wraparound(void) { RUN(verifier_direct_stack_access_wraparound); }
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void test_verifier_div0(void) { RUN(verifier_div0); }
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213
tools/testing/selftests/bpf/progs/verifier_div0.c
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213
tools/testing/selftests/bpf/progs/verifier_div0.c
Normal file
@ -0,0 +1,213 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Converted from tools/testing/selftests/bpf/verifier/div0.c */
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#include <linux/bpf.h>
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#include <bpf/bpf_helpers.h>
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#include "bpf_misc.h"
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SEC("socket")
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__description("DIV32 by 0, zero check 1")
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__success __success_unpriv __retval(42)
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__naked void by_0_zero_check_1_1(void)
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{
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asm volatile (" \
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w0 = 42; \
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w1 = 0; \
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w2 = 1; \
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w2 /= w1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("socket")
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__description("DIV32 by 0, zero check 2")
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__success __success_unpriv __retval(42)
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__naked void by_0_zero_check_2_1(void)
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{
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asm volatile (" \
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w0 = 42; \
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r1 = 0xffffffff00000000LL ll; \
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w2 = 1; \
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w2 /= w1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("socket")
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__description("DIV64 by 0, zero check")
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__success __success_unpriv __retval(42)
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__naked void div64_by_0_zero_check(void)
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{
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asm volatile (" \
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w0 = 42; \
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w1 = 0; \
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w2 = 1; \
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r2 /= r1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("socket")
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__description("MOD32 by 0, zero check 1")
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__success __success_unpriv __retval(42)
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__naked void by_0_zero_check_1_2(void)
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{
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asm volatile (" \
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w0 = 42; \
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w1 = 0; \
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w2 = 1; \
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w2 %%= w1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("socket")
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__description("MOD32 by 0, zero check 2")
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__success __success_unpriv __retval(42)
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__naked void by_0_zero_check_2_2(void)
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{
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asm volatile (" \
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w0 = 42; \
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r1 = 0xffffffff00000000LL ll; \
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w2 = 1; \
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w2 %%= w1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("socket")
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__description("MOD64 by 0, zero check")
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__success __success_unpriv __retval(42)
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__naked void mod64_by_0_zero_check(void)
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{
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asm volatile (" \
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w0 = 42; \
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w1 = 0; \
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w2 = 1; \
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r2 %%= r1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("DIV32 by 0, zero check ok, cls")
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__success __retval(8)
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__naked void _0_zero_check_ok_cls_1(void)
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{
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asm volatile (" \
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w0 = 42; \
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w1 = 2; \
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w2 = 16; \
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w2 /= w1; \
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r0 = r2; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("DIV32 by 0, zero check 1, cls")
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__success __retval(0)
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__naked void _0_zero_check_1_cls_1(void)
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{
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asm volatile (" \
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w1 = 0; \
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w0 = 1; \
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w0 /= w1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("DIV32 by 0, zero check 2, cls")
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__success __retval(0)
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__naked void _0_zero_check_2_cls_1(void)
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{
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asm volatile (" \
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r1 = 0xffffffff00000000LL ll; \
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w0 = 1; \
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w0 /= w1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("DIV64 by 0, zero check, cls")
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__success __retval(0)
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__naked void by_0_zero_check_cls(void)
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{
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asm volatile (" \
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w1 = 0; \
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w0 = 1; \
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r0 /= r1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("MOD32 by 0, zero check ok, cls")
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__success __retval(2)
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__naked void _0_zero_check_ok_cls_2(void)
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{
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asm volatile (" \
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w0 = 42; \
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w1 = 3; \
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w2 = 5; \
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w2 %%= w1; \
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r0 = r2; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("MOD32 by 0, zero check 1, cls")
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__success __retval(1)
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__naked void _0_zero_check_1_cls_2(void)
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{
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asm volatile (" \
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w1 = 0; \
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w0 = 1; \
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w0 %%= w1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("MOD32 by 0, zero check 2, cls")
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__success __retval(1)
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__naked void _0_zero_check_2_cls_2(void)
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{
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asm volatile (" \
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r1 = 0xffffffff00000000LL ll; \
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w0 = 1; \
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w0 %%= w1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("MOD64 by 0, zero check 1, cls")
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__success __retval(2)
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__naked void _0_zero_check_1_cls_3(void)
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{
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asm volatile (" \
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w1 = 0; \
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w0 = 2; \
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r0 %%= r1; \
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exit; \
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" ::: __clobber_all);
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}
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SEC("tc")
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__description("MOD64 by 0, zero check 2, cls")
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__success __retval(-1)
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__naked void _0_zero_check_2_cls_3(void)
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{
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asm volatile (" \
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w1 = 0; \
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w0 = -1; \
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r0 %%= r1; \
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exit; \
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" ::: __clobber_all);
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}
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char _license[] SEC("license") = "GPL";
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@ -1,184 +0,0 @@
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{
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"DIV32 by 0, zero check 1",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 42),
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_2, 1),
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BPF_ALU32_REG(BPF_DIV, BPF_REG_2, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 42,
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},
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{
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"DIV32 by 0, zero check 2",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 42),
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BPF_LD_IMM64(BPF_REG_1, 0xffffffff00000000LL),
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BPF_MOV32_IMM(BPF_REG_2, 1),
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BPF_ALU32_REG(BPF_DIV, BPF_REG_2, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 42,
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},
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{
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"DIV64 by 0, zero check",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 42),
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_2, 1),
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BPF_ALU64_REG(BPF_DIV, BPF_REG_2, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 42,
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},
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{
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"MOD32 by 0, zero check 1",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 42),
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_2, 1),
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BPF_ALU32_REG(BPF_MOD, BPF_REG_2, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 42,
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},
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{
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"MOD32 by 0, zero check 2",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 42),
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BPF_LD_IMM64(BPF_REG_1, 0xffffffff00000000LL),
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BPF_MOV32_IMM(BPF_REG_2, 1),
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BPF_ALU32_REG(BPF_MOD, BPF_REG_2, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 42,
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},
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{
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"MOD64 by 0, zero check",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 42),
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_2, 1),
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BPF_ALU64_REG(BPF_MOD, BPF_REG_2, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 42,
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},
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{
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"DIV32 by 0, zero check ok, cls",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 42),
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BPF_MOV32_IMM(BPF_REG_1, 2),
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BPF_MOV32_IMM(BPF_REG_2, 16),
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BPF_ALU32_REG(BPF_DIV, BPF_REG_2, BPF_REG_1),
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BPF_MOV64_REG(BPF_REG_0, BPF_REG_2),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 8,
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},
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{
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"DIV32 by 0, zero check 1, cls",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_0, 1),
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BPF_ALU32_REG(BPF_DIV, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 0,
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},
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{
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"DIV32 by 0, zero check 2, cls",
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.insns = {
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BPF_LD_IMM64(BPF_REG_1, 0xffffffff00000000LL),
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BPF_MOV32_IMM(BPF_REG_0, 1),
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BPF_ALU32_REG(BPF_DIV, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 0,
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},
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{
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"DIV64 by 0, zero check, cls",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_0, 1),
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BPF_ALU64_REG(BPF_DIV, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 0,
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},
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{
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"MOD32 by 0, zero check ok, cls",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 42),
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BPF_MOV32_IMM(BPF_REG_1, 3),
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BPF_MOV32_IMM(BPF_REG_2, 5),
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BPF_ALU32_REG(BPF_MOD, BPF_REG_2, BPF_REG_1),
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BPF_MOV64_REG(BPF_REG_0, BPF_REG_2),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 2,
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},
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{
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"MOD32 by 0, zero check 1, cls",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_0, 1),
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BPF_ALU32_REG(BPF_MOD, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"MOD32 by 0, zero check 2, cls",
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.insns = {
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BPF_LD_IMM64(BPF_REG_1, 0xffffffff00000000LL),
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BPF_MOV32_IMM(BPF_REG_0, 1),
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BPF_ALU32_REG(BPF_MOD, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"MOD64 by 0, zero check 1, cls",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_0, 2),
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BPF_ALU64_REG(BPF_MOD, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 2,
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},
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{
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"MOD64 by 0, zero check 2, cls",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_1, 0),
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BPF_MOV32_IMM(BPF_REG_0, -1),
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BPF_ALU64_REG(BPF_MOD, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = -1,
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},
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