drm/amdgpu: Modify .ras_fini function pointer parameter
Modify .ras_fini function pointer parameter so that we can remove redundant intermediate calls in some ras blocks. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -644,7 +644,7 @@ late_fini:
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return r;
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}
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void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
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void amdgpu_gfx_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
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adev->gfx.ras_if)
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@ -387,7 +387,7 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
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void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
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int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
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int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
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void amdgpu_gfx_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
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void *err_data,
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struct amdgpu_iv_entry *entry);
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@ -455,16 +455,16 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
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void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
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{
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if (adev->umc.ras && adev->umc.ras->ras_block.ras_fini)
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adev->umc.ras->ras_block.ras_fini(adev);
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adev->umc.ras->ras_block.ras_fini(adev, NULL);
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if (adev->mmhub.ras && adev->mmhub.ras->ras_block.ras_fini)
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adev->mmhub.ras->ras_block.ras_fini(adev);
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adev->mmhub.ras->ras_block.ras_fini(adev, NULL);
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if (adev->gmc.xgmi.ras && adev->gmc.xgmi.ras->ras_block.ras_fini)
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adev->gmc.xgmi.ras->ras_block.ras_fini(adev);
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adev->gmc.xgmi.ras->ras_block.ras_fini(adev, NULL);
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if (adev->hdp.ras && adev->hdp.ras->ras_block.ras_fini)
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adev->hdp.ras->ras_block.ras_fini(adev);
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adev->hdp.ras->ras_block.ras_fini(adev, NULL);
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}
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/*
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@ -24,7 +24,7 @@
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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void amdgpu_hdp_ras_fini(struct amdgpu_device *adev)
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void amdgpu_hdp_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP) &&
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adev->hdp.ras_if)
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@ -44,5 +44,5 @@ struct amdgpu_hdp {
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};
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int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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void amdgpu_hdp_ras_fini(struct amdgpu_device *adev);
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void amdgpu_hdp_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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#endif /* __AMDGPU_HDP_H__ */
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@ -24,7 +24,7 @@
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev)
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void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
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adev->mmhub.ras_if)
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@ -47,6 +47,6 @@ struct amdgpu_mmhub {
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struct amdgpu_mmhub_ras *ras;
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};
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void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev);
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void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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#endif
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@ -44,7 +44,7 @@ late_fini:
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return r;
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}
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void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
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void amdgpu_nbio_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
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adev->nbio.ras_if)
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@ -105,5 +105,5 @@ struct amdgpu_nbio {
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};
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int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
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void amdgpu_nbio_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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#endif
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@ -491,7 +491,7 @@ struct amdgpu_ras_block_object {
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int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
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enum amdgpu_ras_block block, uint32_t sub_block_index);
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int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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void (*ras_fini)(struct amdgpu_device *adev);
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void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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ras_ih_cb ras_cb;
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const struct amdgpu_ras_block_hw_ops *hw_ops;
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};
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@ -111,7 +111,7 @@ late_fini:
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return r;
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}
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void amdgpu_sdma_ras_fini(struct amdgpu_device *adev)
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void amdgpu_sdma_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
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adev->sdma.ras_if)
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@ -118,7 +118,7 @@ int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
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uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
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int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
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struct ras_common_if *ras_block);
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void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
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void amdgpu_sdma_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
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void *err_data,
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struct amdgpu_iv_entry *entry);
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@ -162,7 +162,7 @@ late_fini:
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return r;
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}
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void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
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void amdgpu_umc_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
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adev->umc.ras_if)
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@ -73,7 +73,7 @@ struct amdgpu_umc {
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};
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int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
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void amdgpu_umc_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
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void *ras_error_status,
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bool reset);
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@ -768,7 +768,7 @@ static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_comm
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return amdgpu_ras_block_late_init(adev, ras_block);
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}
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static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
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static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
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adev->gmc.xgmi.ras_if)
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@ -2433,7 +2433,7 @@ static int gfx_v9_0_sw_fini(void *handle)
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->gfx.ras && adev->gfx.ras->ras_block.ras_fini)
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adev->gfx.ras->ras_block.ras_fini(adev);
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adev->gfx.ras->ras_block.ras_fini(adev, NULL);
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for (i = 0; i < adev->gfx.num_gfx_rings; i++)
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amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
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@ -37,7 +37,7 @@ static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
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ras_error_status);
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}
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static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev)
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static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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amdgpu_mca_ras_fini(adev, &adev->mca.mp0);
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}
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@ -83,7 +83,7 @@ static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
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ras_error_status);
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}
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static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev)
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static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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amdgpu_mca_ras_fini(adev, &adev->mca.mp1);
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}
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@ -115,7 +115,7 @@ static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
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ras_error_status);
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}
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static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev)
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static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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amdgpu_mca_ras_fini(adev, &adev->mca.mpio);
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}
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@ -1997,7 +1997,7 @@ static int sdma_v4_0_sw_fini(void *handle)
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if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
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adev->sdma.ras->ras_block.ras_fini)
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adev->sdma.ras->ras_block.ras_fini(adev);
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adev->sdma.ras->ras_block.ras_fini(adev, NULL);
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for (i = 0; i < adev->sdma.num_instances; i++) {
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amdgpu_ring_fini(&adev->sdma.instance[i].ring);
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@ -1215,7 +1215,7 @@ static int soc15_common_sw_fini(void *handle)
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->nbio.ras && adev->nbio.ras->ras_block.ras_fini)
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adev->nbio.ras->ras_block.ras_fini(adev);
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adev->nbio.ras->ras_block.ras_fini(adev, NULL);
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if (adev->df.funcs &&
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adev->df.funcs->sw_fini)
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