staging: comedi: ni_pcidio.c: Spaces preferred around operators
Fix the checkpatch.pl issue: CHECK: spaces preferred around that '|' (ctx:VxV) Signed-off-by: Saber Rezvani <irsaber@gmail.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -65,7 +65,7 @@
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#define WindowAddressStatus_mask 0x7c
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#define WindowAddressStatus_mask 0x7c
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#define Master_DMA_And_Interrupt_Control 5 /* W */
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#define Master_DMA_And_Interrupt_Control 5 /* W */
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#define InterruptLine(x) ((x)&3)
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#define InterruptLine(x) ((x) & 3)
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#define OpenInt BIT(2)
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#define OpenInt BIT(2)
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#define Group_Status 5 /* R */
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#define Group_Status 5 /* R */
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#define DataLeft BIT(0)
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#define DataLeft BIT(0)
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@ -100,38 +100,38 @@
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#define Chip_ID_I 25
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#define Chip_ID_I 25
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#define Chip_ID_O 26
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#define Chip_ID_O 26
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#define Chip_Version 27
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#define Chip_Version 27
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#define Port_IO(x) (28+(x))
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#define Port_IO(x) (28 + (x))
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#define Port_Pin_Directions(x) (32+(x))
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#define Port_Pin_Directions(x) (32 + (x))
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#define Port_Pin_Mask(x) (36+(x))
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#define Port_Pin_Mask(x) (36 + (x))
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#define Port_Pin_Polarities(x) (40+(x))
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#define Port_Pin_Polarities(x) (40 + (x))
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#define Master_Clock_Routing 45
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#define Master_Clock_Routing 45
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#define RTSIClocking(x) (((x)&3)<<4)
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#define RTSIClocking(x) (((x) & 3) << 4)
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#define Group_1_Second_Clear 46 /* W */
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#define Group_1_Second_Clear 46 /* W */
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#define Group_2_Second_Clear 47 /* W */
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#define Group_2_Second_Clear 47 /* W */
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#define ClearExpired BIT(0)
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#define ClearExpired BIT(0)
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#define Port_Pattern(x) (48+(x))
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#define Port_Pattern(x) (48 + (x))
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#define Data_Path 64
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#define Data_Path 64
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#define FIFOEnableA BIT(0)
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#define FIFOEnableA BIT(0)
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#define FIFOEnableB BIT(1)
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#define FIFOEnableB BIT(1)
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#define FIFOEnableC BIT(2)
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#define FIFOEnableC BIT(2)
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#define FIFOEnableD BIT(3)
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#define FIFOEnableD BIT(3)
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#define Funneling(x) (((x)&3)<<4)
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#define Funneling(x) (((x) & 3) << 4)
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#define GroupDirection BIT(7)
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#define GroupDirection BIT(7)
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#define Protocol_Register_1 65
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#define Protocol_Register_1 65
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#define OpMode Protocol_Register_1
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#define OpMode Protocol_Register_1
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#define RunMode(x) ((x)&7)
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#define RunMode(x) ((x) & 7)
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#define Numbered BIT(3)
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#define Numbered BIT(3)
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#define Protocol_Register_2 66
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#define Protocol_Register_2 66
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#define ClockReg Protocol_Register_2
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#define ClockReg Protocol_Register_2
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#define ClockLine(x) (((x)&3)<<5)
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#define ClockLine(x) (((x) & 3) << 5)
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#define InvertStopTrig BIT(7)
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#define InvertStopTrig BIT(7)
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#define DataLatching(x) (((x)&3)<<5)
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#define DataLatching(x) (((x) & 3) << 5)
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#define Protocol_Register_3 67
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#define Protocol_Register_3 67
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#define Sequence Protocol_Register_3
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#define Sequence Protocol_Register_3
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@ -141,13 +141,13 @@
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#define Protocol_Register_4 70
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#define Protocol_Register_4 70
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#define ReqReg Protocol_Register_4
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#define ReqReg Protocol_Register_4
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#define ReqConditioning(x) (((x)&7)<<3)
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#define ReqConditioning(x) (((x) & 7) << 3)
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#define Protocol_Register_5 71
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#define Protocol_Register_5 71
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#define BlockMode Protocol_Register_5
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#define BlockMode Protocol_Register_5
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#define FIFO_Control 72
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#define FIFO_Control 72
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#define ReadyLevel(x) ((x)&7)
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#define ReadyLevel(x) ((x) & 7)
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#define Protocol_Register_6 73
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#define Protocol_Register_6 73
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#define LinePolarities Protocol_Register_6
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#define LinePolarities Protocol_Register_6
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@ -160,7 +160,7 @@
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#define Protocol_Register_7 74
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#define Protocol_Register_7 74
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#define AckSer Protocol_Register_7
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#define AckSer Protocol_Register_7
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#define AckLine(x) (((x)&3)<<2)
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#define AckLine(x) (((x) & 3) << 2)
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#define ExchangePins BIT(7)
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#define ExchangePins BIT(7)
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#define Interrupt_Control 75
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#define Interrupt_Control 75
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@ -180,15 +180,15 @@ static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
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}
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}
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#define Transfer_Size_Control 77
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#define Transfer_Size_Control 77
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#define TransferWidth(x) ((x)&3)
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#define TransferWidth(x) ((x) & 3)
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#define TransferLength(x) (((x)&3)<<3)
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#define TransferLength(x) (((x) & 3) << 3)
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#define RequireRLevel BIT(5)
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#define RequireRLevel BIT(5)
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#define Protocol_Register_15 79
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#define Protocol_Register_15 79
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#define DAQOptions Protocol_Register_15
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#define DAQOptions Protocol_Register_15
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#define StartSource(x) ((x)&0x3)
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#define StartSource(x) ((x) & 0x3)
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#define InvertStart BIT(2)
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#define InvertStart BIT(2)
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#define StopSource(x) (((x)&0x3)<<3)
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#define StopSource(x) (((x) & 0x3) << 3)
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#define ReqStart BIT(6)
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#define ReqStart BIT(6)
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#define PreStart BIT(7)
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#define PreStart BIT(7)
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@ -255,9 +255,9 @@ enum FPGA_Control_Bits {
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#define TIMER_BASE 50 /* nanoseconds */
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#define TIMER_BASE 50 /* nanoseconds */
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#ifdef USE_DMA
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#ifdef USE_DMA
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#define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
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#define IntEn (CountExpired | Waited | PrimaryTC | SecondaryTC)
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#else
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#else
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#define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
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#define IntEn (TransferReady | CountExpired | Waited | PrimaryTC | SecondaryTC)
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#endif
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#endif
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enum nidio_boardid {
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enum nidio_boardid {
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