net: phy: add genphy_c45_ethtool_get/set_eee() support
Add replacement for phy_ethtool_get/set_eee() functions. Current phy_ethtool_get/set_eee() implementation is great and it is possible to make it even better: - this functionality is for devices implementing parts of IEEE 802.3 specification beyond Clause 22. The better place for this code is phy-c45.c - currently it is able to do read/write operations on PHYs with different abilities to not existing registers. It is better to use stored supported_eee abilities to avoid false read/write operations. - the eee_active detection will provide wrong results on not supported link modes. It is better to validate speed/duplex properties against supported EEE link modes. - it is able to support only limited amount of link modes. We have more EEE link modes... By refactoring this code I address most of this point except of the last one. Adding additional EEE link modes will need more work. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Oleksij Rempel
David S. Miller
parent
cf9f607969
commit
022c3f87f8
@ -661,6 +661,129 @@ int genphy_c45_read_mdix(struct phy_device *phydev)
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
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/**
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* genphy_c45_write_eee_adv - write advertised EEE link modes
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* @phydev: target phy_device struct
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* @adv: the linkmode advertisement settings
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*/
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int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv)
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{
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int val, changed;
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if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) {
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val = linkmode_to_mii_eee_cap1_t(adv);
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/* In eee_broken_modes are stored MDIO_AN_EEE_ADV specific raw
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* register values.
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*/
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val &= ~phydev->eee_broken_modes;
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/* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1
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* (Register 7.60)
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*/
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val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
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MDIO_AN_EEE_ADV,
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MDIO_EEE_100TX | MDIO_EEE_1000T |
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MDIO_EEE_10GT | MDIO_EEE_1000KX |
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MDIO_EEE_10GKX4 | MDIO_EEE_10GKR,
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val);
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if (val < 0)
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return val;
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if (val > 0)
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changed = 1;
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}
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
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phydev->supported_eee)) {
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val = linkmode_adv_to_mii_10base_t1_t(adv);
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/* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
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* (Register 7.526)
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*/
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val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
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MDIO_AN_10BT1_AN_CTRL,
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MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L,
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val);
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if (val < 0)
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return val;
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if (val > 0)
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changed = 1;
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}
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return changed;
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}
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/**
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* genphy_c45_read_eee_adv - read advertised EEE link modes
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* @phydev: target phy_device struct
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* @adv: the linkmode advertisement status
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*/
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static int genphy_c45_read_eee_adv(struct phy_device *phydev,
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unsigned long *adv)
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{
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int val;
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if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) {
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/* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1
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* (Register 7.60)
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*/
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
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if (val < 0)
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return val;
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mii_eee_cap1_mod_linkmode_t(adv, val);
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}
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
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phydev->supported_eee)) {
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/* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
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* (Register 7.526)
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*/
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL);
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if (val < 0)
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return val;
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mii_10base_t1_adv_mod_linkmode_t(adv, val);
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}
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return 0;
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}
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/**
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* genphy_c45_read_eee_lpa - read advertised LP EEE link modes
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* @phydev: target phy_device struct
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* @lpa: the linkmode LP advertisement status
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*/
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static int genphy_c45_read_eee_lpa(struct phy_device *phydev,
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unsigned long *lpa)
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{
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int val;
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if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) {
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/* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1
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* (Register 7.61)
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*/
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
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if (val < 0)
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return val;
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mii_eee_cap1_mod_linkmode_t(lpa, val);
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}
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
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phydev->supported_eee)) {
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/* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register
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* (Register 7.527)
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*/
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT);
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if (val < 0)
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return val;
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mii_10base_t1_adv_mod_linkmode_t(lpa, val);
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}
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return 0;
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}
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/**
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* genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20
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* @phydev: target phy_device struct
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@ -1194,6 +1317,121 @@ int genphy_c45_plca_get_status(struct phy_device *phydev,
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}
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EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status);
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/**
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* genphy_c45_eee_is_active - get EEE status
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* @phydev: target phy_device struct
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* @adv: variable to store advertised linkmodes
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* @lp: variable to store LP advertised linkmodes
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* @is_enabled: variable to store EEE enabled/disabled configuration value
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*
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* Description: this function will read local and link partner PHY
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* advertisements. Compare them return current EEE state.
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*/
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int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv,
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unsigned long *lp, bool *is_enabled)
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{
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__ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_adv) = {};
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__ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {};
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__ETHTOOL_DECLARE_LINK_MODE_MASK(common);
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bool eee_enabled, eee_active;
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int ret;
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ret = genphy_c45_read_eee_adv(phydev, tmp_adv);
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if (ret)
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return ret;
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ret = genphy_c45_read_eee_lpa(phydev, tmp_lp);
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if (ret)
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return ret;
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eee_enabled = !linkmode_empty(tmp_adv);
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linkmode_and(common, tmp_adv, tmp_lp);
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if (eee_enabled && !linkmode_empty(common))
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eee_active = phy_check_valid(phydev->speed, phydev->duplex,
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common);
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else
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eee_active = false;
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if (adv)
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linkmode_copy(adv, tmp_adv);
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if (lp)
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linkmode_copy(lp, tmp_lp);
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if (is_enabled)
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*is_enabled = eee_enabled;
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return eee_active;
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}
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EXPORT_SYMBOL(genphy_c45_eee_is_active);
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/**
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* genphy_c45_ethtool_get_eee - get EEE supported and status
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* @phydev: target phy_device struct
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* @data: ethtool_eee data
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*
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* Description: it reports the Supported/Advertisement/LP Advertisement
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* capabilities.
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*/
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int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
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struct ethtool_eee *data)
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{
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__ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {};
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__ETHTOOL_DECLARE_LINK_MODE_MASK(lp) = {};
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bool overflow = false, is_enabled;
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int ret;
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ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled);
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if (ret < 0)
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return ret;
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data->eee_enabled = is_enabled;
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data->eee_active = ret;
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if (!ethtool_convert_link_mode_to_legacy_u32(&data->supported,
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phydev->supported_eee))
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overflow = true;
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if (!ethtool_convert_link_mode_to_legacy_u32(&data->advertised, adv))
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overflow = true;
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if (!ethtool_convert_link_mode_to_legacy_u32(&data->lp_advertised, lp))
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overflow = true;
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if (overflow)
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phydev_warn(phydev, "Not all supported or advertised EEE link modes were passed to the user space\n");
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return 0;
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}
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EXPORT_SYMBOL(genphy_c45_ethtool_get_eee);
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/**
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* genphy_c45_ethtool_set_eee - get EEE supported and status
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* @phydev: target phy_device struct
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* @data: ethtool_eee data
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*
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* Description: it reportes the Supported/Advertisement/LP Advertisement
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* capabilities.
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*/
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int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
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struct ethtool_eee *data)
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{
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__ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {};
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int ret;
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if (data->eee_enabled) {
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if (data->advertised)
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adv[0] = data->advertised;
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else
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linkmode_copy(adv, phydev->supported_eee);
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}
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ret = genphy_c45_write_eee_adv(phydev, adv);
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if (ret < 0)
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return ret;
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if (ret > 0)
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return phy_restart_aneg(phydev);
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return 0;
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}
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EXPORT_SYMBOL(genphy_c45_ethtool_set_eee);
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struct phy_driver genphy_c45_driver = {
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.phy_id = 0xffffffff,
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.phy_id_mask = 0xffffffff,
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@ -428,6 +428,64 @@ static inline void mii_eee_cap1_mod_linkmode_t(unsigned long *adv, u32 val)
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adv, val & MDIO_EEE_10GKR);
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}
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/**
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* linkmode_to_mii_eee_cap1_t()
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* @adv: the linkmode advertisement settings
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*
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* A function that translates linkmode to value for IEEE 802.3-2018 45.2.7.13
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* "EEE advertisement 1" register (7.60)
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*/
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static inline u32 linkmode_to_mii_eee_cap1_t(unsigned long *adv)
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{
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u32 result = 0;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, adv))
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result |= MDIO_EEE_100TX;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, adv))
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result |= MDIO_EEE_1000T;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, adv))
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result |= MDIO_EEE_10GT;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, adv))
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result |= MDIO_EEE_1000KX;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, adv))
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result |= MDIO_EEE_10GKX4;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, adv))
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result |= MDIO_EEE_10GKR;
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return result;
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}
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/**
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* mii_10base_t1_adv_mod_linkmode_t()
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* @adv: linkmode advertisement settings
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* @val: register value
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*
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* A function that translates IEEE 802.3cg-2019 45.2.7.26 "10BASE-T1 AN status"
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* register (7.527) value to the linkmode.
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*/
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static inline void mii_10base_t1_adv_mod_linkmode_t(unsigned long *adv, u16 val)
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{
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
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adv, val & MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L);
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}
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/**
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* linkmode_adv_to_mii_10base_t1_t()
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* @adv: linkmode advertisement settings
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*
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* A function that translates the linkmode to IEEE 802.3cg-2019 45.2.7.25
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* "10BASE-T1 AN control" register (7.526) value.
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*/
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static inline u32 linkmode_adv_to_mii_10base_t1_t(unsigned long *adv)
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{
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u32 result = 0;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, adv))
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result |= MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L;
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return result;
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}
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int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
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int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
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int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum,
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@ -1758,6 +1758,13 @@ int genphy_c45_plca_set_cfg(struct phy_device *phydev,
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const struct phy_plca_cfg *plca_cfg);
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int genphy_c45_plca_get_status(struct phy_device *phydev,
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struct phy_plca_status *plca_st);
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int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv,
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unsigned long *lp, bool *is_enabled);
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int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
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struct ethtool_eee *data);
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int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
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struct ethtool_eee *data);
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int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv);
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/* Generic C45 PHY driver */
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extern struct phy_driver genphy_c45_driver;
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@ -79,6 +79,8 @@
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#define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
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#define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */
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#define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */
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#define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */
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#define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */
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#define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */
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/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
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@ -340,6 +342,12 @@
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#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
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#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
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/* 10BASE-T1 AN control register */
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#define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 /* 10BASE-T1L EEE ability advertisement */
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/* 10BASE-T1 AN status register */
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#define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */
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/* BASE-T1 PMA/PMD control register */
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#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */
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