Merge branch 'for-v5.17/dt-usi' into next/dt64
This commit is contained in:
Krzysztof Kozlowski
commit
0257bc5cce
159
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
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159
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung's Exynos USI (Universal Serial Interface) binding
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maintainers:
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- Sam Protsenko <semen.protsenko@linaro.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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description: |
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USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
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USI shares almost all internal circuits within each protocol, so only one
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protocol can be chosen at a time. USI is modeled as a node with zero or more
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child nodes, each representing a serial sub-node device. The mode setting
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selects which particular function will be used.
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Refer to next bindings documentation for information on protocol subnodes that
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can exist under USI node:
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[1] Documentation/devicetree/bindings/serial/samsung_uart.yaml
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[2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
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[3] Documentation/devicetree/bindings/spi/spi-samsung.txt
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properties:
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$nodename:
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pattern: "^usi@[0-9a-f]+$"
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compatible:
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enum:
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- samsung,exynos850-usi # for USIv2 (Exynos850, ExynosAutoV9)
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reg: true
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clocks: true
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clock-names: true
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ranges: true
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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samsung,sysreg:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Should be phandle/offset pair. The phandle to System Register syscon node
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(for the same domain where this USI controller resides) and the offset
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of SW_CONF register for this USI controller.
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samsung,mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Selects USI function (which serial protocol to use). Refer to
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<include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
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samsung,clkreq-on:
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type: boolean
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description:
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Enable this property if underlying protocol requires the clock to be
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continuously provided without automatic gating. As suggested by SoC
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manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
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multi-master mode. Usually this property is needed if USI mode is set
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to "UART".
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This property is optional.
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patternProperties:
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# All other properties should be child nodes
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"^(serial|spi|i2c)@[0-9a-f]+$":
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type: object
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description: Child node describing underlying USI serial protocol
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required:
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- compatible
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- ranges
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- "#address-cells"
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- "#size-cells"
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- samsung,sysreg
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- samsung,mode
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if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos850-usi
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then:
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properties:
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Bus (APB) clock
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- description: Operating clock for UART/SPI/I2C protocol
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clock-names:
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items:
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- const: pclk
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- const: ipclk
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required:
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- reg
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- clocks
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- clock-names
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else:
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properties:
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reg: false
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clocks: false
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clock-names: false
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samsung,clkreq-on: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/samsung,exynos-usi.h>
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usi0: usi@138200c0 {
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compatible = "samsung,exynos850-usi";
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reg = <0x138200c0 0x20>;
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samsung,sysreg = <&sysreg_peri 0x1010>;
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samsung,mode = <USI_V2_UART>;
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samsung,clkreq-on; /* needed for UART mode */
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&cmu_peri 32>, <&cmu_peri 31>;
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clock-names = "pclk", "ipclk";
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serial_0: serial@13820000 {
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compatible = "samsung,exynos850-uart";
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reg = <0x13820000 0xc0>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu_peri 32>, <&cmu_peri 31>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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hsi2c_0: i2c@13820000 {
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compatible = "samsung,exynosautov9-hsi2c";
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reg = <0x13820000 0xc0>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cmu_peri 31>, <&cmu_peri 32>;
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clock-names = "hsi2c", "hsi2c_pclk";
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status = "disabled";
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};
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};
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@ -54,3 +54,7 @@
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vcc-supply = <&ufs_0_fixed_vcc_reg>;
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vcc-fixed-regulator;
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};
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&usi_0 {
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status = "okay";
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};
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@ -7,6 +7,7 @@
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/samsung,exynos-usi.h>
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/ {
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compatible = "samsung,exynosautov9";
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@ -256,16 +257,35 @@
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reg = <0x17c20000 0x1000>;
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};
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/* USI: UART */
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serial_0: uart@10300000 {
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compatible = "samsung,exynos850-uart";
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reg = <0x10300000 0x100>;
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interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_bus_dual>;
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syscon_peric0: syscon@10220000 {
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compatible = "samsung,exynosautov9-sysreg", "syscon";
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reg = <0x10220000 0x2000>;
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};
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usi_0: usi@103000c0 {
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compatible = "samsung,exynos850-usi";
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reg = <0x103000c0 0x20>;
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samsung,sysreg = <&syscon_peric0 0x1000>;
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samsung,mode = <USI_V2_UART>;
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samsung,clkreq-on; /* needed for UART mode */
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&uart_clock>, <&uart_clock>;
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clock-names = "uart", "clk_uart_baud0";
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clock-names = "pclk", "ipclk";
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status = "disabled";
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/* USI: UART */
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serial_0: serial@10300000 {
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compatible = "samsung,exynos850-uart";
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reg = <0x10300000 0xc0>;
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interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_bus_dual>;
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clocks = <&uart_clock>, <&uart_clock>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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};
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ufs_0_phy: ufs0-phy@17e04000 {
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17
include/dt-bindings/soc/samsung,exynos-usi.h
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17
include/dt-bindings/soc/samsung,exynos-usi.h
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021 Linaro Ltd.
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* Author: Sam Protsenko <semen.protsenko@linaro.org>
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*
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* Device Tree bindings for Samsung Exynos USI (Universal Serial Interface).
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*/
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#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
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#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
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#define USI_V2_NONE 0
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#define USI_V2_UART 1
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#define USI_V2_SPI 2
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#define USI_V2_I2C 3
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#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */
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