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arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy"

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Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy' as discussed in [1].
Re-name subnodes of serdes in J721E to 'phy'.

[1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus

Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances")
Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603143427.28735-5-kishon@ti.com
This commit is contained in:
Kishon Vijay Abraham I 2021-06-03 20:04:27 +05:30 committed by Nishanth Menon
parent f2a7657ad7
commit 02b4d91861
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
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@ -359,7 +359,7 @@
};
&serdes3 {
serdes3_usb_link: link@0 {
serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@ -674,7 +674,7 @@
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz0_pll1_refclk>;
serdes0_pcie_link: link@0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@ -687,7 +687,7 @@
assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz1_pll1_refclk>;
serdes1_pcie_link: link@0 {
serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@ -700,7 +700,7 @@
assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz2_pll1_refclk>;
serdes2_pcie_link: link@0 {
serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;