iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/amd/display: Allow subvp on vactive pipes that are 2560x1440@60

Browse Source 
commit 2ebd103620 upstream.

Enable subvp on specifically 1440p@60hz displays even though it can
switch in vactive.

Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alvin Lee
2022-12-14 10:12:55 -05:00
committed by Greg Kroah-Hartman
parent 00e81f191b
commit 02c8fa11f5
2 changed files with 32 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
View File

@ -142,6 +142,8 @@ void dcn32_restore_mall_state(struct dc *dc,
struct dc_state *context, struct dc_state *context,
struct mall_temp_config *temp_config); struct mall_temp_config *temp_config);
bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);
/* definitions for run time init of reg offsets */ /* definitions for run time init of reg offsets */
/* CLK SRC */ /* CLK SRC */

31
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@ -676,7 +676,9 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
*/ */
if (pipe->plane_state && !pipe->top_pipe && if (pipe->plane_state && !pipe->top_pipe &&
pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface && pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&
vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) { (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||
(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
dcn32_allow_subvp_with_active_margin(pipe)))) {
while (pipe) { while (pipe) {
num_pipes++; num_pipes++;
pipe = pipe->bottom_pipe; pipe = pipe->bottom_pipe;
@ -2558,3 +2560,30 @@ void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
} }
bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
{
bool allow = false;
uint32_t refresh_rate = 0;
/* Allow subvp on displays that have active margin for 2560x1440@60hz displays
* only for now. There must be no scaling as well.
*
* For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs
* for p-state switching.
*/
if (pipe->stream && pipe->plane_state) {
refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
if (pipe->stream->timing.v_addressable == 1440 &&
pipe->stream->timing.h_addressable == 2560 &&
refresh_rate >= 55 && refresh_rate <= 65 &&
pipe->plane_state->src_rect.height == 1440 &&
pipe->plane_state->src_rect.width == 2560 &&
pipe->plane_state->dst_rect.height == 1440 &&
pipe->plane_state->dst_rect.width == 2560)
allow = true;
}
return allow;
}