iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: meson: make pll rst bit as optional

Browse Source 
Compared with the previous SoCs, self-adaption current module
is newly added for A1, and there is no reset parameter except the
fixed pll. Since we use clk-pll generic driver for A1 pll
implementation, rst bit should be optional to support new behavior.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230523135351.19133-2-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Dmitry Rokosov 2023-05-23 16:53:46 +03:00 committed by Jerome Brunet
parent 98872da6c6
commit 02f1e17c41
1 changed files with 17 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/clk/meson/clk-pll.c
View File

@ -295,10 +295,14 @@ static int meson_clk_pll_init(struct clk_hw *hw)
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
if (pll->init_count) { if (pll->init_count) {
meson_parm_write(clk->map, &pll->rst, 1); if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
regmap_multi_reg_write(clk->map, pll->init_regs, regmap_multi_reg_write(clk->map, pll->init_regs,
pll->init_count); pll->init_count);
meson_parm_write(clk->map, &pll->rst, 0);
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 0);
} }
return 0; return 0;
@ -309,8 +313,11 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
struct clk_regmap *clk = to_clk_regmap(hw); struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
if (meson_parm_read(clk->map, &pll->rst) || if (MESON_PARM_APPLICABLE(&pll->rst) &&
!meson_parm_read(clk->map, &pll->en) || meson_parm_read(clk->map, &pll->rst))
return 0;
if (!meson_parm_read(clk->map, &pll->en) ||
!meson_parm_read(clk->map, &pll->l)) !meson_parm_read(clk->map, &pll->l))
return 0; return 0;
@ -341,13 +348,15 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
return 0; return 0;
/* Make sure the pll is in reset */ /* Make sure the pll is in reset */
meson_parm_write(clk->map, &pll->rst, 1); if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
/* Enable the pll */ /* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1); meson_parm_write(clk->map, &pll->en, 1);
/* Take the pll out reset */ /* Take the pll out reset */
meson_parm_write(clk->map, &pll->rst, 0); if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 0);
if (meson_clk_pll_wait_lock(hw)) if (meson_clk_pll_wait_lock(hw))
return -EIO; return -EIO;
@ -361,7 +370,8 @@ static void meson_clk_pll_disable(struct clk_hw *hw)
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
/* Put the pll is in reset */ /* Put the pll is in reset */
meson_parm_write(clk->map, &pll->rst, 1); if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
/* Disable the pll */ /* Disable the pll */
meson_parm_write(clk->map, &pll->en, 0); meson_parm_write(clk->map, &pll->en, 0);