Timer changes to make it easier to support various SoCs
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPqwArAAoJEBvUPslcq6Vz0KMP+wWpRkFC+Retu1O1Lxy00Ea4 Zjg5wVfYGLuDAJf3i0xFKcDZA8AfDJws/kHi4sC0cbP296AfHqz7I25gKZqPoXf4 Y6iDRU/qLlO8djhJh7i+OP7/A4IlgMtOlMWJEZXrmhvuHRI5VusfpU/2p802yvFR xn3oWJrQ1WtE+vvNo9sK67HXLogt+49r83XGWNY66WGePKTpBf/LD+wN7zsCVaW2 xK6vqg6Z/jq8naS6WN9+zdhqgB8huULM9RX/FcOmV8hgm9oSJrqzxHIB9jyVvjXQ OMTz7WjHlakkneYBWxEGCsF8I4w5PJIXOav1OACvrsERKZpPJ0AmvYW05ZusJwLC XWuYER9v+IJG1zzym7SBa/jIkGWrCKrQKxERvi8MD9NUl2y33flGzS89Hvm9Zjap TO5U2yXIADqL83zHhtkgmWT6isHnFbQcwbc2Nz+oh/0Tnm2vrwRf88jxeFVX0k7D l9A+XgPpUeoVEdyFtb1Gt++xojuwgEjZWKHuMfS+fJrj3WwolC2MLAVW6pDsTTQd AERUuOHMgzODQ2Jx1rnljTAh57+3gVkw2iICtrWzecbbqHb6bOiB/sRN1KK+oQKh CDiH2TzibDL1T+WDLFHBJTx0eTbRiQjViYaYtgM28k3r+wlNNRbf7WTU8PjA7AZp rd/0s6+c+/kI4BcRVVF/ =ALlA -----END PGP SIGNATURE----- Merge tag 'omap-cleanup-timer-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup2 Timer changes to make it easier to support various SoCs By Vaibhav Hiremath via Tony Lindgren * tag 'omap-cleanup-timer-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP: Make OMAP clocksource source selection using kernel param ARM: OMAP2+: Replace space with underscore in the name field of system timers ARM: OMAP1: Add checks for possible error condition in timer_init
This commit is contained in:
Olof Johansson
commit
030caf3f22
@ -57,7 +57,14 @@ void omap1_init_irq(void);
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void omap1_restart(char, const char *);
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extern struct sys_timer omap1_timer;
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extern bool omap_32k_timer_init(void);
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#ifdef CONFIG_OMAP_32K_TIMER
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extern int omap_32k_timer_init(void);
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#else
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static inline int __init omap_32k_timer_init(void)
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{
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return -ENODEV;
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}
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#endif
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extern void __init omap_init_consistent_dma_size(void);
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#endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
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@ -232,20 +232,6 @@ static inline void omap_mpu_timer_init(void)
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}
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#endif /* CONFIG_OMAP_MPU_TIMER */
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static inline int omap_32k_timer_usable(void)
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{
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int res = false;
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if (cpu_is_omap730() || cpu_is_omap15xx())
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return res;
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#ifdef CONFIG_OMAP_32K_TIMER
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res = omap_32k_timer_init();
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#endif
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return res;
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}
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/*
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* ---------------------------------------------------------------------------
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* Timer initialization
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@ -253,7 +239,7 @@ static inline int omap_32k_timer_usable(void)
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*/
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static void __init omap1_timer_init(void)
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{
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if (!omap_32k_timer_usable())
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if (omap_32k_timer_init() != 0)
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omap_mpu_timer_init();
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}
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@ -71,6 +71,7 @@
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/* 16xx specific defines */
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#define OMAP1_32K_TIMER_BASE 0xfffb9000
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#define OMAP1_32KSYNC_TIMER_BASE 0xfffbc400
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#define OMAP1_32K_TIMER_CR 0x08
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#define OMAP1_32K_TIMER_TVR 0x00
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#define OMAP1_32K_TIMER_TCR 0x04
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@ -182,10 +183,29 @@ static __init void omap_init_32k_timer(void)
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* Timer initialization
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* ---------------------------------------------------------------------------
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*/
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bool __init omap_32k_timer_init(void)
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int __init omap_32k_timer_init(void)
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{
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omap_init_clocksource_32k();
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omap_init_32k_timer();
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int ret = -ENODEV;
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return true;
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if (cpu_is_omap16xx()) {
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void __iomem *base;
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struct clk *sync32k_ick;
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base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K);
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if (!base) {
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pr_err("32k_counter: failed to map base addr\n");
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return -ENODEV;
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}
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sync32k_ick = clk_get(NULL, "omap_32ksync_ick");
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if (!IS_ERR(sync32k_ick))
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clk_enable(sync32k_ick);
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ret = omap_init_clocksource_32k(base);
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}
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if (!ret)
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omap_init_32k_timer();
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return ret;
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}
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@ -90,7 +90,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
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}
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static struct irqaction omap2_gp_timer_irq = {
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.name = "gp timer",
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.name = "gp_timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = omap2_gp_timer_interrupt,
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};
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@ -132,7 +132,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
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}
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static struct clock_event_device clockevent_gpt = {
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.name = "gp timer",
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.name = "gp_timer",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_next_event = omap2_gp_timer_set_next_event,
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@ -236,22 +236,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
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}
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/* Clocksource code */
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#ifdef CONFIG_OMAP_32K_TIMER
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/*
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* When 32k-timer is enabled, don't use GPTimer for clocksource
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* instead, just leave default clocksource which uses the 32k
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* sync counter. See clocksource setup in plat-omap/counter_32k.c
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*/
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static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
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{
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omap_init_clocksource_32k();
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}
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#else
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static struct omap_dm_timer clksrc;
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static bool use_gptimer_clksrc;
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/*
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* clocksource
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@ -262,7 +248,7 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs)
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}
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static struct clocksource clocksource_gpt = {
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.name = "gp timer",
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.name = "gp_timer",
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.rating = 300,
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.read = clocksource_read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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@ -278,7 +264,46 @@ static u32 notrace dmtimer_read_sched_clock(void)
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}
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/* Setup free-running counter for clocksource */
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static void __init omap2_gp_clocksource_init(int gptimer_id,
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static int __init omap2_sync32k_clocksource_init(void)
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{
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int ret;
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struct omap_hwmod *oh;
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void __iomem *vbase;
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const char *oh_name = "counter_32k";
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/*
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* First check hwmod data is available for sync32k counter
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*/
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oh = omap_hwmod_lookup(oh_name);
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if (!oh || oh->slaves_cnt == 0)
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return -ENODEV;
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omap_hwmod_setup_one(oh_name);
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vbase = omap_hwmod_get_mpu_rt_va(oh);
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if (!vbase) {
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pr_warn("%s: failed to get counter_32k resource\n", __func__);
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return -ENXIO;
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}
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ret = omap_hwmod_enable(oh);
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if (ret) {
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pr_warn("%s: failed to enable counter_32k module (%d)\n",
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__func__, ret);
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return ret;
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}
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ret = omap_init_clocksource_32k(vbase);
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if (ret) {
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pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
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__func__, ret);
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omap_hwmod_idle(oh);
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}
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return ret;
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}
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static void __init omap2_gptimer_clocksource_init(int gptimer_id,
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const char *fck_source)
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{
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int res;
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@ -286,9 +311,6 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
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res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
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BUG_ON(res);
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pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
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gptimer_id, clksrc.rate);
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__omap_dm_timer_load_start(&clksrc,
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OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
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setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
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@ -296,15 +318,36 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
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if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
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pr_err("Could not register clocksource %s\n",
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clocksource_gpt.name);
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else
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pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
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gptimer_id, clksrc.rate);
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}
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static void __init omap2_clocksource_init(int gptimer_id,
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const char *fck_source)
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{
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/*
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* First give preference to kernel parameter configuration
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* by user (clocksource="gp_timer").
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*
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* In case of missing kernel parameter for clocksource,
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* first check for availability for 32k-sync timer, in case
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* of failure in finding 32k_counter module or registering
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* it as clocksource, execution will fallback to gp-timer.
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*/
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if (use_gptimer_clksrc == true)
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omap2_gptimer_clocksource_init(gptimer_id, fck_source);
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else if (omap2_sync32k_clocksource_init())
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/* Fall back to gp-timer code */
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omap2_gptimer_clocksource_init(gptimer_id, fck_source);
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}
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#endif
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#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
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clksrc_nr, clksrc_src) \
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static void __init omap##name##_timer_init(void) \
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{ \
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omap2_gp_clockevent_init((clkev_nr), clkev_src); \
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omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
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omap2_clocksource_init((clksrc_nr), clksrc_src); \
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}
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#define OMAP_SYS_TIMER(name) \
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@ -335,7 +378,7 @@ static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
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static void __init omap4_timer_init(void)
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{
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omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
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omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
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omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
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#ifdef CONFIG_LOCAL_TIMERS
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/* Local timers are not supprted on OMAP4430 ES1.0 */
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if (omap_rev() != OMAP4430_REV_ES1_0) {
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@ -503,3 +546,28 @@ static int __init omap2_dm_timer_init(void)
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return 0;
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}
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arch_initcall(omap2_dm_timer_init);
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/**
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* omap2_override_clocksource - clocksource override with user configuration
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*
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* Allows user to override default clocksource, using kernel parameter
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* clocksource="gp_timer" (For all OMAP2PLUS architectures)
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*
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* Note that, here we are using same standard kernel parameter "clocksource=",
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* and not introducing any OMAP specific interface.
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*/
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static int __init omap2_override_clocksource(char *str)
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{
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if (!str)
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return 0;
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/*
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* For OMAP architecture, we only have two options
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* - sync_32k (default)
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* - gp_timer (sys_clk based)
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*/
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if (!strcmp(str, "gp_timer"))
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use_gptimer_clksrc = true;
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return 0;
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}
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early_param("clocksource", omap2_override_clocksource);
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@ -27,19 +27,20 @@
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#include <plat/clock.h>
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/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
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#define OMAP2_32KSYNCNT_CR_OFF 0x10
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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static void __iomem *timer_32k_base;
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#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
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static void __iomem *sync32k_cnt_reg;
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static u32 notrace omap_32k_read_sched_clock(void)
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{
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return timer_32k_base ? __raw_readl(timer_32k_base) : 0;
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return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
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}
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/**
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@ -59,7 +60,7 @@ void read_persistent_clock(struct timespec *ts)
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struct timespec *tsp = &persistent_ts;
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last_cycles = cycles;
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cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
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cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
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delta = cycles - last_cycles;
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nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
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@ -68,54 +69,40 @@ void read_persistent_clock(struct timespec *ts)
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*ts = *tsp;
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}
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int __init omap_init_clocksource_32k(void)
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/**
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* omap_init_clocksource_32k - setup and register counter 32k as a
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* kernel clocksource
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* @pbase: base addr of counter_32k module
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* @size: size of counter_32k to map
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*
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* Returns 0 upon success or negative error code upon failure.
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*
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*/
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int __init omap_init_clocksource_32k(void __iomem *vbase)
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{
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static char err[] __initdata = KERN_ERR
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"%s: can't register clocksource!\n";
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int ret;
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if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
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u32 pbase;
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unsigned long size = SZ_4K;
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void __iomem *base;
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struct clk *sync_32k_ick;
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/*
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* 32k sync Counter register offset is at 0x10
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*/
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
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if (cpu_is_omap16xx()) {
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pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
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size = SZ_1K;
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} else if (cpu_is_omap2420())
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pbase = OMAP2420_32KSYNCT_BASE + 0x10;
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else if (cpu_is_omap2430())
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pbase = OMAP2430_32KSYNCT_BASE + 0x10;
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else if (cpu_is_omap34xx())
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pbase = OMAP3430_32KSYNCT_BASE + 0x10;
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else if (cpu_is_omap44xx())
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pbase = OMAP4430_32KSYNCT_BASE + 0x10;
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else
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return -ENODEV;
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/*
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* 120000 rough estimate from the calculations in
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* __clocksource_updatefreq_scale.
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*/
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clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
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32768, NSEC_PER_SEC, 120000);
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/* For this to work we must have a static mapping in io.c for this area */
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base = ioremap(pbase, size);
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if (!base)
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return -ENODEV;
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sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
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if (!IS_ERR(sync_32k_ick))
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clk_enable(sync_32k_ick);
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timer_32k_base = base;
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/*
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* 120000 rough estimate from the calculations in
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* __clocksource_updatefreq_scale.
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*/
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clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
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32768, NSEC_PER_SEC, 120000);
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if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
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clocksource_mmio_readl_up))
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printk(err, "32k_counter");
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setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
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ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
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250, 32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("32k_counter: can't register clocksource\n");
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return ret;
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}
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setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
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pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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return 0;
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}
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@ -30,7 +30,7 @@
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#include <plat/i2c.h>
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#include <plat/omap_hwmod.h>
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extern int __init omap_init_clocksource_32k(void);
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extern int __init omap_init_clocksource_32k(void __iomem *vbase);
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extern void omap_reserve(void);
|
||||
extern int omap_dss_reset(struct omap_hwmod *);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user