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rtw-next patches for v6.11

Browse Source 
Some cleanups of rtl8xxxu and rtlwifi, and some fixes of rtw88. The major
 change is to develop WoWLAN and preparation of RTL8852BE-VT listed below:
 
 rtw89:
   - preparation of RTL8852BE-VT
     * add RF calibration code
     * move shared code with RTL8852BE to common module
   - add WoWLAN for WiFi 6 chips
   - support 36-bit PCI DMA
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Merge tag 'rtw-next-2024-07-05' of https://github.com/pkshih/rtw

rtw-next patches for v6.11

Some cleanups of rtl8xxxu and rtlwifi, and some fixes of rtw88. The major
change is to develop WoWLAN and preparation of RTL8852BE-VT listed below:

rtw89:
  - preparation of RTL8852BE-VT
    * add RF calibration code
    * move shared code with RTL8852BE to common module
  - add WoWLAN for WiFi 6 chips
  - support 36-bit PCI DMA
This commit is contained in:
Kalle Valo 2024-07-09 13:17:09 +03:00
commit 0321e45737
65 changed files with 8131 additions and 2176 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/net/wireless/realtek/rtl8xxxu/8188f.c
View File

@ -697,9 +697,14 @@ static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv)
rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
}
#define TX_POWER_INDEX_MAX 0x3F
#define TX_POWER_INDEX_DEFAULT_CCK 0x22
#define TX_POWER_INDEX_DEFAULT_HT40 0x27
static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv)
{
struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu;
int i;
if (efuse->rtl_id != cpu_to_le16(0x8129))
return -EINVAL;
@ -713,6 +718,16 @@ static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv)
efuse->tx_power_index_A.ht40_base,
sizeof(efuse->tx_power_index_A.ht40_base));
for (i = 0; i < ARRAY_SIZE(priv->cck_tx_power_index_A); i++) {
if (priv->cck_tx_power_index_A[i] > TX_POWER_INDEX_MAX)
priv->cck_tx_power_index_A[i] = TX_POWER_INDEX_DEFAULT_CCK;
}
for (i = 0; i < ARRAY_SIZE(priv->ht40_1s_tx_power_index_A); i++) {
if (priv->ht40_1s_tx_power_index_A[i] > TX_POWER_INDEX_MAX)
priv->ht40_1s_tx_power_index_A[i] = TX_POWER_INDEX_DEFAULT_HT40;
}
priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;

6
drivers/net/wireless/realtek/rtl8xxxu/core.c
View File

@ -6679,7 +6679,6 @@ static void rtl8xxxu_switch_ports(struct rtl8xxxu_priv *priv)
u8 macid[ETH_ALEN], bssid[ETH_ALEN], macid_1[ETH_ALEN], bssid_1[ETH_ALEN];
u8 msr, bcn_ctrl, bcn_ctrl_1, atimwnd[2], atimwnd_1[2];
struct rtl8xxxu_vif *rtlvif;
struct ieee80211_vif *vif;
u8 tsftr[8], tsftr_1[8];
int i;
@ -6744,10 +6743,7 @@ static void rtl8xxxu_switch_ports(struct rtl8xxxu_priv *priv)
/* write bcn ctl */
rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1);
rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl);
vif = priv->vifs[0];
priv->vifs[0] = priv->vifs[1];
priv->vifs[1] = vif;
swap(priv->vifs[0], priv->vifs[1]);
/* priv->vifs[0] is NULL here, based on how this function is currently
* called from rtl8xxxu_add_interface().

2
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c
View File

@ -27,7 +27,7 @@ static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* set default to RTL8192CE:3 RTL8192E:2
*/
rtlpci->const_pci_aspm = 3;

2
drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c
View File

@ -31,7 +31,7 @@ static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw)
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* set default to RTL8192CE:3 RTL8192E:2
* */
rtlpci->const_pci_aspm = 3;

2
drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c
View File

@ -32,7 +32,7 @@ static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* set default to RTL8192CE:3 RTL8192E:2
* */
rtlpci->const_pci_aspm = 3;

2
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c
View File

@ -31,7 +31,7 @@ static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* set default to RTL8192CE:3 RTL8192E:2
*/
rtlpci->const_pci_aspm = 3;

2
drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
View File

@ -27,7 +27,7 @@ static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* set default to RTL8192CE:3 RTL8192E:2
* */
rtlpci->const_pci_aspm = 2;

2
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c
View File

@ -33,7 +33,7 @@ static void rtl8723e_init_aspm_vars(struct ieee80211_hw *hw)
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* set default to RTL8192CE:3 RTL8192E:2
*/
rtlpci->const_pci_aspm = 3;

2
drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c
View File

@ -32,7 +32,7 @@ static void rtl8723be_init_aspm_vars(struct ieee80211_hw *hw)
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* set default to RTL8192CE:3 RTL8192E:2
*/
rtlpci->const_pci_aspm = 3;

2
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c
View File

@ -30,7 +30,7 @@ static void rtl8821ae_init_aspm_vars(struct ieee80211_hw *hw)
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* set default to RTL8192CE:3 RTL8192E:2
*/
rtlpci->const_pci_aspm = 3;

9
drivers/net/wireless/realtek/rtw88/mac.c
View File

@ -1201,6 +1201,15 @@ static int __priority_queue_cfg(struct rtw_dev *rtwdev,
rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
if (rtwdev->hci.type == RTW_HCI_TYPE_USB) {
rtw_write8_mask(rtwdev, REG_AUTO_LLT_V1, BIT_MASK_BLK_DESC_NUM,
chip->usb_tx_agg_desc_num);
rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num);
rtw_write8_set(rtwdev, REG_TXDMA_OFFSET_CHK + 1, BIT(1));
}
rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))

2
drivers/net/wireless/realtek/rtw88/main.h
View File

@ -1197,6 +1197,8 @@ struct rtw_chip_info {
u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
const struct rtw_fwcd_segs *fwcd_segs;
u8 usb_tx_agg_desc_num;
u8 default_1ss_tx_path;
bool path_div_supported;

1
drivers/net/wireless/realtek/rtw88/reg.h
View File

@ -270,6 +270,7 @@
#define BIT_MASK_BCN_HEAD_1_V1 0xfff
#define REG_AUTO_LLT_V1 0x0208
#define BIT_AUTO_INIT_LLT_V1 BIT(0)
#define BIT_MASK_BLK_DESC_NUM GENMASK(7, 4)
#define REG_DWBCN0_CTRL 0x0208
#define BIT_BCN_VALID BIT(16)
#define REG_TXDMA_OFFSET_CHK 0x020C

1
drivers/net/wireless/realtek/rtw88/rtw8703b.c
View File

@ -2013,6 +2013,7 @@ const struct rtw_chip_info rtw8703b_hw_spec = {
.tx_stbc = false,
.max_power_index = 0x3f,
.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
.usb_tx_agg_desc_num = 1, /* Not sure if this chip has USB interface */
.path_div_supported = false,
.ht_supported = true,

1
drivers/net/wireless/realtek/rtw88/rtw8723d.c
View File

@ -2171,6 +2171,7 @@ const struct rtw_chip_info rtw8723d_hw_spec = {
.band = RTW_BAND_2G,
.page_size = TX_PAGE_SIZE,
.dig_min = 0x20,
.usb_tx_agg_desc_num = 1,
.ht_supported = true,
.vht_supported = false,
.lps_deep_mode_supported = 0,

1
drivers/net/wireless/realtek/rtw88/rtw8821c.c
View File

@ -2008,6 +2008,7 @@ const struct rtw_chip_info rtw8821c_hw_spec = {
.band = RTW_BAND_2G | RTW_BAND_5G,
.page_size = TX_PAGE_SIZE,
.dig_min = 0x1c,
.usb_tx_agg_desc_num = 3,
.ht_supported = true,
.vht_supported = true,
.lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),

1
drivers/net/wireless/realtek/rtw88/rtw8822b.c
View File

@ -2548,6 +2548,7 @@ const struct rtw_chip_info rtw8822b_hw_spec = {
.band = RTW_BAND_2G | RTW_BAND_5G,
.page_size = TX_PAGE_SIZE,
.dig_min = 0x1c,
.usb_tx_agg_desc_num = 3,
.ht_supported = true,
.vht_supported = true,
.lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),

1
drivers/net/wireless/realtek/rtw88/rtw8822c.c
View File

@ -5366,6 +5366,7 @@ const struct rtw_chip_info rtw8822c_hw_spec = {
.band = RTW_BAND_2G | RTW_BAND_5G,
.page_size = TX_PAGE_SIZE,
.dig_min = 0x20,
.usb_tx_agg_desc_num = 3,
.default_1ss_tx_path = BB_PATH_A,
.path_div_supported = true,
.ht_supported = true,

17
drivers/net/wireless/realtek/rtw88/usb.c
View File

@ -379,7 +379,9 @@ static bool rtw_usb_tx_agg_skb(struct rtw_usb *rtwusb, struct sk_buff_head *list
skb_iter = skb_peek(list);
if (skb_iter && skb_iter->len + skb_head->len <= RTW_USB_MAX_XMITBUF_SZ)
if (skb_iter &&
skb_iter->len + skb_head->len <= RTW_USB_MAX_XMITBUF_SZ &&
agg_num < rtwdev->chip->usb_tx_agg_desc_num)
__skb_unlink(skb_iter, list);
else
skb_iter = NULL;
@ -740,7 +742,6 @@ static struct rtw_hci_ops rtw_usb_ops = {
static int rtw_usb_init_rx(struct rtw_dev *rtwdev)
{
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
int i;
rtwusb->rxwq = create_singlethread_workqueue("rtw88_usb: rx wq");
if (!rtwusb->rxwq) {
@ -752,13 +753,19 @@ static int rtw_usb_init_rx(struct rtw_dev *rtwdev)
INIT_WORK(&rtwusb->rx_work, rtw_usb_rx_handler);
return 0;
}
static void rtw_usb_setup_rx(struct rtw_dev *rtwdev)
{
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
int i;
for (i = 0; i < RTW_USB_RXCB_NUM; i++) {
struct rx_usb_ctrl_block *rxcb = &rtwusb->rx_cb[i];
rtw_usb_rx_resubmit(rtwusb, rxcb);
}
return 0;
}
static void rtw_usb_deinit_rx(struct rtw_dev *rtwdev)
@ -895,6 +902,8 @@ int rtw_usb_probe(struct usb_interface *intf, const struct usb_device_id *id)
goto err_destroy_rxwq;
}
rtw_usb_setup_rx(rtwdev);
return 0;
err_destroy_rxwq:

4
drivers/net/wireless/realtek/rtw89/Kconfig
View File

@ -22,6 +22,9 @@ config RTW89_8851B
config RTW89_8852A
tristate
config RTW89_8852B_COMMON
tristate
config RTW89_8852B
tristate
@ -59,6 +62,7 @@ config RTW89_8852BE
select RTW89_CORE
select RTW89_PCI
select RTW89_8852B
select RTW89_8852B_COMMON
help
Select this option will enable support for 8852BE chipset

6
drivers/net/wireless/realtek/rtw89/Makefile
View File

@ -17,7 +17,8 @@ rtw89_core-y += core.o \
ps.o \
chan.o \
ser.o \
acpi.o
acpi.o \
util.o
rtw89_core-$(CONFIG_PM) += wow.o
@ -39,6 +40,9 @@ rtw89_8852a-objs := rtw8852a.o \
obj-$(CONFIG_RTW89_8852AE) += rtw89_8852ae.o
rtw89_8852ae-objs := rtw8852ae.o
obj-$(CONFIG_RTW89_8852B_COMMON) += rtw89_8852b_common.o
rtw89_8852b_common-objs := rtw8852b_common.o
obj-$(CONFIG_RTW89_8852B) += rtw89_8852b.o
rtw89_8852b-objs := rtw8852b.o \
rtw8852b_table.o \

1
drivers/net/wireless/realtek/rtw89/cam.c
View File

@ -523,6 +523,7 @@ static u8 rtw89_get_addr_cam_entry_size(struct rtw89_dev *rtwdev)
case RTL8852A:
case RTL8852B:
case RTL8851B:
case RTL8852BT:
return ADDR_CAM_ENT_SIZE;
default:
return ADDR_CAM_ENT_SHORT_SIZE;

22
drivers/net/wireless/realtek/rtw89/chan.c
View File

@ -141,6 +141,28 @@ bool rtw89_assign_entity_chan(struct rtw89_dev *rtwdev,
return band_changed;
}
int rtw89_iterate_entity_chan(struct rtw89_dev *rtwdev,
int (*iterator)(const struct rtw89_chan *chan,
void *data),
void *data)
{
struct rtw89_hal *hal = &rtwdev->hal;
const struct rtw89_chan *chan;
int ret;
u8 idx;
lockdep_assert_held(&rtwdev->mutex);
for_each_set_bit(idx, hal->entity_map, NUM_OF_RTW89_SUB_ENTITY) {
chan = rtw89_chan_get(rtwdev, idx);
ret = iterator(chan, data);
if (ret)
return ret;
}
return 0;
}
static void __rtw89_config_entity_chandef(struct rtw89_dev *rtwdev,
enum rtw89_sub_entity_idx idx,
const struct cfg80211_chan_def *chandef,

4
drivers/net/wireless/realtek/rtw89/chan.h
View File

@ -78,6 +78,10 @@ void rtw89_chan_create(struct rtw89_chan *chan, u8 center_chan, u8 primary_chan,
bool rtw89_assign_entity_chan(struct rtw89_dev *rtwdev,
enum rtw89_sub_entity_idx idx,
const struct rtw89_chan *new);
int rtw89_iterate_entity_chan(struct rtw89_dev *rtwdev,
int (*iterator)(const struct rtw89_chan *chan,
void *data),
void *data);
void rtw89_config_entity_chandef(struct rtw89_dev *rtwdev,
enum rtw89_sub_entity_idx idx,
const struct cfg80211_chan_def *chandef);

29
drivers/net/wireless/realtek/rtw89/coex.c
View File

@ -91,7 +91,7 @@ static const struct rtw89_btc_fbtc_slot s_def[] = {
[CXST_BLK] = __DEF_FBTC_SLOT(500, 0x55555555, SLOT_MIX),
[CXST_E2G] = __DEF_FBTC_SLOT(0, 0xea5a5a5a, SLOT_MIX),
[CXST_E5G] = __DEF_FBTC_SLOT(0, 0xffffffff, SLOT_ISO),
[CXST_EBT] = __DEF_FBTC_SLOT(0, 0xe5555555, SLOT_MIX),
[CXST_EBT] = __DEF_FBTC_SLOT(5, 0xe5555555, SLOT_MIX),
[CXST_ENULL] = __DEF_FBTC_SLOT(0, 0xaaaaaaaa, SLOT_ISO),
[CXST_WLK] = __DEF_FBTC_SLOT(250, 0xea5a5a5a, SLOT_MIX),
[CXST_W1FDD] = __DEF_FBTC_SLOT(50, 0xffffffff, SLOT_ISO),
@ -228,6 +228,7 @@ static u32 chip_id_to_bt_rom_code_id(u32 id)
case RTL8852A:
case RTL8852B:
case RTL8852C:
case RTL8852BT:
return 0x8852;
case RTL8851B:
return 0x8851;
@ -3616,6 +3617,7 @@ void rtw89_btc_set_policy_v1(struct rtw89_dev *rtwdev, u16 policy_type)
struct rtw89_btc_wl_info *wl = &btc->cx.wl;
u8 type, null_role;
u32 tbl_w1, tbl_b1, tbl_b4;
u16 dur_2;
type = FIELD_GET(BTC_CXP_MASK, policy_type);
@ -3726,7 +3728,21 @@ void rtw89_btc_set_policy_v1(struct rtw89_dev *rtwdev, u16 policy_type)
if (hid->exist || hfp->exist)
tbl_w1 = cxtbl[16];
dur_2 = dm->e2g_slot_limit;
switch (policy_type) {
case BTC_CXP_OFFE_2GBWISOB: /* for normal-case */
_slot_set(btc, CXST_E2G, 0, tbl_w1, SLOT_ISO);
_slot_set_le(btc, CXST_EBT, s_def[CXST_EBT].dur,
s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype);
_slot_set_dur(btc, CXST_EBT, dur_2);
break;
case BTC_CXP_OFFE_2GISOB: /* for bt no-link */
_slot_set(btc, CXST_E2G, 0, cxtbl[1], SLOT_ISO);
_slot_set_le(btc, CXST_EBT, s_def[CXST_EBT].dur,
s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype);
_slot_set_dur(btc, CXST_EBT, dur_2);
break;
case BTC_CXP_OFFE_DEF:
_slot_set_le(btc, CXST_E2G, s_def[CXST_E2G].dur,
s_def[CXST_E2G].cxtbl, s_def[CXST_E2G].cxtype);
@ -3746,6 +3762,15 @@ void rtw89_btc_set_policy_v1(struct rtw89_dev *rtwdev, u16 policy_type)
_slot_set_le(btc, CXST_ENULL, s_def[CXST_ENULL].dur,
s_def[CXST_ENULL].cxtbl, s_def[CXST_ENULL].cxtype);
break;
case BTC_CXP_OFFE_2GBWMIXB:
_slot_set(btc, CXST_E2G, 0, 0x55555555, SLOT_MIX);
_slot_set_le(btc, CXST_EBT, s_def[CXST_EBT].dur,
cpu_to_le32(0x55555555), s_def[CXST_EBT].cxtype);
break;
case BTC_CXP_OFFE_WL: /* for 4-way */
_slot_set(btc, CXST_E2G, 0, cxtbl[1], SLOT_MIX);
_slot_set(btc, CXST_EBT, 0, cxtbl[1], SLOT_MIX);
break;
default:
break;
}
@ -9514,7 +9539,7 @@ static void _get_gnt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_coex_gnt *gnt
u32 val, status;
if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
chip->chip_id == RTL8851B) {
chip->chip_id == RTL8851B || chip->chip_id == RTL8852BT) {
rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val);
rtw89_mac_read_lte(rtwdev, R_AX_GNT_VAL, &status);

21
drivers/net/wireless/realtek/rtw89/core.c
View File

@ -1921,7 +1921,8 @@ static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
return;
if (ieee80211_is_beacon(hdr->frame_control)) {
if (vif->type == NL80211_IFTYPE_STATION) {
if (vif->type == NL80211_IFTYPE_STATION &&
!test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
rtw89_vif_sync_bcn_tsf(rtwvif, hdr, skb->len);
rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
}
@ -3375,8 +3376,12 @@ int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
/* for station mode, assign the mac_id from itself */
rtwsta->mac_id = rtwvif->mac_id;
/* must do rtw89_reg_6ghz_power_recalc() before rfk channel */
rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, true);
/* must do rtw89_reg_6ghz_recalc() before rfk channel */
ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif, true);
if (ret)
return ret;
rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
BTC_ROLE_MSTS_STA_CONN_START);
rtw89_chip_rfk_channel(rtwdev);
@ -3564,7 +3569,7 @@ int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
int ret;
if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, false);
rtw89_reg_6ghz_recalc(rtwdev, rtwvif, false);
rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
BTC_ROLE_MSTS_STA_DIS_CONN);
} else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
@ -4054,15 +4059,15 @@ void rtw89_core_update_beacon_work(struct work_struct *work)
int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
{
struct completion *cmpl = &wait->completion;
unsigned long timeout;
unsigned long time_left;
unsigned int cur;
cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
if (cur != RTW89_WAIT_COND_IDLE)
return -EBUSY;
timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
if (timeout == 0) {
time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
if (time_left == 0) {
atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
return -ETIMEDOUT;
}
@ -4382,7 +4387,7 @@ static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
rtwdev->hal.cv = cv;
if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) {
if (rtw89_is_rtl885xb(rtwdev)) {
ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
if (ret)
return;

38
drivers/net/wireless/realtek/rtw89/core.h
View File

@ -132,6 +132,7 @@ enum rtw89_hci_type {
enum rtw89_core_chip_id {
RTL8852A,
RTL8852B,
RTL8852BT,
RTL8852C,
RTL8851B,
RTL8922A,
@ -745,6 +746,14 @@ enum rtw89_reg_6ghz_power {
RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
};
#define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
/* calculate based on ieee80211 Transmit Power Envelope */
struct rtw89_reg_6ghz_tpe {
bool valid;
s8 constraint; /* unit: dBm */
};
enum rtw89_fw_pkt_ofld_type {
RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
@ -1329,6 +1338,7 @@ struct rtw89_btc_wl_smap {
u32 scan: 1;
u32 connecting: 1;
u32 roaming: 1;
u32 dbccing: 1;
u32 transacting: 1;
u32 _4way: 1;
u32 rf_off: 1;
@ -3395,6 +3405,7 @@ struct rtw89_vif {
bool chanctx_assigned; /* only valid when running with chanctx_ops */
enum rtw89_sub_entity_idx sub_entity_idx;
enum rtw89_reg_6ghz_power reg_6ghz_power;
struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
u8 mac_id;
u8 port;
@ -4235,7 +4246,7 @@ struct rtw89_chip_info {
const u32 *c2h_regs;
struct rtw89_reg_def c2h_counter_reg;
const struct rtw89_page_regs *page_regs;
u32 wow_reason_reg;
const u32 *wow_reason_reg;
bool cfo_src_fd;
bool cfo_hw_comp;
const struct rtw89_reg_def *dcfo_comp;
@ -4345,6 +4356,7 @@ enum rtw89_fw_feature {
RTW89_FW_FEATURE_NO_LPS_PG,
RTW89_FW_FEATURE_BEACON_FILTER,
RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
RTW89_FW_FEATURE_WOW_REASON_V1,
};
struct rtw89_fw_suit {
@ -4683,7 +4695,12 @@ struct rtw89_dack_info {
bool msbk_timeout[RTW89_DACK_PATH_NR];
};
#define RTW89_RFK_CHS_NR 3
enum rtw89_rfk_chs_nrs {
__RTW89_RFK_CHS_NR_V0 = 2,
__RTW89_RFK_CHS_NR_V1 = 3,
RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
};
struct rtw89_rfk_mcc_info {
u8 ch[RTW89_RFK_CHS_NR];
@ -4762,6 +4779,8 @@ struct rtw89_dpk_info {
u8 cur_idx[RTW89_DPK_RF_PATH];
u8 cur_k_set;
struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
u32 dpk_order[RTW89_DPK_RF_PATH];
};
struct rtw89_fem_info {
@ -4936,6 +4955,7 @@ struct rtw89_regd {
struct rtw89_regulatory_info {
const struct rtw89_regd *regd;
enum rtw89_reg_6ghz_power reg_6ghz_power;
struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
@ -6420,6 +6440,16 @@ static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
}
}
static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
return true;
return false;
}
int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
@ -6520,8 +6550,8 @@ void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
const u8 *mac_addr, bool hw_scan);
void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
struct ieee80211_vif *vif, bool hw_scan);
void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
struct rtw89_vif *rtwvif, bool active);
int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
bool active);
void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);

29
drivers/net/wireless/realtek/rtw89/debug.c
View File

@ -818,6 +818,28 @@ static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] =
[RTW89_CHIP_BE] = &dbgfs_txpwr_table_be,
};
static
void rtw89_debug_priv_txpwr_table_get_regd(struct seq_file *m,
struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan)
{
const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
const struct rtw89_reg_6ghz_tpe *tpe6 = &regulatory->reg_6ghz_tpe;
seq_printf(m, "[Chanctx] band %u, ch %u, bw %u\n",
chan->band_type, chan->channel, chan->band_width);
seq_puts(m, "[Regulatory] ");
__print_regd(m, rtwdev, chan);
if (chan->band_type == RTW89_BAND_6G) {
seq_printf(m, "[reg6_pwr_type] %u\n", regulatory->reg_6ghz_power);
if (tpe6->valid)
seq_printf(m, "[TPE] %d dBm\n", tpe6->constraint);
}
}
static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)
{
struct rtw89_debugfs_priv *debugfs_priv = m->private;
@ -831,8 +853,7 @@ static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)
rtw89_leave_ps_mode(rtwdev);
chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
seq_puts(m, "[Regulatory] ");
__print_regd(m, rtwdev, chan);
rtw89_debug_priv_txpwr_table_get_regd(m, rtwdev, chan);
seq_puts(m, "[SAR]\n");
rtw89_print_sar(m, rtwdev, chan->freq);
@ -2996,7 +3017,7 @@ static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel)
sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA &&
sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2)
return false;
if (rtwdev->chip->chip_id == RTL8852B &&
if (rtw89_is_rtl885xb(rtwdev) &&
sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
return false;
@ -3531,7 +3552,7 @@ static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
case RX_ENC_HE:
seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx,
status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
he_gi_str[rate->he_gi] : "N/A");
he_gi_str[status->he_gi] : "N/A");
break;
case RX_ENC_EHT:
seq_printf(m, "EHT %dSS MCS-%d GI:%s", status->nss, status->rate_idx,

114
drivers/net/wireless/realtek/rtw89/fw.c
View File

@ -13,22 +13,20 @@
#include "ps.h"
#include "reg.h"
#include "util.h"
#include "wow.h"
struct rtw89_eapol_2_of_2 {
struct ieee80211_hdr_3addr hdr;
u8 gtkbody[14];
u8 key_des_ver;
u8 rsvd[92];
} __packed __aligned(2);
} __packed;
struct rtw89_sa_query {
struct ieee80211_hdr_3addr hdr;
u8 category;
u8 action;
} __packed __aligned(2);
} __packed;
struct rtw89_arp_rsp {
struct ieee80211_hdr_3addr addr;
u8 llc_hdr[sizeof(rfc1042_header)];
__be16 llc_type;
struct arphdr arp_hdr;
@ -36,7 +34,7 @@ struct rtw89_arp_rsp {
__be32 sender_ip;
u8 target_hw[ETH_ALEN];
__be32 target_ip;
} __packed __aligned(2);
} __packed;
static const u8 mss_signature[] = {0x4D, 0x53, 0x53, 0x4B, 0x50, 0x4F, 0x4F, 0x4C};
@ -462,7 +460,7 @@ int rtw89_mfw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
const u8 *mfw = firmware->data;
u32 mfw_len = firmware->size;
const struct rtw89_mfw_hdr *mfw_hdr = (const struct rtw89_mfw_hdr *)mfw;
const struct rtw89_mfw_info *mfw_info;
const struct rtw89_mfw_info *mfw_info = NULL, *tmp;
int i;
if (mfw_hdr->sig != RTW89_MFW_SIG) {
@ -476,15 +474,27 @@ int rtw89_mfw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
}
for (i = 0; i < mfw_hdr->fw_nr; i++) {
mfw_info = &mfw_hdr->info[i];
if (mfw_info->type == type) {
if (mfw_info->cv == rtwdev->hal.cv && !mfw_info->mp)
goto found;
if (type == RTW89_FW_LOGFMT)
goto found;
tmp = &mfw_hdr->info[i];
if (tmp->type != type)
continue;
if (type == RTW89_FW_LOGFMT) {
mfw_info = tmp;
goto found;
}
/* Version order of WiFi firmware in firmware file are not in order,
* pass all firmware to find the equal or less but closest version.
*/
if (tmp->cv <= rtwdev->hal.cv && !tmp->mp) {
if (!mfw_info || mfw_info->cv < tmp->cv)
mfw_info = tmp;
}
}
if (mfw_info)
goto found;
if (!nowarn)
rtw89_err(rtwdev, "no suitable firmware found\n");
return -ENOENT;
@ -606,10 +616,16 @@ int __rtw89_fw_recognize_from_elm(struct rtw89_dev *rtwdev,
struct rtw89_hal *hal = &rtwdev->hal;
struct rtw89_fw_suit *fw_suit;
if (hal->cv != elm->u.bbmcu.cv)
/* Version of BB MCU is in decreasing order in firmware file, so take
* first equal or less version, which is equal or less but closest version.
*/
if (hal->cv < elm->u.bbmcu.cv)
return 1; /* ignore this element */
fw_suit = rtw89_fw_suit_get(rtwdev, type);
if (fw_suit->data)
return 1; /* ignore this element (a firmware is taken already) */
fw_suit->data = elm->u.bbmcu.contents;
fw_suit->size = le32_to_cpu(elm->size);
@ -659,10 +675,12 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = {
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 36, 0, SCAN_OFFLOAD),
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 40, 0, CRASH_TRIGGER),
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 56, 10, BEACON_FILTER),
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 80, 0, WOW_REASON_V1),
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 30, 0, CRASH_TRIGGER),
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 11, 0, MACID_PAUSE_SLEEP),
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 35, 0, SCAN_OFFLOAD),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 12, 0, BEACON_FILTER),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 22, 0, WOW_REASON_V1),
};
static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
@ -2179,8 +2197,10 @@ static struct sk_buff *rtw89_eapol_get(struct rtw89_dev *rtwdev,
0x8E, 0x01, 0x03, 0x00, 0x5F, 0x02, 0x03};
struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
u8 sec_hdr_len = rtw89_wow_get_sec_hdr_len(rtwdev);
struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
struct rtw89_eapol_2_of_2 *eapol_pkt;
struct ieee80211_hdr_3addr *hdr;
struct sk_buff *skb;
u8 key_des_ver;
@ -2193,17 +2213,21 @@ static struct sk_buff *rtw89_eapol_get(struct rtw89_dev *rtwdev,
else
key_des_ver = 0;
skb = dev_alloc_skb(sizeof(*eapol_pkt));
skb = dev_alloc_skb(sizeof(*hdr) + sec_hdr_len + sizeof(*eapol_pkt));
if (!skb)
return NULL;
hdr = skb_put_zero(skb, sizeof(*hdr));
hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA |
IEEE80211_FCTL_TODS |
IEEE80211_FCTL_PROTECTED);
ether_addr_copy(hdr->addr1, bss_conf->bssid);
ether_addr_copy(hdr->addr2, vif->addr);
ether_addr_copy(hdr->addr3, bss_conf->bssid);
skb_put_zero(skb, sec_hdr_len);
eapol_pkt = skb_put_zero(skb, sizeof(*eapol_pkt));
eapol_pkt->hdr.frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA |
IEEE80211_FCTL_TODS |
IEEE80211_FCTL_PROTECTED);
ether_addr_copy(eapol_pkt->hdr.addr1, bss_conf->bssid);
ether_addr_copy(eapol_pkt->hdr.addr2, vif->addr);
ether_addr_copy(eapol_pkt->hdr.addr3, bss_conf->bssid);
memcpy(eapol_pkt->gtkbody, gtkbody, sizeof(gtkbody));
eapol_pkt->key_des_ver = key_des_ver;
@ -2215,20 +2239,26 @@ static struct sk_buff *rtw89_sa_query_get(struct rtw89_dev *rtwdev,
{
struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
u8 sec_hdr_len = rtw89_wow_get_sec_hdr_len(rtwdev);
struct ieee80211_hdr_3addr *hdr;
struct rtw89_sa_query *sa_query;
struct sk_buff *skb;
skb = dev_alloc_skb(sizeof(*sa_query));
skb = dev_alloc_skb(sizeof(*hdr) + sec_hdr_len + sizeof(*sa_query));
if (!skb)
return NULL;
hdr = skb_put_zero(skb, sizeof(*hdr));
hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
IEEE80211_STYPE_ACTION |
IEEE80211_FCTL_PROTECTED);
ether_addr_copy(hdr->addr1, bss_conf->bssid);
ether_addr_copy(hdr->addr2, vif->addr);
ether_addr_copy(hdr->addr3, bss_conf->bssid);
skb_put_zero(skb, sec_hdr_len);
sa_query = skb_put_zero(skb, sizeof(*sa_query));
sa_query->hdr.frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
IEEE80211_STYPE_ACTION |
IEEE80211_FCTL_PROTECTED);
ether_addr_copy(sa_query->hdr.addr1, bss_conf->bssid);
ether_addr_copy(sa_query->hdr.addr2, vif->addr);
ether_addr_copy(sa_query->hdr.addr3, bss_conf->bssid);
sa_query->category = WLAN_CATEGORY_SA_QUERY;
sa_query->action = WLAN_ACTION_SA_QUERY_RESPONSE;
@ -2238,17 +2268,19 @@ static struct sk_buff *rtw89_sa_query_get(struct rtw89_dev *rtwdev,
static struct sk_buff *rtw89_arp_response_get(struct rtw89_dev *rtwdev,
struct rtw89_vif *rtwvif)
{
u8 sec_hdr_len = rtw89_wow_get_sec_hdr_len(rtwdev);
struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
struct ieee80211_hdr_3addr *hdr;
struct rtw89_arp_rsp *arp_skb;
struct arphdr *arp_hdr;
struct sk_buff *skb;
__le16 fc;
skb = dev_alloc_skb(sizeof(struct rtw89_arp_rsp));
skb = dev_alloc_skb(sizeof(*hdr) + sec_hdr_len + sizeof(*arp_skb));
if (!skb)
return NULL;
arp_skb = skb_put_zero(skb, sizeof(*arp_skb));
hdr = skb_put_zero(skb, sizeof(*hdr));
if (rtw_wow->ptk_alg)
fc = cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_FCTL_TODS |
@ -2256,11 +2288,14 @@ static struct sk_buff *rtw89_arp_response_get(struct rtw89_dev *rtwdev,
else
fc = cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_FCTL_TODS);
arp_skb->addr.frame_control = fc;
ether_addr_copy(arp_skb->addr.addr1, rtwvif->bssid);
ether_addr_copy(arp_skb->addr.addr2, rtwvif->mac_addr);
ether_addr_copy(arp_skb->addr.addr3, rtwvif->bssid);
hdr->frame_control = fc;
ether_addr_copy(hdr->addr1, rtwvif->bssid);
ether_addr_copy(hdr->addr2, rtwvif->mac_addr);
ether_addr_copy(hdr->addr3, rtwvif->bssid);
skb_put_zero(skb, sec_hdr_len);
arp_skb = skb_put_zero(skb, sizeof(*arp_skb));
memcpy(arp_skb->llc_hdr, rfc1042_header, sizeof(rfc1042_header));
arp_skb->llc_type = htons(ETH_P_ARP);
@ -2461,6 +2496,7 @@ int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
struct rtw89_h2c_lps_ch_info *h2c;
u32 len = sizeof(*h2c);
struct sk_buff *skb;
u32 done;
int ret;
if (chip->chip_gen != RTW89_CHIP_BE)
@ -2484,12 +2520,18 @@ int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
H2C_CAT_OUTSRC, H2C_CL_OUTSRC_DM,
H2C_FUNC_FW_LPS_CH_INFO, 0, 0, len);
rtw89_phy_write32_mask(rtwdev, R_CHK_LPS_STAT, B_CHK_LPS_STAT, 0);
ret = rtw89_h2c_tx(rtwdev, skb, false);
if (ret) {
rtw89_err(rtwdev, "failed to send h2c\n");
goto fail;
}
ret = read_poll_timeout(rtw89_phy_read32_mask, done, done, 50, 5000,
true, rtwdev, R_CHK_LPS_STAT, B_CHK_LPS_STAT);
if (ret)
rtw89_warn(rtwdev, "h2c_lps_ch_info done polling timeout\n");
return 0;
fail:
dev_kfree_skb_any(skb);
@ -6732,10 +6774,8 @@ int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
skb_put(skb, len);
h2c = (struct rtw89_h2c_wow_gtk_ofld *)skb->data;
if (!enable) {
skb_put_zero(skb, sizeof(*gtk_info));
if (!enable)
goto hdr;
}
ret = rtw89_fw_h2c_add_general_pkt(rtwdev, rtwvif,
RTW89_PKT_OFLD_TYPE_EAPOL_KEY,

6
drivers/net/wireless/realtek/rtw89/fw.h
View File

@ -4659,4 +4659,10 @@ const struct rtw89_rfe_parms *
rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
const struct rtw89_rfe_parms *init);
enum rtw89_wow_wakeup_ver {
RTW89_WOW_REASON_V0,
RTW89_WOW_REASON_V1,
RTW89_WOW_REASON_NUM,
};
#endif

112
drivers/net/wireless/realtek/rtw89/mac.c
View File

@ -1568,6 +1568,8 @@ static int dmac_func_en_ax(struct rtw89_dev *rtwdev)
B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN |
B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN |
B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN);
if (chip_id == RTL8852BT)
val32 |= B_AX_AXIDMA_CLK_EN;
rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32);
return 0;
@ -1577,7 +1579,7 @@ static int chip_func_en_ax(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
if (chip_id == RTL8852A || chip_id == RTL8852B)
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
B_AX_OCP_L1_MASK);
@ -2146,8 +2148,8 @@ int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
{
const struct rtw89_chip_info *chip = rtwdev->chip;
if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
chip->chip_id == RTL8851B || !is_qta_poh(rtwdev))
if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) ||
!is_qta_poh(rtwdev))
return 0;
return preload_init_set(rtwdev, mac_idx, mode);
@ -2183,8 +2185,7 @@ static void _patch_ss2f_path(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
chip->chip_id == RTL8851B)
if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
return;
rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,
@ -2360,7 +2361,7 @@ static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
SIFS_MACTXEN_T1);
if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) {
if (rtw89_is_rtl885xb(rtwdev)) {
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx);
rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);
}
@ -2588,7 +2589,9 @@ static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
case RTL8852A:
sifs = WMAC_SPEC_SIFS_OFDM_52A;
break;
case RTL8851B:
case RTL8852B:
case RTL8852BT:
sifs = WMAC_SPEC_SIFS_OFDM_52B;
break;
default:
@ -2632,6 +2635,7 @@ static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
#define RX_MAX_LEN_UNIT 512
#define PLD_RLS_MAX_PG 127
#define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
int ret;
u32 reg, rx_max_len, rx_qta;
u16 val;
@ -2652,6 +2656,8 @@ static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
B_AX_RX_DLK_DATA_TIME_MASK);
val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO,
B_AX_RX_DLK_CCA_TIME_MASK);
if (chip_id == RTL8852BT)
val |= B_AX_RX_DLK_RST_EN;
rtw89_write16(rtwdev, reg, val);
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx);
@ -2668,8 +2674,7 @@ static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
rx_max_len /= RX_MAX_LEN_UNIT;
rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len);
if (rtwdev->chip->chip_id == RTL8852A &&
rtwdev->hal.cv == CHIP_CBV) {
if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) {
rtw89_write16_mask(rtwdev,
rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx),
B_AX_RX_DLK_CCA_TIME_MASK, 0);
@ -2700,7 +2705,7 @@ static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK);
rtw89_write32(rtwdev, reg, val);
if (chip_id == RTL8852A || chip_id == RTL8852B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
}
@ -2766,11 +2771,10 @@ static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
u32 reg;
int ret;
if (chip_id != RTL8852B)
if (!rtw89_is_rtl885xb(rtwdev))
return 0;
ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
@ -3587,13 +3591,11 @@ static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx,
static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR,
en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS);
rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR,
en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS);
if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta)
if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta)
rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1,
en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS);
}
@ -3719,10 +3721,9 @@ static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev)
static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
u32 val32;
if (chip_id == RTL8852B || chip_id == RTL8851B) {
if (rtw89_is_rtl885xb(rtwdev)) {
rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
return;
@ -3818,7 +3819,7 @@ static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev)
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
u32 val;
if (chip_id == RTL8851B)
if (chip_id == RTL8851B || chip_id == RTL8852BT)
val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN;
else
val = B_AX_DISPATCHER_CLK_EN;
@ -5201,6 +5202,46 @@ rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32
case RTW89_MAC_MRC_DEL_SCH_OK:
func = H2C_FUNC_DEL_MRC;
break;
case RTW89_MAC_MRC_EMPTY_SCH_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: empty sch fail\n");
return;
case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: role not exist fail\n");
return;
case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: data not found fail\n");
return;
case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: get next slot fail\n");
return;
case RTW89_MAC_MRC_ALT_ROLE_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: alt role fail\n");
return;
case RTW89_MAC_MRC_ADD_PSTIMER_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: add ps timer fail\n");
return;
case RTW89_MAC_MRC_MALLOC_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: malloc fail\n");
return;
case RTW89_MAC_MRC_SWITCH_CH_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: switch ch fail\n");
return;
case RTW89_MAC_MRC_TXNULL0_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: tx null-0 fail\n");
return;
case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"MRC C2H STS RPT: port func en fail\n");
return;
default:
rtw89_debug(rtwdev, RTW89_DBG_CHAN,
"invalid MRC C2H STS RPT: status %d\n", status);
@ -5463,18 +5504,19 @@ void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)
int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
u8 val;
u16 val16;
u32 val32;
int ret;
rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT);
if (rtwdev->chip->chip_id != RTL8851B)
if (chip_id != RTL8851B && chip_id != RTL8852BT)
rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN);
rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8);
rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16);
if (rtwdev->chip->chip_id != RTL8851B)
if (chip_id != RTL8851B && chip_id != RTL8852BT)
rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24);
val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0);
@ -5757,8 +5799,7 @@ bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)
if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A)
return false;
else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
chip->chip_id == RTL8851B)
else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3,
B_AX_LTE_MUX_CTRL_PATH >> 24);
@ -6319,9 +6360,30 @@ int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
return ret;
}
int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
{
struct rtw89_mac_h2c_info h2c_info = {};
struct rtw89_mac_c2h_info c2h_info = {};
u32 ret;
h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL;
h2c_info.content_len = sizeof(h2c_info.u.hdr);
h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN);
ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
if (ret)
return ret;
if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK)
ret = -EINVAL;
return ret;
}
static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
const struct rtw89_chip_info *chip = rtwdev->chip;
int ret;
if (enable_wow) {
@ -6332,12 +6394,19 @@ static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow)
}
rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE);
rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0);
rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0);
rtw89_write32(rtwdev, R_AX_TF_FWD, 0);
rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0);
if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
else
rtw89_write32_set(rtwdev, R_AX_DBG_WOW,
B_AX_DBG_WOW_CPU_IO_RX_EN);
} else {
ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false);
if (ret) {
@ -6345,6 +6414,7 @@ static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow)
return ret;
}
rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);

11
drivers/net/wireless/realtek/rtw89/mac.h
View File

@ -466,6 +466,16 @@ enum rtw89_mac_mrc_status {
RTW89_MAC_MRC_START_SCH_OK = 0,
RTW89_MAC_MRC_STOP_SCH_OK = 1,
RTW89_MAC_MRC_DEL_SCH_OK = 2,
RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16,
RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17,
RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18,
RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19,
RTW89_MAC_MRC_ALT_ROLE_FAIL = 20,
RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21,
RTW89_MAC_MRC_MALLOC_FAIL = 22,
RTW89_MAC_MRC_SWITCH_CH_FAIL = 23,
RTW89_MAC_MRC_TXNULL0_FAIL = 24,
RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25,
};
struct rtw89_mac_ax_coex {
@ -1446,5 +1456,6 @@ int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mod
int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
enum rtw89_mac_dle_rsvd_qt_type type,
struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable);
#endif

3
drivers/net/wireless/realtek/rtw89/mac80211.c
View File

@ -487,6 +487,9 @@ static void rtw89_ops_link_info_changed(struct ieee80211_hw *hw,
if (changed & BSS_CHANGED_CQM)
rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true);
if (changed & BSS_CHANGED_TPE)
rtw89_reg_6ghz_recalc(rtwdev, rtwvif, true);
mutex_unlock(&rtwdev->mutex);
}

20
drivers/net/wireless/realtek/rtw89/mac_be.c
View File

@ -2312,26 +2312,6 @@ static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev)
dump_err_status_dispatcher_be(rtwdev);
}
static int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
{
struct rtw89_mac_h2c_info h2c_info = {};
struct rtw89_mac_c2h_info c2h_info = {};
u32 ret;
h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL;
h2c_info.content_len = sizeof(h2c_info.u.hdr);
h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN);
ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
if (ret)
return ret;
if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK)
ret = -EINVAL;
return ret;
}
static int rtw89_wow_config_mac_be(struct rtw89_dev *rtwdev, bool enable_wow)
{
if (enable_wow) {

136
drivers/net/wireless/realtek/rtw89/pci.c
View File

@ -183,14 +183,17 @@ static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev,
static void rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev,
struct sk_buff *skb)
{
struct rtw89_pci_rxbd_info *rxbd_info;
struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb);
struct rtw89_pci_rxbd_info *rxbd_info;
__le32 info;
rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data;
rx_info->fs = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_FS);
rx_info->ls = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_LS);
rx_info->len = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_WRITE_SIZE);
rx_info->tag = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_TAG);
info = rxbd_info->dword;
rx_info->fs = le32_get_bits(info, RTW89_PCI_RXBD_FS);
rx_info->ls = le32_get_bits(info, RTW89_PCI_RXBD_LS);
rx_info->len = le32_get_bits(info, RTW89_PCI_RXBD_WRITE_SIZE);
rx_info->tag = le32_get_bits(info, RTW89_PCI_RXBD_TAG);
}
static int rtw89_pci_validate_rx_tag(struct rtw89_dev *rtwdev,
@ -1298,10 +1301,12 @@ u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
dma_addr_t dma, u8 *add_info_nr)
{
struct rtw89_pci_tx_addr_info_32 *txaddr_info = txaddr_info_addr;
__le16 option;
txaddr_info->length = cpu_to_le16(total_len);
txaddr_info->option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS |
RTW89_PCI_ADDR_NUM(1));
option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS | RTW89_PCI_ADDR_NUM(1));
option |= le16_encode_bits(upper_32_bits(dma), RTW89_PCI_ADDR_HIGH_MASK);
txaddr_info->option = option;
txaddr_info->dma = cpu_to_le32(dma);
*add_info_nr = 1;
@ -1328,6 +1333,8 @@ u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
length_option = FIELD_PREP(B_PCIADDR_LEN_V1_MASK, len) |
FIELD_PREP(B_PCIADDR_HIGH_SEL_V1_MASK, 0) |
FIELD_PREP(B_PCIADDR_LS_V1_MASK, remain == 0);
length_option |= u16_encode_bits(upper_32_bits(dma),
B_PCIADDR_HIGH_SEL_V1_MASK);
txaddr_info->length_opt = cpu_to_le16(length_option);
txaddr_info->dma_low_lsb = cpu_to_le16(FIELD_GET(GENMASK(15, 0), dma));
txaddr_info->dma_low_msb = cpu_to_le16(FIELD_GET(GENMASK(31, 16), dma));
@ -1418,6 +1425,7 @@ static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev,
struct sk_buff *skb = tx_req->skb;
struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb);
dma_addr_t dma;
__le16 opt;
txdesc = skb_push(skb, txdesc_size);
memset(txdesc, 0, txdesc_size);
@ -1430,7 +1438,9 @@ static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev,
}
tx_data->dma = dma;
txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS);
opt = cpu_to_le16(RTW89_PCI_TXBD_OPT_LS);
opt |= le16_encode_bits(upper_32_bits(dma), RTW89_PCI_TXBD_OPT_DMA_HI);
txbd->opt = opt;
txbd->length = cpu_to_le16(skb->len);
txbd->dma = cpu_to_le32(tx_data->dma);
skb_queue_tail(&rtwpci->h2c_queue, skb);
@ -1446,6 +1456,7 @@ static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev,
struct rtw89_core_tx_request *tx_req)
{
struct rtw89_pci_tx_wd *txwd;
__le16 opt;
int ret;
/* FWCMD queue doesn't have wd pages. Instead, it submits the CMD
@ -1470,7 +1481,9 @@ static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev,
list_add_tail(&txwd->list, &tx_ring->busy_pages);
txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS);
opt = cpu_to_le16(RTW89_PCI_TXBD_OPT_LS);
opt |= le16_encode_bits(upper_32_bits(txwd->paddr), RTW89_PCI_TXBD_OPT_DMA_HI);
txbd->opt = opt;
txbd->length = cpu_to_le16(txwd->len);
txbd->dma = cpu_to_le32(txwd->paddr);
@ -1569,6 +1582,25 @@ const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM] = {
};
EXPORT_SYMBOL(rtw89_bd_ram_table_single);
static void rtw89_pci_init_wp_16sel(struct rtw89_dev *rtwdev)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
u32 addr = info->wp_sel_addr;
u32 val;
int i;
if (!info->wp_sel_addr)
return;
for (i = 0; i < 16; i += 4) {
val = u32_encode_bits(i + 0, MASKBYTE0) |
u32_encode_bits(i + 1, MASKBYTE1) |
u32_encode_bits(i + 2, MASKBYTE2) |
u32_encode_bits(i + 3, MASKBYTE3);
rtw89_write32(rtwdev, addr + i, val);
}
}
static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
@ -1607,6 +1639,7 @@ static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev)
rtw89_write32(rtwdev, addr_bdram, val32);
}
rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma);
rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma));
}
for (i = 0; i < RTW89_RXCH_NUM; i++) {
@ -1626,10 +1659,13 @@ static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev)
rtw89_write16(rtwdev, addr_num, bd_ring->len);
rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma);
rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma));
if (info->rx_ring_eq_is_full)
rtw89_write16(rtwdev, addr_idx, bd_ring->wp);
}
rtw89_pci_init_wp_16sel(rtwdev);
}
static void rtw89_pci_release_tx_ring(struct rtw89_dev *rtwdev,
@ -2039,7 +2075,7 @@ static int rtw89_pci_write_config_byte(struct rtw89_dev *rtwdev, u16 addr,
if (!ret)
return 0;
if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B)
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
ret = rtw89_dbi_write8(rtwdev, addr, data);
return ret;
@ -2057,7 +2093,7 @@ static int rtw89_pci_read_config_byte(struct rtw89_dev *rtwdev, u16 addr,
if (!ret)
return 0;
if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B)
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
ret = rtw89_dbi_read8(rtwdev, addr, value);
return ret;
@ -2137,10 +2173,9 @@ __get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate
static int rtw89_pci_autok_x(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
int ret;
if (chip_id != RTL8852B && chip_id != RTL8851B)
if (!rtw89_is_rtl885xb(rtwdev))
return 0;
ret = rtw89_write16_mdio_mask(rtwdev, RAC_REG_FLD_0, BAC_AUTOK_N_MASK,
@ -2150,14 +2185,13 @@ static int rtw89_pci_autok_x(struct rtw89_dev *rtwdev)
static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
enum rtw89_pcie_phy phy_rate;
u16 val16, mgn_set, div_set, tar;
u8 val8, bdr_ori;
bool l1_flag = false;
int ret = 0;
if (chip_id != RTL8852B && chip_id != RTL8851B)
if (!rtw89_is_rtl885xb(rtwdev))
return 0;
ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_PHY_RATE, &val8);
@ -2398,7 +2432,7 @@ static void rtw89_pci_l1off_pwroff(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
if (chip_id != RTL8852A && chip_id != RTL8852B && chip_id != RTL8851B)
if (chip_id != RTL8852A && !rtw89_is_rtl885xb(rtwdev))
return;
rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL, B_AX_L1OFF_PWR_OFF_EN);
@ -2428,7 +2462,7 @@ static void rtw89_pci_aphy_pwrcut(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
if (chip_id != RTL8852A && chip_id != RTL8852B && chip_id != RTL8851B)
if (chip_id != RTL8852A && !rtw89_is_rtl885xb(rtwdev))
return;
rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_PSUS_OFF_CAPC_EN);
@ -2438,7 +2472,7 @@ static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL,
B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL,
@ -2451,9 +2485,7 @@ static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev)
static int rtw89_pci_dphy_delay(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
if (chip_id != RTL8852B && chip_id != RTL8851B)
if (!rtw89_is_rtl885xb(rtwdev))
return 0;
return rtw89_write16_mdio_mask(rtwdev, RAC_REG_REV2, BAC_CMU_EN_DLY_MASK,
@ -2715,7 +2747,7 @@ static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev)
B_AX_PCIE_RX_APPLEN_MASK, 0);
}
if (chip_id == RTL8852A || chip_id == RTL8852B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, tx_burst);
rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, rx_burst);
} else if (chip_id == RTL8852C) {
@ -2723,7 +2755,7 @@ static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev)
rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_RXDMA_MASK, rx_burst);
}
if (chip_id == RTL8852A || chip_id == RTL8852B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
if (tag_mode == MAC_AX_TAG_SGL) {
val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) &
~B_AX_LATENCY_CONTROL;
@ -2738,7 +2770,7 @@ static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev)
rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask,
info->multi_tag_num);
if (chip_id == RTL8852A || chip_id == RTL8852B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE,
wd_dma_idle_intvl);
rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT,
@ -2951,7 +2983,7 @@ static int rtw89_pci_ops_mac_post_init_ax(struct rtw89_dev *rtwdev)
/* ltr sw trigger */
rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT);
}
if (chip_id == RTL8852A || chip_id == RTL8852B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
/* ADDR info 8-byte mode */
rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING,
B_AX_HOST_ADDR_INFO_8B_SEL);
@ -2994,6 +3026,27 @@ static void rtw89_pci_declaim_device(struct rtw89_dev *rtwdev,
pci_disable_device(pdev);
}
static void rtw89_pci_cfg_dac(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
const struct rtw89_chip_info *chip = rtwdev->chip;
if (!rtwpci->enable_dac)
return;
switch (chip->chip_id) {
case RTL8852A:
case RTL8852B:
case RTL8851B:
case RTL8852BT:
break;
default:
return;
}
rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL, RTW89_PCIE_BIT_EN_64BITS);
}
static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev,
struct pci_dev *pdev)
{
@ -3008,16 +3061,17 @@ static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev,
goto err;
}
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
rtw89_err(rtwdev, "failed to set dma mask to 32-bit\n");
goto err_release_regions;
}
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
rtw89_err(rtwdev, "failed to set consistent dma mask to 32-bit\n");
goto err_release_regions;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
if (!ret) {
rtwpci->enable_dac = true;
rtw89_pci_cfg_dac(rtwdev);
} else {
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
rtw89_err(rtwdev,
"failed to set dma and consistent mask to 32/36-bit\n");
goto err_release_regions;
}
}
resource_len = pci_resource_len(pdev, bar_id);
@ -3168,6 +3222,7 @@ static int rtw89_pci_init_rx_bd(struct rtw89_dev *rtwdev, struct pci_dev *pdev,
memset(rx_bd, 0, sizeof(*rx_bd));
rx_bd->buf_size = cpu_to_le16(buf_sz);
rx_bd->dma = cpu_to_le32(dma);
rx_bd->opt = le16_encode_bits(upper_32_bits(dma), RTW89_PCI_RXBD_OPT_DMA_HI);
rx_info->dma = dma;
return 0;
@ -3760,7 +3815,7 @@ static void rtw89_pci_clkreq_set_ax(struct rtw89_dev *rtwdev, bool enable)
if (ret)
rtw89_err(rtwdev, "failed to set CLKREQ Delay\n");
if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
if (enable)
ret = rtw89_pci_config_byte_set(rtwdev,
RTW89_PCIE_L1_CTRL,
@ -3812,7 +3867,7 @@ static void rtw89_pci_aspm_set_ax(struct rtw89_dev *rtwdev, bool enable)
if (ret)
rtw89_warn(rtwdev, "failed to read ASPM Delay\n");
if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
if (enable)
ret = rtw89_pci_config_byte_set(rtwdev,
RTW89_PCIE_L1_CTRL,
@ -3911,7 +3966,7 @@ static void rtw89_pci_l1ss_set_ax(struct rtw89_dev *rtwdev, bool enable)
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
int ret;
if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
if (enable)
ret = rtw89_pci_config_byte_set(rtwdev,
RTW89_PCIE_TIMER_CTRL,
@ -4108,7 +4163,7 @@ static int __maybe_unused rtw89_pci_suspend(struct device *dev)
rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);
rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST);
rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);
if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL,
B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1,
@ -4142,7 +4197,7 @@ static int __maybe_unused rtw89_pci_resume(struct device *dev)
rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);
rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST);
rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);
if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) {
if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL,
B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1,
@ -4155,6 +4210,7 @@ static int __maybe_unused rtw89_pci_resume(struct device *dev)
}
rtw89_pci_l2_hci_ldo(rtwdev);
rtw89_pci_disable_eq(rtwdev);
rtw89_pci_cfg_dac(rtwdev);
rtw89_pci_filter_out(rtwdev);
rtw89_pci_link_cfg(rtwdev);
rtw89_pci_l1ss_cfg(rtwdev);

24
drivers/net/wireless/realtek/rtw89/pci.h
View File

@ -724,6 +724,11 @@
#define B_AX_CH11_BUSY BIT(1)
#define B_AX_CH10_BUSY BIT(0)
#define R_AX_WP_ADDR_H_SEL0_3 0x1334
#define R_AX_WP_ADDR_H_SEL4_7 0x1338
#define R_AX_WP_ADDR_H_SEL8_11 0x133C
#define R_AX_WP_ADDR_H_SEL12_15 0x1340
#define R_BE_HAXI_DMA_STOP1 0xB010
#define B_BE_STOP_WPDMA BIT(31)
#define B_BE_STOP_CH14 BIT(14)
@ -823,6 +828,11 @@
#define R_BE_RPQ0_RXBD_DESA_L_V1 0xB308
#define R_BE_RPQ0_RXBD_DESA_H_V1 0xB30C
#define R_BE_WP_ADDR_H_SEL0_3_V1 0xB420
#define R_BE_WP_ADDR_H_SEL4_7_V1 0xB424
#define R_BE_WP_ADDR_H_SEL8_11_V1 0xB428
#define R_BE_WP_ADDR_H_SEL12_15_V1 0xB42C
/* Configure */
#define R_AX_PCIE_INIT_CFG2 0x1004
#define B_AX_WD_ITVL_IDLE GENMASK(27, 24)
@ -1055,6 +1065,7 @@
#define RTW89_PCIE_TIMER_CTRL 0x0718
#define RTW89_PCIE_BIT_L1SUB BIT(5)
#define RTW89_PCIE_L1_CTRL 0x0719
#define RTW89_PCIE_BIT_EN_64BITS BIT(5)
#define RTW89_PCIE_BIT_CLK BIT(4)
#define RTW89_PCIE_BIT_L1 BIT(3)
#define RTW89_PCIE_CLK_CTRL 0x0725
@ -1304,6 +1315,7 @@ struct rtw89_pci_info {
u32 rpwm_addr;
u32 cpwm_addr;
u32 mit_addr;
u32 wp_sel_addr;
u32 tx_dma_ch_mask;
const struct rtw89_pci_bd_idx_addr *bd_idx_addr_low_power;
const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;
@ -1330,11 +1342,11 @@ struct rtw89_pci_rx_info {
u32 fs:1, ls:1, tag:13, len:14;
};
#define RTW89_PCI_TXBD_OPTION_LS BIT(14)
struct rtw89_pci_tx_bd_32 {
__le16 length;
__le16 option;
__le16 opt;
#define RTW89_PCI_TXBD_OPT_LS BIT(14)
#define RTW89_PCI_TXBD_OPT_DMA_HI GENMASK(13, 6)
__le32 dma;
} __packed;
@ -1349,7 +1361,7 @@ struct rtw89_pci_tx_wp_info {
#define RTW89_PCI_ADDR_MSDU_LS BIT(15)
#define RTW89_PCI_ADDR_LS BIT(14)
#define RTW89_PCI_ADDR_HIGH(a) (((a) << 6) & GENMASK(13, 6))
#define RTW89_PCI_ADDR_HIGH_MASK GENMASK(13, 6)
#define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0))
struct rtw89_pci_tx_addr_info_32 {
@ -1386,7 +1398,8 @@ struct rtw89_pci_rpp_fmt {
struct rtw89_pci_rx_bd_32 {
__le16 buf_size;
__le16 rsvd;
__le16 opt;
#define RTW89_PCI_RXBD_OPT_DMA_HI GENMASK(13, 6)
__le32 dma;
} __packed;
@ -1475,6 +1488,7 @@ struct rtw89_pci {
bool running;
bool low_power;
bool under_recovery;
bool enable_dac;
struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM];
struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM];
struct sk_buff_head h2c_queue;

109
drivers/net/wireless/realtek/rtw89/phy.c
View File

@ -2,6 +2,7 @@
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#include "chan.h"
#include "coex.h"
#include "debug.h"
#include "fw.h"
@ -1676,7 +1677,7 @@ static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev)
rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
if (chip->chip_id != RTL8851B)
rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
if (chip->chip_id == RTL8852B)
if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT)
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
/* check 0x8080 */
@ -1847,6 +1848,36 @@ static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf)
return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
}
static s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63);
}
static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)
{
const u8 tssi_deviation_point = 0;
const u8 tssi_max_deviation = 2;
if (dbm <= tssi_deviation_point)
dbm -= tssi_max_deviation;
return dbm;
}
static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
{
struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
const struct rtw89_reg_6ghz_tpe *tpe = &regulatory->reg_6ghz_tpe;
s8 cstr = S8_MAX;
if (band == RTW89_BAND_6G && tpe->valid)
cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint);
return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr);
}
s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
const struct rtw89_rate_desc *rate_desc)
{
@ -1921,6 +1952,7 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
u8 regd = rtw89_regd_get(rtwdev, band);
u8 reg6 = regulatory->reg_6ghz_power;
s8 lmt = 0, sar;
s8 cstr;
switch (band) {
case RTW89_BAND_2G:
@ -1953,8 +1985,9 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt);
sar = rtw89_query_sar(rtwdev, freq);
cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
return min(lmt, sar);
return min3(lmt, sar, cstr);
}
EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
@ -2178,6 +2211,7 @@ s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
u8 regd = rtw89_regd_get(rtwdev, band);
u8 reg6 = regulatory->reg_6ghz_power;
s8 lmt_ru = 0, sar;
s8 cstr;
switch (band) {
case RTW89_BAND_2G:
@ -2210,8 +2244,9 @@ s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru);
sar = rtw89_query_sar(rtwdev, freq);
cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
return min(lmt_ru, sar);
return min3(lmt_ru, sar, cstr);
}
static void
@ -5969,6 +6004,74 @@ void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif
vif->cfg.aid, phy_idx);
}
static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc)
{
return desc->ch != 0;
}
static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc,
const struct rtw89_chan *chan)
{
if (!rfk_chan_validate_desc(desc))
return false;
if (desc->ch != chan->channel)
return false;
if (desc->has_band && desc->band != chan->band_type)
return false;
if (desc->has_bw && desc->bw != chan->band_width)
return false;
return true;
}
struct rfk_chan_iter_data {
const struct rtw89_rfk_chan_desc desc;
unsigned int found;
};
static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data)
{
struct rfk_chan_iter_data *iter_data = data;
if (rfk_chan_is_equivalent(&iter_data->desc, chan))
iter_data->found++;
return 0;
}
u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
const struct rtw89_chan *target_chan)
{
int sel = -1;
u8 i;
for (i = 0; i < desc_nr; i++) {
struct rfk_chan_iter_data iter_data = {
.desc = desc[i],
};
if (rfk_chan_is_equivalent(&desc[i], target_chan))
return i;
rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data);
if (!iter_data.found && sel == -1)
sel = i;
}
if (sel == -1) {
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"no idle rfk entry; force replace the first\n");
sel = 0;
}
return sel;
}
EXPORT_SYMBOL(rtw89_rfk_chan_lookup);
static void
_rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
{

17
drivers/net/wireless/realtek/rtw89/phy.h
View File

@ -129,6 +129,7 @@
#define EDCCA_HL_DIFF_NORMAL 8
#define RSSI_UNIT_CONVER 110
#define EDCCA_UNIT_CONVER 128
#define EDCCA_PWROFST_DEFAULT 18
enum rtw89_phy_c2h_ra_func {
RTW89_PHY_C2H_FUNC_STS_RPT,
@ -714,6 +715,19 @@ enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband sub
}
}
struct rtw89_rfk_chan_desc {
/* desc is valid iff ch is non-zero */
u8 ch;
/* To avoid us from extending old chip code every time, each new
* field must be defined along with a bool flag in positivte way.
*/
bool has_band;
u8 band;
bool has_bw;
u8 bw;
};
enum rtw89_rfk_flag {
RTW89_RFK_F_WRF = 0,
RTW89_RFK_F_WM = 1,
@ -949,5 +963,8 @@ enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx);
enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx);
u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
const struct rtw89_chan *target_chan);
#endif

56
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -311,6 +311,9 @@
#define B_AX_S1_LDO2PWRCUT_F BIT(23)
#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
#define R_AX_DBG_WOW 0x0504
#define B_AX_DBG_WOW_CPU_IO_RX_EN BIT(8)
#define R_AX_SEC_CTRL 0x0C00
#define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16)
@ -3169,6 +3172,8 @@
#define R_AX_DLK_PROTECT_CTL_C1 0xEE02
#define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
#define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
#define B_AX_RX_DLK_RST_EN BIT(1)
#define B_AX_RX_DLK_INT_EN BIT(0)
#define R_AX_PLCP_HDR_FLTR 0xCE04
#define R_AX_PLCP_HDR_FLTR_C1 0xEE04
@ -4313,6 +4318,8 @@
#define R_BE_WLCPU_PORT_PC 0x03FC
#define R_BE_DBG_WOW 0x0504
#define R_BE_DCPU_PLATFORM_ENABLE 0x0888
#define B_BE_DCPU_SYM_DPLT_MEM_MUX_EN BIT(10)
#define B_BE_DCPU_WARM_EN BIT(9)
@ -7811,6 +7818,8 @@
#define B_UPD_P0_EN BIT(31)
#define R_EMLSR 0x0044
#define B_EMLSR_PARM GENMASK(27, 12)
#define R_CHK_LPS_STAT 0x0058
#define B_CHK_LPS_STAT BIT(0)
#define R_SPOOF_CG 0x00B4
#define B_SPOOF_CG_EN BIT(17)
#define R_CHINFO_SEG 0x00B4
@ -7827,6 +7836,7 @@
#define B_ANAPAR_PW15_H2 GENMASK(27, 26)
#define R_ANAPAR 0x032C
#define B_ANAPAR_15 GENMASK(31, 16)
#define B_ANAPAR_EN1 BIT(31)
#define B_ANAPAR_ADCCLK BIT(30)
#define B_ANAPAR_FLTRST BIT(22)
#define B_ANAPAR_CRXBB GENMASK(18, 16)
@ -7868,10 +7878,12 @@
#define R_RXCCA_BE1 0x0520
#define B_RXCCA_BE1_DIS BIT(0)
#define R_UPD_CLK_ADC 0x0700
#define B_UPD_GEN_ON BIT(27)
#define B_UPD_CLK_ADC_VAL GENMASK(26, 25)
#define B_UPD_CLK_ADC_ON BIT(24)
#define B_ENABLE_CCK BIT(5)
#define R_RSTB_ASYNC 0x0704
#define B_RSTB_ASYNC_BW80 GENMASK(9, 8)
#define B_RSTB_ASYNC_ALL BIT(1)
#define R_P0_ANT_SW 0x0728
#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12)
@ -7935,6 +7947,8 @@
#define B_MEASUREMENT_TRIG_MSK BIT(2)
#define B_CCX_TRIG_OPT_MSK BIT(1)
#define B_CCX_EN_MSK BIT(0)
#define R_FAHM 0x0C1C
#define B_RXTD_CKEN BIT(2)
#define R_IFS_COUNTER 0x0C28
#define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
#define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14)
@ -7968,6 +7982,7 @@
#define B_IQK_DPK_RST BIT(0)
#define R_TX_COLLISION_T2R_ST 0x0C70
#define B_TX_COLLISION_T2R_ST_M GENMASK(25, 20)
#define B_TXRX_FORCE_VAL GENMASK(9, 0)
#define R_TXGATING 0x0C74
#define B_TXGATING_EN BIT(4)
#define R_TXRFC 0x0C7C
@ -8028,6 +8043,7 @@
#define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
#define R_P0_NRBW 0x12B8
#define B_P0_NRBW_DBG BIT(30)
#define B_P0_NRBW_RSTB BIT(28)
#define R_S0_RXDC 0x12D4
#define B_S0_RXDC_I GENMASK(25, 16)
#define B_S0_RXDC_Q GENMASK(31, 26)
@ -8109,6 +8125,8 @@
#define R_S0_ADDCK 0x1E00
#define B_S0_ADDCK_I GENMASK(9, 0)
#define B_S0_ADDCK_Q GENMASK(19, 10)
#define R_TXCKEN_FORCE 0x2008
#define B_TXCKEN_FORCE_ALL GENMASK(24, 0)
#define R_EDCCA_RPT_SEL 0x20CC
#define B_EDCCA_RPT_SEL_MSK GENMASK(2, 0)
#define R_ADC_FIFO 0x20fc
@ -8264,6 +8282,7 @@
#define R_DCFO_COMP_S0 0x448C
#define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
#define R_DCFO_WEIGHT 0x4490
#define B_DAC_CLK_IDX BIT(31)
#define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
#define R_DCFO_OPT 0x4494
#define B_DCFO_OPT_EN BIT(29)
@ -8379,6 +8398,7 @@
#define B_CDD_EVM_CHK_EN BIT(0)
#define R_PATH0_BAND_SEL_V1 0x4738
#define B_PATH0_BAND_SEL_MSK_V1 BIT(17)
#define B_PATH0_BAND_NRBW_EN_V1 BIT(16)
#define R_PATH0_BT_SHARE_V1 0x4738
#define B_PATH0_BT_SHARE_V1 BIT(19)
#define R_PATH0_BTG_PATH_V1 0x4738
@ -8422,6 +8442,7 @@
#define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
#define R_PATH1_BAND_SEL_V1 0x4AA4
#define B_PATH1_BAND_SEL_MSK_V1 BIT(17)
#define B_PATH1_BAND_NRBW_EN_V1 BIT(16)
#define R_PATH1_BT_SHARE_V1 0x4AA4
#define B_PATH1_BT_SHARE_V1 BIT(19)
#define R_PATH1_BTG_PATH_V1 0x4AA4
@ -8442,6 +8463,8 @@
#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30)
#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29)
#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
#define R_PWOFST 0x488C
#define B_PWOFST GENMASK(21, 17)
#define R_2P4G_BAND 0x4970
#define B_2P4G_BAND_SEL BIT(1)
#define R_FC0_BW 0x4974
@ -8622,6 +8645,8 @@
#define B_P0_TMETER GENMASK(15, 10)
#define B_P0_TMETER_DIS BIT(16)
#define B_P0_TMETER_TRK BIT(24)
#define R_P0_ADCFF_EN 0x58C8
#define B_P0_ADCFF_EN BIT(24)
#define R_P1_TSSIC 0x7814
#define B_P1_TSSIC_BYPASS BIT(11)
#define R_P0_TSSI_TRK 0x5818
@ -8633,7 +8658,9 @@
#define B_P0_TSSI_EN BIT(31)
#define B_P0_TSSI_AVG GENMASK(15, 12)
#define R_P0_RFCTM 0x5864
#define B_P0_CLKG_FORCE GENMASK(31, 30)
#define B_P0_RFCTM_EN BIT(29)
#define B_P0_GOT_TXRX GENMASK(28, 27)
#define B_P0_RFCTM_VAL GENMASK(25, 20)
#define R_P0_RFCTM_RDY BIT(26)
#define R_P0_TRSW 0x5868
@ -8666,12 +8693,14 @@
#define B_P0_RFM_BT_EN BIT(5)
#define B_P0_RFM_OUT GENMASK(4, 0)
#define R_P0_PATH_RST 0x58AC
#define B_P0_PATH_RST BIT(27)
#define R_P0_TXDPD 0x58D4
#define B_P0_TXDPD GENMASK(31, 28)
#define R_P0_TXPW_RSTB 0x58DC
#define B_P0_TXPW_RSTB_MANON BIT(30)
#define B_P0_TXPW_RSTB_TSSI BIT(31)
#define R_P0_TSSI_MV_AVG 0x58E4
#define B_P0_TXPW_RSTB GENMASK(28, 27)
#define B_P0_TSSI_MV_MIX GENMASK(19, 11)
#define B_P0_TSSI_MV_AVG GENMASK(13, 11)
#define B_P0_TSSI_MV_CLR BIT(14)
@ -8796,6 +8825,10 @@
#define B_P1_TSSI_ALIM2 GENMASK(29, 0)
#define R_P1_TSSI_ADC_CLK 0x766c
#define B_P1_TSSI_ADC_CLK GENMASK(17, 16)
#define R_P1_TXAGC_TH 0x7800
#define B_P1_TXAGC_MAXMIN GENMASK(15, 0)
#define R_P1_TXPW_FORCE 0x780C
#define B_P1_TXPW_RDY BIT(15)
#define R_P1_TSSIC 0x7814
#define B_P1_TSSIC_BYPASS BIT(11)
#define R_P1_TMETER 0x7810
@ -8811,14 +8844,20 @@
#define B_P1_TSSI_EN BIT(31)
#define B_P1_TSSI_AVG GENMASK(15, 12)
#define R_P1_RFCTM 0x7864
#define B_P1_CLKG_FORCE GENMASK(31, 30)
#define B_P1_GOT_TXRX GENMASK(28, 27)
#define R_P1_RFCTM_RDY BIT(26)
#define B_P1_RFCTM_VAL GENMASK(25, 20)
#define B_P1_RFCTM_DEL GENMASK(19, 11)
#define R_P1_PATH_RST 0x78AC
#define B_P1_PATH_RST BIT(27)
#define R_P1_ADCFF_EN 0x78C8
#define B_P1_ADCFF_EN BIT(24)
#define R_P1_TXPW_RSTB 0x78DC
#define B_P1_TXPW_RSTB_MANON BIT(30)
#define B_P1_TXPW_RSTB_TSSI BIT(31)
#define R_P1_TSSI_MV_AVG 0x78E4
#define B_P1_TXPW_RSTB GENMASK(28, 27)
#define B_P1_TSSI_MV_MIX GENMASK(19, 11)
#define B_P1_TSSI_MV_AVG GENMASK(13, 11)
#define B_P1_TSSI_MV_CLR BIT(14)
@ -9003,6 +9042,7 @@
#define R_IQRSN 0x8220
#define B_IQRSN_K1 BIT(28)
#define B_IQRSN_K2 BIT(16)
#define R_DPD_CH0B 0x82BC
#define R_RXCFIR_P0C0 0x8D40
#define R_RXCFIR_P0C1 0x8D84
#define R_RXCFIR_P0C2 0x8DC8
@ -9036,15 +9076,18 @@
#define B_IQKINF2_FCNT GENMASK(23, 16)
#define B_IQKINF2_KCNT GENMASK(15, 8)
#define B_IQKINF2_NCTLV GENMASK(7, 0)
#define R_RFK_ST 0xBFF8
#define R_DCOF0 0xC000
#define B_DCOF0_RST BIT(17)
#define B_DCOF0_V GENMASK(4, 1)
#define R_DCOF1 0xC004
#define B_DCOF1_VAL GENMASK(31, 20)
#define B_DCOF1_RST BIT(17)
#define B_DCOF1_S BIT(0)
#define R_DCOF8 0xC020
#define B_DCOF8_V GENMASK(4, 1)
#define R_DCOF9 0xC024
#define B_DCOF9_VAL GENMASK(31, 20)
#define B_DCOF9_RST BIT(17)
#define R_DACK_S0P0 0xC040
#define B_DACK_S0P0_OK BIT(31)
@ -9095,6 +9138,7 @@
#define R_ADCMOD 0xC0E8
#define B_ADCMOD_LP GENMASK(31, 16)
#define R_DCIM 0xC0EC
#define B_DCIM_RC GENMASK(23, 16)
#define B_DCIM_FR GENMASK(14, 13)
#define R_ADDCK0D 0xC0F0
#define B_ADDCK0D_VAL2 GENMASK(31, 26)
@ -9117,11 +9161,18 @@
#define B_ADDCKR0_DC GENMASK(15, 4)
#define B_ADDCKR0_A1 GENMASK(9, 0)
#define R_DACK10 0xC100
#define B_DACK10_RST BIT(17)
#define B_DACK10 GENMASK(4, 1)
#define R_DACK1_K 0xc104
#define B_DACK1_VAL GENMASK(31, 20)
#define B_DACK1_RST BIT(17)
#define B_DACK1_EN BIT(0)
#define R_DACK11 0xC120
#define B_DACK11 GENMASK(4, 1)
#define R_DACK2_K 0xC124
#define B_DACK2_VAL GENMASK(31, 20)
#define B_DACK2_RST BIT(17)
#define B_DACK2_EN BIT(0)
#define R_DACK_S1P0 0xC140
#define B_DACK_S1P0_OK BIT(31)
#define R_DACK_BIAS10 0xC148
@ -9170,6 +9221,11 @@
#define B_DACKN0_V GENMASK(21, 14)
#define R_DACKN1_CTL 0xC224
#define B_DACKN1_V GENMASK(21, 14)
#define B_DACKN1_ON BIT(0)
#define R_DACKN2_CTL 0xC238
#define B_DACKN2_ON BIT(0)
#define R_DACKN3_CTL 0xC24C
#define B_DACKN3_ON BIT(0)
#define R_GAIN_MAP0 0xE44C
#define B_GAIN_MAP0_EN BIT(0)
#define R_GAIN_MAP1 0xE54C

190
drivers/net/wireless/realtek/rtw89/regd.c
View File

@ -714,7 +714,154 @@ exit:
mutex_unlock(&rtwdev->mutex);
}
static void __rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev)
/* Maximum Transmit Power field (@raw) can be EIRP or PSD.
* Both units are 0.5 dB-based. Return a constraint in dB.
*/
static s8 tpe_get_constraint(s8 raw)
{
const u8 hw_deviation = 3; /* unit: 0.5 dB */
const u8 antenna_gain = 10; /* unit: 0.5 dB */
const u8 array_gain = 6; /* unit: 0.5 dB */
const u8 offset = hw_deviation + antenna_gain + array_gain;
return (raw - offset) / 2;
}
static void tpe_intersect_constraint(struct rtw89_reg_6ghz_tpe *tpe, s8 cstr)
{
if (tpe->valid) {
tpe->constraint = min(tpe->constraint, cstr);
return;
}
tpe->constraint = cstr;
tpe->valid = true;
}
static void tpe_deal_with_eirp(struct rtw89_reg_6ghz_tpe *tpe,
const struct ieee80211_parsed_tpe_eirp *eirp)
{
unsigned int i;
s8 cstr;
if (!eirp->valid)
return;
for (i = 0; i < eirp->count; i++) {
cstr = tpe_get_constraint(eirp->power[i]);
tpe_intersect_constraint(tpe, cstr);
}
}
static s8 tpe_convert_psd_to_eirp(s8 psd)
{
static const unsigned int mlog20 = 1301;
return psd + 10 * mlog20 / 1000;
}
static void tpe_deal_with_psd(struct rtw89_reg_6ghz_tpe *tpe,
const struct ieee80211_parsed_tpe_psd *psd)
{
unsigned int i;
s8 cstr_psd;
s8 cstr;
if (!psd->valid)
return;
for (i = 0; i < psd->count; i++) {
cstr_psd = tpe_get_constraint(psd->power[i]);
cstr = tpe_convert_psd_to_eirp(cstr_psd);
tpe_intersect_constraint(tpe, cstr);
}
}
static void rtw89_calculate_tpe(struct rtw89_dev *rtwdev,
struct rtw89_reg_6ghz_tpe *result_tpe,
const struct ieee80211_parsed_tpe *parsed_tpe)
{
static const u8 category = IEEE80211_TPE_CAT_6GHZ_DEFAULT;
tpe_deal_with_eirp(result_tpe, &parsed_tpe->max_local[category]);
tpe_deal_with_eirp(result_tpe, &parsed_tpe->max_reg_client[category]);
tpe_deal_with_psd(result_tpe, &parsed_tpe->psd_local[category]);
tpe_deal_with_psd(result_tpe, &parsed_tpe->psd_reg_client[category]);
}
static bool __rtw89_reg_6ghz_tpe_recalc(struct rtw89_dev *rtwdev)
{
struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
struct rtw89_reg_6ghz_tpe new = {};
struct rtw89_vif *rtwvif;
bool changed = false;
rtw89_for_each_rtwvif(rtwdev, rtwvif) {
const struct rtw89_reg_6ghz_tpe *tmp;
const struct rtw89_chan *chan;
chan = rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx);
if (chan->band_type != RTW89_BAND_6G)
continue;
tmp = &rtwvif->reg_6ghz_tpe;
if (!tmp->valid)
continue;
tpe_intersect_constraint(&new, tmp->constraint);
}
if (memcmp(&regulatory->reg_6ghz_tpe, &new,
sizeof(regulatory->reg_6ghz_tpe)) != 0)
changed = true;
if (changed) {
if (new.valid)
rtw89_debug(rtwdev, RTW89_DBG_REGD,
"recalc 6 GHz reg TPE to %d dBm\n",
new.constraint);
else
rtw89_debug(rtwdev, RTW89_DBG_REGD,
"recalc 6 GHz reg TPE to none\n");
regulatory->reg_6ghz_tpe = new;
}
return changed;
}
static int rtw89_reg_6ghz_tpe_recalc(struct rtw89_dev *rtwdev,
struct rtw89_vif *rtwvif, bool active,
unsigned int *changed)
{
struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
struct rtw89_reg_6ghz_tpe *tpe = &rtwvif->reg_6ghz_tpe;
memset(tpe, 0, sizeof(*tpe));
if (!active || rtwvif->reg_6ghz_power != RTW89_REG_6GHZ_POWER_STD)
goto bottom;
rtw89_calculate_tpe(rtwdev, tpe, &bss_conf->tpe);
if (!tpe->valid)
goto bottom;
if (tpe->constraint < RTW89_MIN_VALID_POWER_CONSTRAINT) {
rtw89_err(rtwdev,
"%s: constraint %d dBm is less than min valid val\n",
__func__, tpe->constraint);
tpe->valid = false;
return -EINVAL;
}
bottom:
*changed += __rtw89_reg_6ghz_tpe_recalc(rtwdev);
return 0;
}
static bool __rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev)
{
struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
const struct rtw89_regd *regd = regulatory->regd;
@ -751,23 +898,21 @@ static void __rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev)
}
if (regulatory->reg_6ghz_power == sel)
return;
return false;
rtw89_debug(rtwdev, RTW89_DBG_REGD,
"recalc 6 GHz reg power type to %d\n", sel);
regulatory->reg_6ghz_power = sel;
rtw89_core_set_chip_txpwr(rtwdev);
return true;
}
void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
struct rtw89_vif *rtwvif, bool active)
static int rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
struct rtw89_vif *rtwvif, bool active,
unsigned int *changed)
{
struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
lockdep_assert_held(&rtwdev->mutex);
if (active) {
switch (vif->bss_conf.power_type) {
case IEEE80211_REG_VLP_AP:
@ -787,5 +932,32 @@ void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
rtwvif->reg_6ghz_power = RTW89_REG_6GHZ_POWER_DFLT;
}
__rtw89_reg_6ghz_power_recalc(rtwdev);
*changed += __rtw89_reg_6ghz_power_recalc(rtwdev);
return 0;
}
int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
bool active)
{
unsigned int changed = 0;
int ret;
lockdep_assert_held(&rtwdev->mutex);
/* The result of reg_6ghz_tpe may depend on reg_6ghz_power type,
* so must do reg_6ghz_tpe_recalc() after reg_6ghz_power_recalc().
*/
ret = rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, active, &changed);
if (ret)
return ret;
ret = rtw89_reg_6ghz_tpe_recalc(rtwdev, rtwvif, active, &changed);
if (ret)
return ret;
if (changed)
rtw89_core_set_chip_txpwr(rtwdev);
return 0;
}

6
drivers/net/wireless/realtek/rtw89/rtw8851b.c
View File

@ -105,6 +105,10 @@ static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = {
R_AX_C2HREG_DATA3
};
static const u32 rtw8851b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
};
static const struct rtw89_page_regs rtw8851b_page_regs = {
.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
@ -2509,7 +2513,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
.c2h_regs = rtw8851b_c2h_regs,
.page_regs = &rtw8851b_page_regs,
.wow_reason_reg = R_AX_C2HREG_DATA3 + 3,
.wow_reason_reg = rtw8851b_wow_wakeup_regs,
.cfo_src_fd = true,
.cfo_hw_comp = true,
.dcfo_comp = &rtw8851b_dcfo_comp,

1
drivers/net/wireless/realtek/rtw89/rtw8851be.c
View File

@ -46,6 +46,7 @@ static const struct rtw89_pci_info rtw8851b_pci_info = {
.rpwm_addr = R_AX_PCIE_HRPWM,
.cpwm_addr = R_AX_CPWM,
.mit_addr = R_AX_INT_MIT_RX,
.wp_sel_addr = 0,
.tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) |
BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) |
BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11),

6
drivers/net/wireless/realtek/rtw89/rtw8852a.c
View File

@ -398,6 +398,10 @@ static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
R_AX_C2HREG_DATA3
};
static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
};
static const struct rtw89_page_regs rtw8852a_page_regs = {
.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
@ -2225,7 +2229,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.c2h_regs = rtw8852a_c2h_regs,
.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
.page_regs = &rtw8852a_page_regs,
.wow_reason_reg = R_AX_C2HREG_DATA3 + 3,
.wow_reason_reg = rtw8852a_wow_wakeup_regs,
.cfo_src_fd = false,
.cfo_hw_comp = false,
.dcfo_comp = &rtw8852a_dcfo_comp,

1
drivers/net/wireless/realtek/rtw89/rtw8852ae.c
View File

@ -46,6 +46,7 @@ static const struct rtw89_pci_info rtw8852a_pci_info = {
.rpwm_addr = R_AX_PCIE_HRPWM,
.cpwm_addr = R_AX_CPWM,
.mit_addr = R_AX_INT_MIT_RX,
.wp_sel_addr = 0,
.tx_dma_ch_mask = 0,
.bd_idx_addr_low_power = NULL,
.dma_addr_set = &rtw89_pci_ch_dma_addr_set,

1866
drivers/net/wireless/realtek/rtw89/rtw8852b.c
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File diff suppressed because it is too large Load Diff

122
drivers/net/wireless/realtek/rtw89/rtw8852b.h
View File

@ -10,128 +10,6 @@
#define RF_PATH_NUM_8852B 2
#define BB_PATH_NUM_8852B 2
enum rtw8852b_pmac_mode {
NONE_TEST,
PKTS_TX,
PKTS_RX,
CONT_TX
};
struct rtw8852b_u_efuse {
u8 rsvd[0x88];
u8 mac_addr[ETH_ALEN];
};
struct rtw8852b_e_efuse {
u8 mac_addr[ETH_ALEN];
};
struct rtw8852b_tssi_offset {
u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
u8 rsvd[7];
u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
} __packed;
struct rtw8852b_efuse {
u8 rsvd[0x210];
struct rtw8852b_tssi_offset path_a_tssi;
u8 rsvd1[10];
struct rtw8852b_tssi_offset path_b_tssi;
u8 rsvd2[94];
u8 channel_plan;
u8 xtal_k;
u8 rsvd3;
u8 iqk_lck;
u8 rsvd4[5];
u8 reg_setting:2;
u8 tx_diversity:1;
u8 rx_diversity:2;
u8 ac_mode:1;
u8 module_type:2;
u8 rsvd5;
u8 shared_ant:1;
u8 coex_type:3;
u8 ant_iso:1;
u8 radio_on_off:1;
u8 rsvd6:2;
u8 eeprom_version;
u8 customer_id;
u8 tx_bb_swing_2g;
u8 tx_bb_swing_5g;
u8 tx_cali_pwr_trk_mode;
u8 trx_path_selection;
u8 rfe_type;
u8 country_code[2];
u8 rsvd7[3];
u8 path_a_therm;
u8 path_b_therm;
u8 rsvd8[2];
u8 rx_gain_2g_ofdm;
u8 rsvd9;
u8 rx_gain_2g_cck;
u8 rsvd10;
u8 rx_gain_5g_low;
u8 rsvd11;
u8 rx_gain_5g_mid;
u8 rsvd12;
u8 rx_gain_5g_high;
u8 rsvd13[35];
u8 path_a_cck_pwr_idx[6];
u8 path_a_bw40_1tx_pwr_idx[5];
u8 path_a_ofdm_1tx_pwr_idx_diff:4;
u8 path_a_bw20_1tx_pwr_idx_diff:4;
u8 path_a_bw20_2tx_pwr_idx_diff:4;
u8 path_a_bw40_2tx_pwr_idx_diff:4;
u8 path_a_cck_2tx_pwr_idx_diff:4;
u8 path_a_ofdm_2tx_pwr_idx_diff:4;
u8 rsvd14[0xf2];
union {
struct rtw8852b_u_efuse u;
struct rtw8852b_e_efuse e;
};
} __packed;
struct rtw8852b_bb_pmac_info {
u8 en_pmac_tx:1;
u8 is_cck:1;
u8 mode:3;
u8 rsvd:3;
u16 tx_cnt;
u16 period;
u16 tx_time;
u8 duty_cycle;
};
struct rtw8852b_bb_tssi_bak {
u8 tx_path;
u8 rx_path;
u32 p0_rfmode;
u32 p0_rfmode_ftm;
u32 p1_rfmode;
u32 p1_rfmode_ftm;
s16 tx_pwr; /* S9 */
};
extern const struct rtw89_chip_info rtw8852b_chip_info;
void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev);
void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
struct rtw8852b_bb_pmac_info *tx_info,
enum rtw89_phy_idx idx);
void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
u16 tx_cnt, u16 period, u16 tx_time,
enum rtw89_phy_idx idx);
void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
enum rtw89_phy_idx idx);
void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path);
void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
enum rtw89_rf_path_bit rx_path);
void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx idx, u8 mode);
void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
struct rtw8852b_bb_tssi_bak *bak);
void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
const struct rtw8852b_bb_tssi_bak *bak);
#endif

2053
drivers/net/wireless/realtek/rtw89/rtw8852b_common.c Normal file
View File

File diff suppressed because it is too large Load Diff

388
drivers/net/wireless/realtek/rtw89/rtw8852b_common.h Normal file
View File

@ -0,0 +1,388 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2024 Realtek Corporation
*/
#ifndef __RTW89_8852BX_H__
#define __RTW89_8852BX_H__
#include "core.h"
#define RF_PATH_NUM_8852BX 2
#define BB_PATH_NUM_8852BX 2
enum rtw8852bx_pmac_mode {
NONE_TEST,
PKTS_TX,
PKTS_RX,
CONT_TX
};
struct rtw8852bx_u_efuse {
u8 rsvd[0x88];
u8 mac_addr[ETH_ALEN];
};
struct rtw8852bx_e_efuse {
u8 mac_addr[ETH_ALEN];
};
struct rtw8852bx_tssi_offset {
u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
u8 rsvd[7];
u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
} __packed;
struct rtw8852bx_efuse {
u8 rsvd[0x210];
struct rtw8852bx_tssi_offset path_a_tssi;
u8 rsvd1[10];
struct rtw8852bx_tssi_offset path_b_tssi;
u8 rsvd2[94];
u8 channel_plan;
u8 xtal_k;
u8 rsvd3;
u8 iqk_lck;
u8 rsvd4[5];
u8 reg_setting:2;
u8 tx_diversity:1;
u8 rx_diversity:2;
u8 ac_mode:1;
u8 module_type:2;
u8 rsvd5;
u8 shared_ant:1;
u8 coex_type:3;
u8 ant_iso:1;
u8 radio_on_off:1;
u8 rsvd6:2;
u8 eeprom_version;
u8 customer_id;
u8 tx_bb_swing_2g;
u8 tx_bb_swing_5g;
u8 tx_cali_pwr_trk_mode;
u8 trx_path_selection;
u8 rfe_type;
u8 country_code[2];
u8 rsvd7[3];
u8 path_a_therm;
u8 path_b_therm;
u8 rsvd8[2];
u8 rx_gain_2g_ofdm;
u8 rsvd9;
u8 rx_gain_2g_cck;
u8 rsvd10;
u8 rx_gain_5g_low;
u8 rsvd11;
u8 rx_gain_5g_mid;
u8 rsvd12;
u8 rx_gain_5g_high;
u8 rsvd13[35];
u8 path_a_cck_pwr_idx[6];
u8 path_a_bw40_1tx_pwr_idx[5];
u8 path_a_ofdm_1tx_pwr_idx_diff:4;
u8 path_a_bw20_1tx_pwr_idx_diff:4;
u8 path_a_bw20_2tx_pwr_idx_diff:4;
u8 path_a_bw40_2tx_pwr_idx_diff:4;
u8 path_a_cck_2tx_pwr_idx_diff:4;
u8 path_a_ofdm_2tx_pwr_idx_diff:4;
u8 rsvd14[0xf2];
union {
struct rtw8852bx_u_efuse u;
struct rtw8852bx_e_efuse e;
};
} __packed;
struct rtw8852bx_bb_pmac_info {
u8 en_pmac_tx:1;
u8 is_cck:1;
u8 mode:3;
u8 rsvd:3;
u16 tx_cnt;
u16 period;
u16 tx_time;
u8 duty_cycle;
};
struct rtw8852bx_bb_tssi_bak {
u8 tx_path;
u8 rx_path;
u32 p0_rfmode;
u32 p0_rfmode_ftm;
u32 p1_rfmode;
u32 p1_rfmode_ftm;
s16 tx_pwr; /* S9 */
};
struct rtw8852bx_info {
int (*mac_enable_bb_rf)(struct rtw89_dev *rtwdev);
int (*mac_disable_bb_rf)(struct rtw89_dev *rtwdev);
void (*bb_sethw)(struct rtw89_dev *rtwdev);
void (*bb_reset_all)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void (*bb_cfg_txrx_path)(struct rtw89_dev *rtwdev);
void (*bb_cfg_tx_path)(struct rtw89_dev *rtwdev, u8 tx_path);
void (*bb_ctrl_rx_path)(struct rtw89_dev *rtwdev,
enum rtw89_rf_path_bit rx_path);
void (*bb_set_plcp_tx)(struct rtw89_dev *rtwdev);
void (*bb_set_power)(struct rtw89_dev *rtwdev, s16 pwr_dbm,
enum rtw89_phy_idx idx);
void (*bb_set_pmac_pkt_tx)(struct rtw89_dev *rtwdev, u8 enable,
u16 tx_cnt, u16 period, u16 tx_time,
enum rtw89_phy_idx idx);
void (*bb_backup_tssi)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
struct rtw8852bx_bb_tssi_bak *bak);
void (*bb_restore_tssi)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
const struct rtw8852bx_bb_tssi_bak *bak);
void (*bb_tx_mode_switch)(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx idx, u8 mode);
void (*set_channel_mac)(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan, u8 mac_idx);
void (*set_channel_bb)(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx);
void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
enum rtw89_phy_idx phy_idx);
void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
enum rtw89_phy_idx phy_idx);
void (*query_ppdu)(struct rtw89_dev *rtwdev,
struct rtw89_rx_phy_ppdu *phy_ppdu,
struct ieee80211_rx_status *status);
int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
enum rtw89_efuse_block block);
int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
void (*power_trim)(struct rtw89_dev *rtwdev);
void (*set_txpwr)(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx);
void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx);
int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
s8 pw_ofst, enum rtw89_mac_idx mac_idx);
u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
void (*adc_cfg)(struct rtw89_dev *rtwdev, u8 bw, u8 path);
void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
};
extern const struct rtw8852bx_info rtw8852bx_info;
static inline
int rtw8852bx_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
{
return rtw8852bx_info.mac_enable_bb_rf(rtwdev);
}
static inline
int rtw8852bx_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
{
return rtw8852bx_info.mac_disable_bb_rf(rtwdev);
}
static inline
void rtw8852bx_bb_sethw(struct rtw89_dev *rtwdev)
{
rtw8852bx_info.bb_sethw(rtwdev);
}
static inline
void rtw8852bx_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
rtw8852bx_info.bb_reset_all(rtwdev, phy_idx);
}
static inline
void rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
{
rtw8852bx_info.bb_cfg_txrx_path(rtwdev);
}
static inline
void rtw8852bx_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
{
rtw8852bx_info.bb_cfg_tx_path(rtwdev, tx_path);
}
static inline
void rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
enum rtw89_rf_path_bit rx_path)
{
rtw8852bx_info.bb_ctrl_rx_path(rtwdev, rx_path);
}
static inline
void rtw8852bx_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
{
rtw8852bx_info.bb_set_plcp_tx(rtwdev);
}
static inline
void rtw8852bx_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
enum rtw89_phy_idx idx)
{
rtw8852bx_info.bb_set_power(rtwdev, pwr_dbm, idx);
}
static inline
void rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
u16 tx_cnt, u16 period, u16 tx_time,
enum rtw89_phy_idx idx)
{
rtw8852bx_info.bb_set_pmac_pkt_tx(rtwdev, enable, tx_cnt, period, tx_time, idx);
}
static inline
void rtw8852bx_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
struct rtw8852bx_bb_tssi_bak *bak)
{
rtw8852bx_info.bb_backup_tssi(rtwdev, idx, bak);
}
static inline
void rtw8852bx_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
const struct rtw8852bx_bb_tssi_bak *bak)
{
rtw8852bx_info.bb_restore_tssi(rtwdev, idx, bak);
}
static inline
void rtw8852bx_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx idx, u8 mode)
{
rtw8852bx_info.bb_tx_mode_switch(rtwdev, idx, mode);
}
static inline
void rtw8852bx_set_channel_mac(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan, u8 mac_idx)
{
rtw8852bx_info.set_channel_mac(rtwdev, chan, mac_idx);
}
static inline
void rtw8852bx_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
rtw8852bx_info.set_channel_bb(rtwdev, chan, phy_idx);
}
static inline
void rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
enum rtw89_phy_idx phy_idx)
{
rtw8852bx_info.ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
}
static inline
void rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
enum rtw89_phy_idx phy_idx)
{
rtw8852bx_info.ctrl_btg_bt_rx(rtwdev, en, phy_idx);
}
static inline
void rtw8852bx_query_ppdu(struct rtw89_dev *rtwdev,
struct rtw89_rx_phy_ppdu *phy_ppdu,
struct ieee80211_rx_status *status)
{
rtw8852bx_info.query_ppdu(rtwdev, phy_ppdu, status);
}
static inline
int rtw8852bx_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
enum rtw89_efuse_block block)
{
return rtw8852bx_info.read_efuse(rtwdev, log_map, block);
}
static inline
int rtw8852bx_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
{
return rtw8852bx_info.read_phycap(rtwdev, phycap_map);
}
static inline
void rtw8852bx_power_trim(struct rtw89_dev *rtwdev)
{
rtw8852bx_info.power_trim(rtwdev);
}
static inline
void rtw8852bx_set_txpwr(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
rtw8852bx_info.set_txpwr(rtwdev, chan, phy_idx);
}
static inline
void rtw8852bx_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx)
{
rtw8852bx_info.set_txpwr_ctrl(rtwdev, phy_idx);
}
static inline
int rtw8852bx_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
return rtw8852bx_info.init_txpwr_unit(rtwdev, phy_idx);
}
static inline
void rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
s8 pw_ofst, enum rtw89_mac_idx mac_idx)
{
rtw8852bx_info.set_txpwr_ul_tb_offset(rtwdev, pw_ofst, mac_idx);
}
static inline
u8 rtw8852bx_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
{
return rtw8852bx_info.get_thermal(rtwdev, rf_path);
}
static inline
void rtw8852bx_adc_cfg(struct rtw89_dev *rtwdev, u8 bw, u8 path)
{
rtw8852bx_info.adc_cfg(rtwdev, bw, path);
}
static inline
void rtw8852bx_btc_init_cfg(struct rtw89_dev *rtwdev)
{
rtw8852bx_info.btc_init_cfg(rtwdev);
}
static inline
void rtw8852bx_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
{
rtw8852bx_info.btc_set_wl_pri(rtwdev, map, state);
}
static inline
s8 rtw8852bx_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
{
return rtw8852bx_info.btc_get_bt_rssi(rtwdev, val);
}
static inline
void rtw8852bx_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
{
rtw8852bx_info.btc_update_bt_cnt(rtwdev);
}
static inline
void rtw8852bx_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
{
rtw8852bx_info.btc_wl_s1_standby(rtwdev, state);
}
static inline
void rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
{
rtw8852bx_info.btc_set_wl_rx_gain(rtwdev, level);
}
#endif

21
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
View File

@ -8,6 +8,7 @@
#include "phy.h"
#include "reg.h"
#include "rtw8852b.h"
#include "rtw8852b_common.h"
#include "rtw8852b_rfk.h"
#include "rtw8852b_rfk_table.h"
#include "rtw8852b_table.h"
@ -20,7 +21,7 @@
#define RTW8852B_RF_REL_VERSION 34
#define RTW8852B_DPK_VER 0x0d
#define RTW8852B_DPK_RF_PATH 2
#define RTW8852B_DPK_KIP_REG_NUM 2
#define RTW8852B_DPK_KIP_REG_NUM 3
#define _TSSI_DE_MASK GENMASK(21, 12)
#define ADDC_T_AVG 100
@ -3433,13 +3434,13 @@ static void _tssi_hw_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
rx_path = RF_ABCD; /* don't change path, but still set others */
if (enable) {
rtw8852b_bb_set_plcp_tx(rtwdev);
rtw8852b_bb_cfg_tx_path(rtwdev, path);
rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path);
rtw8852b_bb_set_power(rtwdev, pwr_dbm, phy);
rtw8852bx_bb_set_plcp_tx(rtwdev);
rtw8852bx_bb_cfg_tx_path(rtwdev, path);
rtw8852bx_bb_ctrl_rx_path(rtwdev, rx_path);
rtw8852bx_bb_set_power(rtwdev, pwr_dbm, phy);
}
rtw8852b_bb_set_pmac_pkt_tx(rtwdev, enable, cnt, period, 20, phy);
rtw8852bx_bb_set_pmac_pkt_tx(rtwdev, enable, cnt, period, 20, phy);
}
static void _tssi_backup_bb_registers(struct rtw89_dev *rtwdev,
@ -3578,7 +3579,7 @@ static void _tssi_alimentk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
u32 tssi_cw_rpt[RTW8852B_TSSI_PATH_NR] = {0};
u8 channel = chan->channel;
u8 ch_idx = _tssi_ch_to_idx(rtwdev, channel);
struct rtw8852b_bb_tssi_bak tssi_bak;
struct rtw8852bx_bb_tssi_bak tssi_bak;
s32 aliment_diff, tssi_cw_default;
u32 start_time, finish_time;
u32 bb_reg_backup[8] = {0};
@ -3626,7 +3627,7 @@ static void _tssi_alimentk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
else
band = TSSI_ALIMK_2G;
rtw8852b_bb_backup_tssi(rtwdev, phy, &tssi_bak);
rtw8852bx_bb_backup_tssi(rtwdev, phy, &tssi_bak);
_tssi_backup_bb_registers(rtwdev, phy, bb_reg, bb_reg_backup, ARRAY_SIZE(bb_reg_backup));
rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x8);
@ -3730,8 +3731,8 @@ static void _tssi_alimentk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
out:
_tssi_reload_bb_registers(rtwdev, phy, bb_reg, bb_reg_backup, ARRAY_SIZE(bb_reg_backup));
rtw8852b_bb_restore_tssi(rtwdev, phy, &tssi_bak);
rtw8852b_bb_tx_mode_switch(rtwdev, phy, 0);
rtw8852bx_bb_restore_tssi(rtwdev, phy, &tssi_bak);
rtw8852bx_bb_tx_mode_switch(rtwdev, phy, 0);
finish_time = ktime_get_ns();
tssi_info->tssi_alimk_time += finish_time - start_time;

1
drivers/net/wireless/realtek/rtw89/rtw8852be.c
View File

@ -46,6 +46,7 @@ static const struct rtw89_pci_info rtw8852b_pci_info = {
.rpwm_addr = R_AX_PCIE_HRPWM,
.cpwm_addr = R_AX_CPWM,
.mit_addr = R_AX_INT_MIT_RX,
.wp_sel_addr = 0,
.tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) |
BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) |
BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11),

13
drivers/net/wireless/realtek/rtw89/rtw8852bt.h Normal file
View File

@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2024 Realtek Corporation
*/
#ifndef __RTW89_8852BT_H__
#define __RTW89_8852BT_H__
#include "core.h"
#define RF_PATH_NUM_8852BT 2
#define BB_PATH_NUM_8852BT 2
#endif

4019
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c Normal file
View File

File diff suppressed because it is too large Load Diff

22
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.h Normal file
View File

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2024 Realtek Corporation
*/
#ifndef __RTW89_8852BT_RFK_H__
#define __RTW89_8852BT_RFK_H__
#include "core.h"
void rtw8852bt_rck(struct rtw89_dev *rtwdev);
void rtw8852bt_dack(struct rtw89_dev *rtwdev);
void rtw8852bt_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8852bt_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8852bt_dpk_init(struct rtw89_dev *rtwdev);
void rtw8852bt_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
void rtw8852bt_dpk_track(struct rtw89_dev *rtwdev);
void rtw8852bt_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en);
void rtw8852bt_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
void rtw8852bt_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
enum rtw89_phy_idx phy_idx);
#endif

490
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk_table.c Normal file
View File

@ -0,0 +1,490 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2024 Realtek Corporation
*/
#include "rtw8852bt_rfk_table.h"
static const struct rtw89_reg5_def rtw8852bt_tssi_sys_defs[] = {
RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x4),
RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x4),
RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
RTW89_DECL_RFK_WM(0x0024, 0x00006000, 0x3),
RTW89_DECL_RFK_WM(0x0704, 0xffff0000, 0x601e),
RTW89_DECL_RFK_WM(0x2704, 0xffff0000, 0x601e),
RTW89_DECL_RFK_WM(0x0700, 0xf0000000, 0x4),
RTW89_DECL_RFK_WM(0x2700, 0xf0000000, 0x4),
RTW89_DECL_RFK_WM(0x0650, 0x3c000000, 0x0),
RTW89_DECL_RFK_WM(0x2650, 0x3c000000, 0x0),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_sys_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_sys_a_defs_2g[] = {
RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x33),
RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x33),
RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x1),
RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1e),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_sys_a_defs_2g);
static const struct rtw89_reg5_def rtw8852bt_tssi_sys_a_defs_5g[] = {
RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x44),
RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x44),
RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x0),
RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1d),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_sys_a_defs_5g);
static const struct rtw89_reg5_def rtw8852bt_tssi_sys_b_defs_2g[] = {
RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x33),
RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x33),
RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x1),
RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1e),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_sys_b_defs_2g);
static const struct rtw89_reg5_def rtw8852bt_tssi_sys_b_defs_5g[] = {
RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x44),
RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x44),
RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x0),
RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1d),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_sys_b_defs_5g);
static const struct rtw89_reg5_def rtw8852bt_tssi_init_txpwr_defs_a[] = {
RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
RTW89_DECL_RFK_WM(0x5800, 0xffffffff, 0x003f807f),
RTW89_DECL_RFK_WM(0x580c, 0x0000007f, 0x40),
RTW89_DECL_RFK_WM(0x580c, 0x0fffff00, 0x00040),
RTW89_DECL_RFK_WM(0x5810, 0xffffffff, 0x59010000),
RTW89_DECL_RFK_WM(0x5814, 0x01ffffff, 0x002d000),
RTW89_DECL_RFK_WM(0x5814, 0xf8000000, 0x00),
RTW89_DECL_RFK_WM(0x5818, 0xffffffff, 0x002c1800),
RTW89_DECL_RFK_WM(0x581c, 0x3fffffff, 0x1dc80280),
RTW89_DECL_RFK_WM(0x5820, 0xffffffff, 0x00002080),
RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1),
RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1),
RTW89_DECL_RFK_WM(0x5834, 0x3fffffff, 0x000115f2),
RTW89_DECL_RFK_WM(0x5838, 0x7fffffff, 0x0000121),
RTW89_DECL_RFK_WM(0x5854, 0x3fffffff, 0x000115f2),
RTW89_DECL_RFK_WM(0x5858, 0x7fffffff, 0x0000121),
RTW89_DECL_RFK_WM(0x5860, 0x80000000, 0x0),
RTW89_DECL_RFK_WM(0x5864, 0x07ffffff, 0x00801ff),
RTW89_DECL_RFK_WM(0x5898, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x589c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x58a4, 0x000000ff, 0x16),
RTW89_DECL_RFK_WM(0x58b0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x58b4, 0x7fffffff, 0x0a002000),
RTW89_DECL_RFK_WM(0x58b8, 0x7fffffff, 0x00007628),
RTW89_DECL_RFK_WM(0x58bc, 0x07ffffff, 0x7a7807f),
RTW89_DECL_RFK_WM(0x58c0, 0xfffe0000, 0x003f),
RTW89_DECL_RFK_WM(0x58c4, 0xffffffff, 0x0003ffff),
RTW89_DECL_RFK_WM(0x58c8, 0x00ffffff, 0x000000),
RTW89_DECL_RFK_WM(0x58c8, 0xf0000000, 0x0),
RTW89_DECL_RFK_WM(0x58cc, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x58d0, 0x07ffffff, 0x2008101),
RTW89_DECL_RFK_WM(0x58d4, 0x000000ff, 0x00),
RTW89_DECL_RFK_WM(0x58d4, 0x0003fe00, 0x0ff),
RTW89_DECL_RFK_WM(0x58d4, 0x07fc0000, 0x100),
RTW89_DECL_RFK_WM(0x58d8, 0xffffffff, 0x8008016c),
RTW89_DECL_RFK_WM(0x58dc, 0x0001ffff, 0x0807f),
RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0xc00),
RTW89_DECL_RFK_WM(0x58f0, 0x0003ffff, 0x001ff),
RTW89_DECL_RFK_WM(0x58f4, 0x000fffff, 0x000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_init_txpwr_defs_a);
static const struct rtw89_reg5_def rtw8852bt_tssi_init_txpwr_defs_b[] = {
RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
RTW89_DECL_RFK_WM(0x7800, 0xffffffff, 0x003f807f),
RTW89_DECL_RFK_WM(0x780c, 0x0000007f, 0x40),
RTW89_DECL_RFK_WM(0x780c, 0x0fffff00, 0x00040),
RTW89_DECL_RFK_WM(0x7810, 0xffffffff, 0x59010000),
RTW89_DECL_RFK_WM(0x7814, 0x01ffffff, 0x002d000),
RTW89_DECL_RFK_WM(0x7814, 0xf8000000, 0x00),
RTW89_DECL_RFK_WM(0x7818, 0xffffffff, 0x002c1800),
RTW89_DECL_RFK_WM(0x781c, 0x3fffffff, 0x1dc80280),
RTW89_DECL_RFK_WM(0x7820, 0xffffffff, 0x00002080),
RTW89_DECL_RFK_WM(0x780c, 0x10000000, 0x1),
RTW89_DECL_RFK_WM(0x780c, 0x40000000, 0x1),
RTW89_DECL_RFK_WM(0x7834, 0x3fffffff, 0x000115f2),
RTW89_DECL_RFK_WM(0x7838, 0x7fffffff, 0x0000121),
RTW89_DECL_RFK_WM(0x7854, 0x3fffffff, 0x000115f2),
RTW89_DECL_RFK_WM(0x7858, 0x7fffffff, 0x0000121),
RTW89_DECL_RFK_WM(0x7860, 0x80000000, 0x0),
RTW89_DECL_RFK_WM(0x7864, 0x07ffffff, 0x00801ff),
RTW89_DECL_RFK_WM(0x7898, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x789c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x78a4, 0x000000ff, 0x16),
RTW89_DECL_RFK_WM(0x78b0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x78b4, 0x7fffffff, 0x0a002000),
RTW89_DECL_RFK_WM(0x78b8, 0x7fffffff, 0x00007628),
RTW89_DECL_RFK_WM(0x78bc, 0x07ffffff, 0x7a7807f),
RTW89_DECL_RFK_WM(0x78c0, 0xfffe0000, 0x003f),
RTW89_DECL_RFK_WM(0x78c4, 0xffffffff, 0x0003ffff),
RTW89_DECL_RFK_WM(0x78c8, 0x00ffffff, 0x000000),
RTW89_DECL_RFK_WM(0x78c8, 0xf0000000, 0x0),
RTW89_DECL_RFK_WM(0x78cc, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x78d0, 0x07ffffff, 0x2008101),
RTW89_DECL_RFK_WM(0x78d4, 0x000000ff, 0x00),
RTW89_DECL_RFK_WM(0x78d4, 0x0003fe00, 0x0ff),
RTW89_DECL_RFK_WM(0x78d4, 0x07fc0000, 0x100),
RTW89_DECL_RFK_WM(0x78d8, 0xffffffff, 0x8008016c),
RTW89_DECL_RFK_WM(0x78dc, 0x0001ffff, 0x0807f),
RTW89_DECL_RFK_WM(0x78dc, 0xfff00000, 0xc00),
RTW89_DECL_RFK_WM(0x78f0, 0x0003ffff, 0x001ff),
RTW89_DECL_RFK_WM(0x78f4, 0x000fffff, 0x000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_init_txpwr_defs_b);
static const struct rtw89_reg5_def rtw8852bt_tssi_init_txpwr_he_tb_defs_a[] = {
RTW89_DECL_RFK_WM(0x58a0, 0xffffffff, 0x000000fe),
RTW89_DECL_RFK_WM(0x58e4, 0x0000007f, 0x1f),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_init_txpwr_he_tb_defs_a);
static const struct rtw89_reg5_def rtw8852bt_tssi_init_txpwr_he_tb_defs_b[] = {
RTW89_DECL_RFK_WM(0x78a0, 0xffffffff, 0x000000fe),
RTW89_DECL_RFK_WM(0x78e4, 0x0000007f, 0x1f),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_init_txpwr_he_tb_defs_b);
static const struct rtw89_reg5_def rtw8852bt_tssi_dck_defs_a[] = {
RTW89_DECL_RFK_WM(0x580c, 0x0fff0000, 0x000),
RTW89_DECL_RFK_WM(0x5814, 0x003ff000, 0x0ef),
RTW89_DECL_RFK_WM(0x5814, 0x18000000, 0x0),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_dck_defs_a);
static const struct rtw89_reg5_def rtw8852bt_tssi_dck_defs_b[] = {
RTW89_DECL_RFK_WM(0x780c, 0x0fff0000, 0x000),
RTW89_DECL_RFK_WM(0x7814, 0x003ff000, 0x0ef),
RTW89_DECL_RFK_WM(0x7814, 0x18000000, 0x0),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_dck_defs_b);
static const struct rtw89_reg5_def rtw8852bt_tssi_dac_gain_defs_a[] = {
RTW89_DECL_RFK_WM(0x58b0, 0x00000400, 0x1),
RTW89_DECL_RFK_WM(0x58b0, 0x00000fff, 0x000),
RTW89_DECL_RFK_WM(0x58b0, 0x00000800, 0x1),
RTW89_DECL_RFK_WM(0x5a00, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a04, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a08, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a0c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a10, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a14, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a18, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a1c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a20, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a24, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a28, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a2c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a30, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a34, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a38, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a3c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a40, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a44, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a48, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a4c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a50, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a54, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a58, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a5c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a60, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a64, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a68, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a6c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a70, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a74, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a78, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a7c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a80, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a84, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a88, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a8c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a90, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a94, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a98, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a9c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5aa0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5aa4, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5aa8, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5aac, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5ab0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5ab4, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5ab8, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5abc, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5ac0, 0xffffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_dac_gain_defs_a);
static const struct rtw89_reg5_def rtw8852bt_tssi_dac_gain_defs_b[] = {
RTW89_DECL_RFK_WM(0x78b0, 0x00000fff, 0x000),
RTW89_DECL_RFK_WM(0x78b0, 0x00000800, 0x1),
RTW89_DECL_RFK_WM(0x7a00, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a04, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a08, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a0c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a10, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a14, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a18, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a1c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a20, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a24, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a28, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a2c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a30, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a34, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a38, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a3c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a40, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a44, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a48, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a4c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a50, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a54, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a58, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a5c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a60, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a64, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a68, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a6c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a70, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a74, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a78, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a7c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a80, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a84, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a88, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a8c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a90, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a94, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a98, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a9c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7aa0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7aa4, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7aa8, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7aac, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7ab0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7ab4, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7ab8, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7abc, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7ac0, 0xffffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_dac_gain_defs_b);
static const struct rtw89_reg5_def rtw8852bt_tssi_slope_a_defs_2g[] = {
RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0801008),
RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201020),
RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0804008),
RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08081e28),
RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08081e28),
RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_slope_a_defs_2g);
static const struct rtw89_reg5_def rtw8852bt_tssi_slope_a_defs_5g[] = {
RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201019),
RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08081808),
RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_slope_a_defs_5g);
static const struct rtw89_reg5_def rtw8852bt_tssi_slope_b_defs_2g[] = {
RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0801008),
RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201020),
RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0804008),
RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08081e28),
RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08081e28),
RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_slope_b_defs_2g);
static const struct rtw89_reg5_def rtw8852bt_tssi_slope_b_defs_5g[] = {
RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201019),
RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08081808),
RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_slope_b_defs_5g);
static const struct rtw89_reg5_def rtw8852bt_tssi_align_a_2g_all_defs[] = {
RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x029f57c0),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000077),
RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x029f5bc0),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000076),
RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_align_a_2g_all_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_align_a_5g1_all_defs[] = {
RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x007ff3d7),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000068),
RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_align_a_5g1_all_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_align_a_5g2_all_defs[] = {
RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x00a003db),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000065),
RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_align_a_5g2_all_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_align_a_5g3_all_defs[] = {
RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01101be2),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000065),
RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_align_a_5g3_all_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_align_b_2g_all_defs[] = {
RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x023f3fb9),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000075),
RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x01df3fb8),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000074),
RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_align_b_2g_all_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_align_b_5g1_all_defs[] = {
RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x010017e0),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_align_b_5g1_all_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_align_b_5g2_all_defs[] = {
RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x01201fe2),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000066),
RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_align_b_5g2_all_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_align_b_5g3_all_defs[] = {
RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x01602fe5),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000068),
RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_align_b_5g3_all_defs);
static const struct rtw89_reg5_def rtw8852bt_tssi_slope_defs_a[] = {
RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x1),
RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1),
RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_slope_defs_a);
static const struct rtw89_reg5_def rtw8852bt_tssi_slope_defs_b[] = {
RTW89_DECL_RFK_WM(0x7814, 0x00000800, 0x1),
RTW89_DECL_RFK_WM(0x781c, 0x20000000, 0x1),
RTW89_DECL_RFK_WM(0x7814, 0x20000000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852bt_tssi_slope_defs_b);

38
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk_table.h Normal file
View File

@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2024 Realtek Corporation
*/
#ifndef __RTW89_8852BT_RFK_TABLE_H__
#define __RTW89_8852BT_RFK_TABLE_H__
#include "phy.h"
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_sys_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_sys_a_defs_2g_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_sys_a_defs_5g_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_sys_b_defs_2g_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_sys_b_defs_5g_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_init_txpwr_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_init_txpwr_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_init_txpwr_he_tb_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_init_txpwr_he_tb_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_dck_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_dck_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_dac_gain_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_dac_gain_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_slope_a_defs_2g_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_slope_a_defs_5g_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_slope_b_defs_2g_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_slope_b_defs_5g_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_align_a_2g_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_align_a_5g1_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_align_a_5g2_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_align_a_5g3_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_align_b_2g_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_align_b_5g1_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_align_b_5g2_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_align_b_5g3_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_slope_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852bt_tssi_slope_defs_b_tbl;
#endif

6
drivers/net/wireless/realtek/rtw89/rtw8852c.c
View File

@ -73,6 +73,10 @@ static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = {
R_AX_C2HREG_DATA3_V1
};
static const u32 rtw8852c_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
R_AX_C2HREG_DATA3_V1 + 3, R_AX_DBG_WOW,
};
static const struct rtw89_page_regs rtw8852c_page_regs = {
.hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1,
.ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1,
@ -3007,7 +3011,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
.c2h_regs = rtw8852c_c2h_regs,
.page_regs = &rtw8852c_page_regs,
.wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3,
.wow_reason_reg = rtw8852c_wow_wakeup_regs,
.cfo_src_fd = false,
.cfo_hw_comp = false,
.dcfo_comp = &rtw8852c_dcfo_comp,

32
drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
View File

@ -4070,12 +4070,11 @@ void rtw8852c_set_channel_rf(struct rtw89_dev *rtwdev,
void rtw8852c_mcc_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
DECLARE_BITMAP(map, RTW89_IQK_CHS_NR) = {};
struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V0] = {};
const struct rtw89_chan *chan;
enum rtw89_entity_mode mode;
u8 chan_idx;
u8 idx;
u8 i;
mode = rtw89_get_entity_mode(rtwdev);
switch (mode) {
@ -4087,34 +4086,21 @@ void rtw8852c_mcc_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_i
break;
}
for (i = 0; i <= chan_idx; i++) {
chan = rtw89_chan_get(rtwdev, i);
chan = rtw89_chan_get(rtwdev, chan_idx);
for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
if (rfk_mcc->ch[idx] == chan->channel &&
rfk_mcc->band[idx] == chan->band_type) {
if (i != chan_idx) {
set_bit(idx, map);
break;
}
for (idx = 0; idx < ARRAY_SIZE(desc); idx++) {
struct rtw89_rfk_chan_desc *p = &desc[idx];
goto bottom;
}
}
p->ch = rfk_mcc->ch[idx];
p->has_band = true;
p->band = rfk_mcc->band[idx];
}
idx = find_first_zero_bit(map, RTW89_IQK_CHS_NR);
if (idx == RTW89_IQK_CHS_NR) {
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"%s: no empty rfk table; force replace the first\n",
__func__);
idx = 0;
}
idx = rtw89_rfk_chan_lookup(rtwdev, desc, ARRAY_SIZE(desc), chan);
rfk_mcc->ch[idx] = chan->channel;
rfk_mcc->band[idx] = chan->band_type;
bottom:
rfk_mcc->table_idx = idx;
}

1
drivers/net/wireless/realtek/rtw89/rtw8852ce.c
View File

@ -55,6 +55,7 @@ static const struct rtw89_pci_info rtw8852c_pci_info = {
.rpwm_addr = R_AX_PCIE_HRPWM_V1,
.cpwm_addr = R_AX_PCIE_CRPWM,
.mit_addr = R_AX_INT_MIT_RX_V1,
.wp_sel_addr = R_AX_WP_ADDR_H_SEL0_3,
.tx_dma_ch_mask = 0,
.bd_idx_addr_low_power = &rtw8852c_bd_idx_addr_low_power,
.dma_addr_set = &rtw89_pci_ch_dma_addr_set_v1,

6
drivers/net/wireless/realtek/rtw89/rtw8922a.c
View File

@ -85,6 +85,10 @@ static const u32 rtw8922a_c2h_regs[RTW89_H2CREG_MAX] = {
R_BE_C2HREG_DATA3
};
static const u32 rtw8922a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
R_AX_C2HREG_DATA3_V1 + 3, R_BE_DBG_WOW,
};
static const struct rtw89_page_regs rtw8922a_page_regs = {
.hci_fc_ctrl = R_BE_HCI_FC_CTRL,
.ch_page_ctrl = R_BE_CH_PAGE_CTRL,
@ -2609,7 +2613,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.c2h_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
.c2h_regs = rtw8922a_c2h_regs,
.page_regs = &rtw8922a_page_regs,
.wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3,
.wow_reason_reg = rtw8922a_wow_wakeup_regs,
.cfo_src_fd = true,
.cfo_hw_comp = true,
.dcfo_comp = NULL,

17
drivers/net/wireless/realtek/rtw89/rtw8922a_rfk.c
View File

@ -255,6 +255,7 @@ static void rtw8922a_chlk_ktbl_sel(struct rtw89_dev *rtwdev, u8 kpath, u8 idx)
static void rtw8922a_chlk_reload(struct rtw89_dev *rtwdev)
{
struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V1] = {};
enum rtw89_sub_entity_idx sub_entity_idx;
const struct rtw89_chan *chan;
enum rtw89_entity_mode mode;
@ -265,16 +266,28 @@ static void rtw8922a_chlk_reload(struct rtw89_dev *rtwdev)
switch (mode) {
case RTW89_ENTITY_MODE_MCC_PREPARE:
sub_entity_idx = RTW89_SUB_ENTITY_1;
tbl_sel = 1;
break;
default:
sub_entity_idx = RTW89_SUB_ENTITY_0;
tbl_sel = 0;
break;
}
chan = rtw89_chan_get(rtwdev, sub_entity_idx);
for (tbl_sel = 0; tbl_sel < ARRAY_SIZE(desc); tbl_sel++) {
struct rtw89_rfk_chan_desc *p = &desc[tbl_sel];
p->ch = rfk_mcc->ch[tbl_sel];
p->has_band = true;
p->band = rfk_mcc->band[tbl_sel];
p->has_bw = true;
p->bw = rfk_mcc->bw[tbl_sel];
}
tbl_sel = rtw89_rfk_chan_lookup(rtwdev, desc, ARRAY_SIZE(desc), chan);
rfk_mcc->ch[tbl_sel] = chan->channel;
rfk_mcc->band[tbl_sel] = chan->band_type;
rfk_mcc->bw[tbl_sel] = chan->band_width;

1
drivers/net/wireless/realtek/rtw89/rtw8922ae.c
View File

@ -46,6 +46,7 @@ static const struct rtw89_pci_info rtw8922a_pci_info = {
.rpwm_addr = R_BE_PCIE_HRPWM,
.cpwm_addr = R_BE_PCIE_CRPWM,
.mit_addr = R_BE_PCIE_MIT_CH_EN,
.wp_sel_addr = R_BE_WP_ADDR_H_SEL0_3_V1,
.tx_dma_ch_mask = 0,
.bd_idx_addr_low_power = NULL,
.dma_addr_set = &rtw89_pci_ch_dma_addr_set_be,

106
drivers/net/wireless/realtek/rtw89/util.c Normal file
View File

@ -0,0 +1,106 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2024 Realtek Corporation
*/
#include "util.h"
#define FRAC_ROWS 3
#define FRAC_ROW_MAX (FRAC_ROWS - 1)
#define NORM_ROW_MIN FRAC_ROWS
static const u32 db_invert_table[12][8] = {
/* rows 0~2 in unit of U(32,3) */
{10, 13, 16, 20, 25, 32, 40, 50},
{64, 80, 101, 128, 160, 201, 256, 318},
{401, 505, 635, 800, 1007, 1268, 1596, 2010},
/* rows 3~11 in unit of U(32,0) */
{316, 398, 501, 631, 794, 1000, 1259, 1585},
{1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000},
{12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098},
{79433, 100000, 125893, 158489, 199526, 251189, 316228, 398107},
{501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262, 2511886},
{3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254,
15848932},
{19952623, 25118864, 31622777, 39810717, 50118723, 63095734, 79432823,
100000000},
{125892541, 158489319, 199526232, 251188643, 316227766, 398107171,
501187234, 630957345},
{794328235, 1000000000, 1258925412, 1584893192, 1995262315, 2511886432U,
3162277660U, 3981071706U},
};
u32 rtw89_linear_2_db(u64 val)
{
u8 i, j;
u32 dB;
for (i = 0; i < 12; i++) {
for (j = 0; j < 8; j++) {
if (i <= FRAC_ROW_MAX &&
(val << RTW89_LINEAR_FRAC_BITS) <= db_invert_table[i][j])
goto cnt;
else if (i > FRAC_ROW_MAX && val <= db_invert_table[i][j])
goto cnt;
}
}
return 96; /* maximum 96 dB */
cnt:
/* special cases */
if (j == 0 && i == 0)
goto end;
if (i == NORM_ROW_MIN && j == 0) {
if (db_invert_table[NORM_ROW_MIN][0] - val >
val - (db_invert_table[FRAC_ROW_MAX][7] >> RTW89_LINEAR_FRAC_BITS)) {
i = FRAC_ROW_MAX;
j = 7;
}
goto end;
}
if (i <= FRAC_ROW_MAX)
val <<= RTW89_LINEAR_FRAC_BITS;
/* compare difference to get precise dB */
if (j == 0) {
if (db_invert_table[i][j] - val >
val - db_invert_table[i - 1][7]) {
i--;
j = 7;
}
} else {
if (db_invert_table[i][j] - val >
val - db_invert_table[i][j - 1]) {
j--;
}
}
end:
dB = (i << 3) + j + 1;
return dB;
}
EXPORT_SYMBOL(rtw89_linear_2_db);
u64 rtw89_db_2_linear(u32 db)
{
u64 linear;
u8 i, j;
if (db > 96)
db = 96;
else if (db < 1)
return 1;
i = (db - 1) >> 3;
j = (db - 1) & 0x7;
linear = db_invert_table[i][j];
if (i >= NORM_ROW_MIN)
linear = linear << RTW89_LINEAR_FRAC_BITS;
return linear;
}
EXPORT_SYMBOL(rtw89_db_2_linear);

5
drivers/net/wireless/realtek/rtw89/util.h
View File

@ -6,6 +6,8 @@
#include "core.h"
#define RTW89_LINEAR_FRAC_BITS 3
#define rtw89_iterate_vifs_bh(rtwdev, iterator, data) \
ieee80211_iterate_active_interfaces_atomic((rtwdev)->hw, \
IEEE80211_IFACE_ITER_NORMAL, iterator, data)
@ -55,4 +57,7 @@ static inline void ether_addr_copy_mask(u8 *dst, const u8 *src, u8 mask)
}
}
u32 rtw89_linear_2_db(u64 linear);
u64 rtw89_db_2_linear(u32 db);
#endif

33
drivers/net/wireless/realtek/rtw89/wow.c
View File

@ -27,17 +27,23 @@ void rtw89_wow_parse_akm(struct rtw89_dev *rtwdev, struct sk_buff *skb)
rtw_wow->akm = rsn_ie->akm_cipher_suite.type;
}
#define RTW89_CIPHER_INFO_DEF(cipher) \
{WLAN_CIPHER_SUITE_ ## cipher, .fw_alg = RTW89_WOW_FW_ALG_ ## cipher, \
.len = WLAN_KEY_LEN_ ## cipher}
static const struct rtw89_cipher_info rtw89_cipher_info_defs[] = {
{WLAN_CIPHER_SUITE_WEP40, .fw_alg = 1, .len = WLAN_KEY_LEN_WEP40,},
{WLAN_CIPHER_SUITE_WEP104, .fw_alg = 2, .len = WLAN_KEY_LEN_WEP104,},
{WLAN_CIPHER_SUITE_TKIP, .fw_alg = 3, .len = WLAN_KEY_LEN_TKIP,},
{WLAN_CIPHER_SUITE_CCMP, .fw_alg = 6, .len = WLAN_KEY_LEN_CCMP,},
{WLAN_CIPHER_SUITE_GCMP, .fw_alg = 8, .len = WLAN_KEY_LEN_GCMP,},
{WLAN_CIPHER_SUITE_CCMP_256, .fw_alg = 7, .len = WLAN_KEY_LEN_CCMP_256,},
{WLAN_CIPHER_SUITE_GCMP_256, .fw_alg = 23, .len = WLAN_KEY_LEN_GCMP_256,},
{WLAN_CIPHER_SUITE_AES_CMAC, .fw_alg = 32, .len = WLAN_KEY_LEN_AES_CMAC,},
RTW89_CIPHER_INFO_DEF(WEP40),
RTW89_CIPHER_INFO_DEF(WEP104),
RTW89_CIPHER_INFO_DEF(TKIP),
RTW89_CIPHER_INFO_DEF(CCMP),
RTW89_CIPHER_INFO_DEF(GCMP),
RTW89_CIPHER_INFO_DEF(CCMP_256),
RTW89_CIPHER_INFO_DEF(GCMP_256),
RTW89_CIPHER_INFO_DEF(AES_CMAC),
};
#undef RTW89_CIPHER_INFO_DEF
static const
struct rtw89_cipher_info *rtw89_cipher_alg_recognize(u32 cipher)
{
@ -717,13 +723,18 @@ static void rtw89_wow_show_wakeup_reason(struct rtw89_dev *rtwdev)
{
struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt;
u32 wow_reason_reg = rtwdev->chip->wow_reason_reg;
struct cfg80211_wowlan_nd_info nd_info;
struct cfg80211_wowlan_wakeup wakeup = {
.pattern_idx = -1,
};
u32 wow_reason_reg;
u8 reason;
if (RTW89_CHK_FW_FEATURE(WOW_REASON_V1, &rtwdev->fw))
wow_reason_reg = rtwdev->chip->wow_reason_reg[RTW89_WOW_REASON_V1];
else
wow_reason_reg = rtwdev->chip->wow_reason_reg[RTW89_WOW_REASON_V0];
reason = rtw89_read8(rtwdev, wow_reason_reg);
switch (reason) {
case RTW89_WOW_RSN_RX_DEAUTH:
@ -1284,12 +1295,16 @@ static int rtw89_wow_disable_trx_pre(struct rtw89_dev *rtwdev)
static int rtw89_wow_disable_trx_post(struct rtw89_dev *rtwdev)
{
struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
struct ieee80211_vif *vif = rtw_wow->wow_vif;
int ret;
ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
if (ret)
rtw89_err(rtwdev, "cfg ppdu status\n");
rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true);
return ret;
}

30
drivers/net/wireless/realtek/rtw89/wow.h
View File

@ -35,6 +35,17 @@ enum rtw89_wake_reason {
RTW89_WOW_RSN_RX_NLO = 0x55,
};
enum rtw89_fw_alg {
RTW89_WOW_FW_ALG_WEP40 = 0x1,
RTW89_WOW_FW_ALG_WEP104 = 0x2,
RTW89_WOW_FW_ALG_TKIP = 0x3,
RTW89_WOW_FW_ALG_CCMP = 0x6,
RTW89_WOW_FW_ALG_CCMP_256 = 0x7,
RTW89_WOW_FW_ALG_GCMP = 0x8,
RTW89_WOW_FW_ALG_GCMP_256 = 0x9,
RTW89_WOW_FW_ALG_AES_CMAC = 0xa,
};
struct rtw89_cipher_suite {
u8 oui[3];
u8 type;
@ -64,6 +75,25 @@ struct rtw89_set_key_info_iter_data {
bool error;
};
static inline int rtw89_wow_get_sec_hdr_len(struct rtw89_dev *rtwdev)
{
struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
if (!(rtwdev->chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)))
return 0;
switch (rtw_wow->ptk_alg) {
case RTW89_WOW_FW_ALG_WEP40:
return 4;
case RTW89_WOW_FW_ALG_TKIP:
case RTW89_WOW_FW_ALG_CCMP:
case RTW89_WOW_FW_ALG_GCMP_256:
return 8;
default:
return 0;
}
}
#ifdef CONFIG_PM
int rtw89_wow_suspend(struct rtw89_dev *rtwdev, struct cfg80211_wowlan *wowlan);
int rtw89_wow_resume(struct rtw89_dev *rtwdev);