iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/amd/display: Add DCN3 DPP

Browse Source 
Add support to program the DCN3 DPP (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bhawanpreet Lakha 2020-05-21 12:35:22 -04:00 committed by Alex Deucher
parent b708205f08
commit 03f54d7d34
6 changed files with 3157 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

640
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c Normal file
View File

@ -0,0 +1,640 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "core_types.h"
#include "reg_helper.h"
#include "dcn30_dpp.h"
#include "basics/conversion.h"
#include "dcn30_cm_common.h"
#include "custom_float.h"
#define REG(reg) reg
#define CTX \
ctx //dpp->base.ctx
#undef FN
#define FN(reg_name, field_name) \
reg->shifts.field_name, reg->masks.field_name
void cm_helper_program_gamcor_xfer_func(
struct dc_context *ctx,
const struct pwl_params *params,
const struct dcn3_xfer_func_reg *reg)
{
uint32_t reg_region_cur;
unsigned int i = 0;
REG_SET_2(reg->start_cntl_b, 0,
exp_region_start, params->corner_points[0].blue.custom_float_x,
exp_resion_start_segment, 0);
REG_SET_2(reg->start_cntl_g, 0,
exp_region_start, params->corner_points[0].green.custom_float_x,
exp_resion_start_segment, 0);
REG_SET_2(reg->start_cntl_r, 0,
exp_region_start, params->corner_points[0].red.custom_float_x,
exp_resion_start_segment, 0);
REG_SET(reg->start_slope_cntl_b, 0, //linear slope at start of curve
field_region_linear_slope, params->corner_points[0].blue.custom_float_slope);
REG_SET(reg->start_slope_cntl_g, 0,
field_region_linear_slope, params->corner_points[0].green.custom_float_slope);
REG_SET(reg->start_slope_cntl_r, 0,
field_region_linear_slope, params->corner_points[0].red.custom_float_slope);
REG_SET(reg->start_end_cntl1_b, 0,
field_region_end_base, params->corner_points[1].blue.custom_float_y);
REG_SET(reg->start_end_cntl1_g, 0,
field_region_end_base, params->corner_points[1].green.custom_float_y);
REG_SET(reg->start_end_cntl1_r, 0,
field_region_end_base, params->corner_points[1].red.custom_float_y);
REG_SET_2(reg->start_end_cntl2_b, 0,
field_region_end_slope, params->corner_points[1].blue.custom_float_slope,
field_region_end, params->corner_points[1].blue.custom_float_x);
REG_SET_2(reg->start_end_cntl2_g, 0,
field_region_end_slope, params->corner_points[1].green.custom_float_slope,
field_region_end, params->corner_points[1].green.custom_float_x);
REG_SET_2(reg->start_end_cntl2_r, 0,
field_region_end_slope, params->corner_points[1].red.custom_float_slope,
field_region_end, params->corner_points[1].red.custom_float_x);
for (reg_region_cur = reg->region_start;
reg_region_cur <= reg->region_end;
reg_region_cur++) {
const struct gamma_curve *curve0 = &(params->arr_curve_points[2 * i]);
const struct gamma_curve *curve1 = &(params->arr_curve_points[(2 * i) + 1]);
REG_SET_4(reg_region_cur, 0,
exp_region0_lut_offset, curve0->offset,
exp_region0_num_segments, curve0->segments_num,
exp_region1_lut_offset, curve1->offset,
exp_region1_num_segments, curve1->segments_num);
i++;
}
}
/* driver uses 32 regions or less, but DCN HW has 34, extra 2 are set to 0 */
#define MAX_REGIONS_NUMBER 34
#define MAX_LOW_POINT 25
#define NUMBER_REGIONS 32
#define NUMBER_SW_SEGMENTS 16
bool cm3_helper_translate_curve_to_hw_format(
const struct dc_transfer_func *output_tf,
struct pwl_params *lut_params, bool fixpoint)
{
struct curve_points3 *corner_points;
struct pwl_result_data *rgb_resulted;
struct pwl_result_data *rgb;
struct pwl_result_data *rgb_plus_1;
struct fixed31_32 end_value;
int32_t region_start, region_end;
int32_t i;
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS)
return false;
PERF_TRACE_CTX(output_tf->ctx);
corner_points = lut_params->corner_points;
rgb_resulted = lut_params->rgb_resulted;
hw_points = 0;
memset(lut_params, 0, sizeof(struct pwl_params));
memset(seg_distr, 0, sizeof(seg_distr));
if (output_tf->tf == TRANSFER_FUNCTION_PQ || output_tf->tf == TRANSFER_FUNCTION_GAMMA22 ||
output_tf->tf == TRANSFER_FUNCTION_HLG) {
/* 32 segments
* segments are from 2^-25 to 2^7
*/
for (i = 0; i < NUMBER_REGIONS ; i++)
seg_distr[i] = 3;
region_start = -MAX_LOW_POINT;
region_end = NUMBER_REGIONS - MAX_LOW_POINT;
} else {
/* 10 segments
* segment is from 2^-10 to 2^0
* There are less than 256 points, for optimization
*/
seg_distr[0] = 3;
seg_distr[1] = 4;
seg_distr[2] = 4;
seg_distr[3] = 4;
seg_distr[4] = 4;
seg_distr[5] = 4;
seg_distr[6] = 4;
seg_distr[7] = 4;
seg_distr[8] = 4;
seg_distr[9] = 4;
region_start = -10;
region_end = 0;
}
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
seg_distr[i] = -1;
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
if (seg_distr[k] != -1)
hw_points += (1 << seg_distr[k]);
}
j = 0;
for (k = 0; k < (region_end - region_start); k++) {
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
start_index = (region_start + k + MAX_LOW_POINT) *
NUMBER_SW_SEGMENTS;
for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
i += increment) {
if (j == hw_points - 1)
break;
rgb_resulted[j].red = output_tf->tf_pts.red[i];
rgb_resulted[j].green = output_tf->tf_pts.green[i];
rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
j++;
}
}
/* last point */
start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
// All 3 color channels have same x
corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
dc_fixpt_from_int(region_start));
corner_points[0].green.x = corner_points[0].red.x;
corner_points[0].blue.x = corner_points[0].red.x;
corner_points[1].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
dc_fixpt_from_int(region_end));
corner_points[1].green.x = corner_points[1].red.x;
corner_points[1].blue.x = corner_points[1].red.x;
corner_points[0].red.y = rgb_resulted[0].red;
corner_points[0].green.y = rgb_resulted[0].green;
corner_points[0].blue.y = rgb_resulted[0].blue;
corner_points[0].red.slope = dc_fixpt_div(corner_points[0].red.y,
corner_points[0].red.x);
corner_points[0].green.slope = dc_fixpt_div(corner_points[0].green.y,
corner_points[0].green.x);
corner_points[0].blue.slope = dc_fixpt_div(corner_points[0].blue.y,
corner_points[0].blue.x);
/* see comment above, m_arrPoints[1].y should be the Y value for the
* region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
*/
corner_points[1].red.y = rgb_resulted[hw_points - 1].red;
corner_points[1].green.y = rgb_resulted[hw_points - 1].green;
corner_points[1].blue.y = rgb_resulted[hw_points - 1].blue;
corner_points[1].red.slope = dc_fixpt_zero;
corner_points[1].green.slope = dc_fixpt_zero;
corner_points[1].blue.slope = dc_fixpt_zero;
if (output_tf->tf == TRANSFER_FUNCTION_PQ || output_tf->tf == TRANSFER_FUNCTION_HLG) {
/* for PQ/HLG, we want to have a straight line from last HW X point,
* and the slope to be such that we hit 1.0 at 10000/1000 nits.
*/
if (output_tf->tf == TRANSFER_FUNCTION_PQ)
end_value = dc_fixpt_from_int(125);
else
end_value = dc_fixpt_from_fraction(125, 10);
corner_points[1].red.slope = dc_fixpt_div(
dc_fixpt_sub(dc_fixpt_one, corner_points[1].red.y),
dc_fixpt_sub(end_value, corner_points[1].red.x));
corner_points[1].green.slope = dc_fixpt_div(
dc_fixpt_sub(dc_fixpt_one, corner_points[1].green.y),
dc_fixpt_sub(end_value, corner_points[1].green.x));
corner_points[1].blue.slope = dc_fixpt_div(
dc_fixpt_sub(dc_fixpt_one, corner_points[1].blue.y),
dc_fixpt_sub(end_value, corner_points[1].blue.x));
}
lut_params->hw_points_num = hw_points;
k = 0;
for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
if (seg_distr[k] != -1) {
lut_params->arr_curve_points[k].segments_num =
seg_distr[k];
lut_params->arr_curve_points[i].offset =
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
}
k++;
}
if (seg_distr[k] != -1)
lut_params->arr_curve_points[k].segments_num = seg_distr[k];
rgb = rgb_resulted;
rgb_plus_1 = rgb_resulted + 1;
i = 1;
while (i != hw_points + 1) {
if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
rgb_plus_1->red = rgb->red;
if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
rgb_plus_1->green = rgb->green;
if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
rgb_plus_1->blue = rgb->blue;
rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
if (fixpoint == true) {
rgb->delta_red_reg = dc_fixpt_clamp_u0d10(rgb->delta_red);
rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green);
rgb->delta_blue_reg = dc_fixpt_clamp_u0d10(rgb->delta_blue);
rgb->red_reg = dc_fixpt_clamp_u0d14(rgb->red);
rgb->green_reg = dc_fixpt_clamp_u0d14(rgb->green);
rgb->blue_reg = dc_fixpt_clamp_u0d14(rgb->blue);
}
++rgb_plus_1;
++rgb;
++i;
}
cm3_helper_convert_to_custom_float(rgb_resulted,
lut_params->corner_points,
hw_points, fixpoint);
return true;
}
#define NUM_DEGAMMA_REGIONS 12
bool cm3_helper_translate_curve_to_degamma_hw_format(
const struct dc_transfer_func *output_tf,
struct pwl_params *lut_params)
{
struct curve_points3 *corner_points;
struct pwl_result_data *rgb_resulted;
struct pwl_result_data *rgb;
struct pwl_result_data *rgb_plus_1;
int32_t region_start, region_end;
int32_t i;
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS)
return false;
PERF_TRACE_CTX(output_tf->ctx);
corner_points = lut_params->corner_points;
rgb_resulted = lut_params->rgb_resulted;
hw_points = 0;
memset(lut_params, 0, sizeof(struct pwl_params));
memset(seg_distr, 0, sizeof(seg_distr));
region_start = -NUM_DEGAMMA_REGIONS;
region_end = 0;
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
seg_distr[i] = -1;
/* 12 segments
* segments are from 2^-12 to 0
*/
for (i = 0; i < NUM_DEGAMMA_REGIONS ; i++)
seg_distr[i] = 4;
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
if (seg_distr[k] != -1)
hw_points += (1 << seg_distr[k]);
}
j = 0;
for (k = 0; k < (region_end - region_start); k++) {
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
start_index = (region_start + k + MAX_LOW_POINT) *
NUMBER_SW_SEGMENTS;
for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
i += increment) {
if (j == hw_points - 1)
break;
rgb_resulted[j].red = output_tf->tf_pts.red[i];
rgb_resulted[j].green = output_tf->tf_pts.green[i];
rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
j++;
}
}
/* last point */
start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
dc_fixpt_from_int(region_start));
corner_points[0].green.x = corner_points[0].red.x;
corner_points[0].blue.x = corner_points[0].red.x;
corner_points[1].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
dc_fixpt_from_int(region_end));
corner_points[1].green.x = corner_points[1].red.x;
corner_points[1].blue.x = corner_points[1].red.x;
corner_points[0].red.y = rgb_resulted[0].red;
corner_points[0].green.y = rgb_resulted[0].green;
corner_points[0].blue.y = rgb_resulted[0].blue;
/* see comment above, m_arrPoints[1].y should be the Y value for the
* region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
*/
corner_points[1].red.y = rgb_resulted[hw_points - 1].red;
corner_points[1].green.y = rgb_resulted[hw_points - 1].green;
corner_points[1].blue.y = rgb_resulted[hw_points - 1].blue;
corner_points[1].red.slope = dc_fixpt_zero;
corner_points[1].green.slope = dc_fixpt_zero;
corner_points[1].blue.slope = dc_fixpt_zero;
if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
/* for PQ, we want to have a straight line from last HW X point,
* and the slope to be such that we hit 1.0 at 10000 nits.
*/
const struct fixed31_32 end_value =
dc_fixpt_from_int(125);
corner_points[1].red.slope = dc_fixpt_div(
dc_fixpt_sub(dc_fixpt_one, corner_points[1].red.y),
dc_fixpt_sub(end_value, corner_points[1].red.x));
corner_points[1].green.slope = dc_fixpt_div(
dc_fixpt_sub(dc_fixpt_one, corner_points[1].green.y),
dc_fixpt_sub(end_value, corner_points[1].green.x));
corner_points[1].blue.slope = dc_fixpt_div(
dc_fixpt_sub(dc_fixpt_one, corner_points[1].blue.y),
dc_fixpt_sub(end_value, corner_points[1].blue.x));
}
lut_params->hw_points_num = hw_points;
k = 0;
for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
if (seg_distr[k] != -1) {
lut_params->arr_curve_points[k].segments_num =
seg_distr[k];
lut_params->arr_curve_points[i].offset =
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
}
k++;
}
if (seg_distr[k] != -1)
lut_params->arr_curve_points[k].segments_num = seg_distr[k];
rgb = rgb_resulted;
rgb_plus_1 = rgb_resulted + 1;
i = 1;
while (i != hw_points + 1) {
if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
rgb_plus_1->red = rgb->red;
if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
rgb_plus_1->green = rgb->green;
if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
rgb_plus_1->blue = rgb->blue;
rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
++rgb_plus_1;
++rgb;
++i;
}
cm3_helper_convert_to_custom_float(rgb_resulted,
lut_params->corner_points,
hw_points, false);
return true;
}
bool cm3_helper_convert_to_custom_float(
struct pwl_result_data *rgb_resulted,
struct curve_points3 *corner_points,
uint32_t hw_points_num,
bool fixpoint)
{
struct custom_float_format fmt;
struct pwl_result_data *rgb = rgb_resulted;
uint32_t i = 0;
fmt.exponenta_bits = 6;
fmt.mantissa_bits = 12;
fmt.sign = false;
/* corner_points[0] - beginning base, slope offset for R,G,B
* corner_points[1] - end base, slope offset for R,G,B
*/
if (!convert_to_custom_float_format(corner_points[0].red.x, &fmt,
&corner_points[0].red.custom_float_x)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[0].green.x, &fmt,
&corner_points[0].green.custom_float_x)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[0].blue.x, &fmt,
&corner_points[0].blue.custom_float_x)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[0].red.offset, &fmt,
&corner_points[0].red.custom_float_offset)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[0].green.offset, &fmt,
&corner_points[0].green.custom_float_offset)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[0].blue.offset, &fmt,
&corner_points[0].blue.custom_float_offset)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[0].red.slope, &fmt,
&corner_points[0].red.custom_float_slope)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[0].green.slope, &fmt,
&corner_points[0].green.custom_float_slope)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[0].blue.slope, &fmt,
&corner_points[0].blue.custom_float_slope)) {
BREAK_TO_DEBUGGER();
return false;
}
if (fixpoint == true) {
corner_points[1].red.custom_float_y =
dc_fixpt_clamp_u0d14(corner_points[1].red.y);
corner_points[1].green.custom_float_y =
dc_fixpt_clamp_u0d14(corner_points[1].green.y);
corner_points[1].blue.custom_float_y =
dc_fixpt_clamp_u0d14(corner_points[1].blue.y);
} else {
if (!convert_to_custom_float_format(corner_points[1].red.y,
&fmt, &corner_points[1].red.custom_float_y)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[1].green.y,
&fmt, &corner_points[1].green.custom_float_y)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[1].blue.y,
&fmt, &corner_points[1].blue.custom_float_y)) {
BREAK_TO_DEBUGGER();
return false;
}
}
fmt.mantissa_bits = 10;
fmt.sign = false;
if (!convert_to_custom_float_format(corner_points[1].red.x, &fmt,
&corner_points[1].red.custom_float_x)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[1].green.x, &fmt,
&corner_points[1].green.custom_float_x)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[1].blue.x, &fmt,
&corner_points[1].blue.custom_float_x)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[1].red.slope, &fmt,
&corner_points[1].red.custom_float_slope)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[1].green.slope, &fmt,
&corner_points[1].green.custom_float_slope)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(corner_points[1].blue.slope, &fmt,
&corner_points[1].blue.custom_float_slope)) {
BREAK_TO_DEBUGGER();
return false;
}
if (hw_points_num == 0 || rgb_resulted == NULL || fixpoint == true)
return true;
fmt.mantissa_bits = 12;
while (i != hw_points_num) {
if (!convert_to_custom_float_format(rgb->red, &fmt,
&rgb->red_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(rgb->green, &fmt,
&rgb->green_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(rgb->blue, &fmt,
&rgb->blue_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
&rgb->delta_red_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
&rgb->delta_green_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
&rgb->delta_blue_reg)) {
BREAK_TO_DEBUGGER();
return false;
}
++rgb;
++i;
}
return true;
}
bool is_rgb_equal(const struct pwl_result_data *rgb, uint32_t num)
{
uint32_t i;
bool ret = true;
for (i = 0 ; i < num; i++) {
if (rgb[i].red_reg != rgb[i].green_reg ||
rgb[i].blue_reg != rgb[i].red_reg ||
rgb[i].blue_reg != rgb[i].green_reg) {
ret = false;
break;
}
}
return ret;
}

78
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.h Normal file
View File

@ -0,0 +1,78 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dcn10/dcn10_cm_common.h"
#ifndef __DAL_DCN30_CM_COMMON_H__
#define __DAL_DCN30_CM_COMMON_H__
#define TF_HELPER_REG_FIELD_LIST_DCN3(type) \
TF_HELPER_REG_FIELD_LIST(type);\
type field_region_start_base;\
type field_offset
struct DCN3_xfer_func_shift {
TF_HELPER_REG_FIELD_LIST_DCN3(uint8_t);
};
struct DCN3_xfer_func_mask {
TF_HELPER_REG_FIELD_LIST_DCN3(uint32_t);
};
struct dcn3_xfer_func_reg {
struct DCN3_xfer_func_shift shifts;
struct DCN3_xfer_func_mask masks;
TF_HELPER_REG_LIST;
uint32_t offset_b;
uint32_t offset_g;
uint32_t offset_r;
uint32_t start_base_cntl_b;
uint32_t start_base_cntl_g;
uint32_t start_base_cntl_r;
};
void cm_helper_program_gamcor_xfer_func(
struct dc_context *ctx,
const struct pwl_params *params,
const struct dcn3_xfer_func_reg *reg);
bool cm3_helper_translate_curve_to_hw_format(
const struct dc_transfer_func *output_tf,
struct pwl_params *lut_params, bool fixpoint);
bool cm3_helper_translate_curve_to_degamma_hw_format(
const struct dc_transfer_func *output_tf,
struct pwl_params *lut_params);
bool cm3_helper_convert_to_custom_float(
struct pwl_result_data *rgb_resulted,
struct curve_points3 *corner_points,
uint32_t hw_points_num,
bool fixpoint);
bool is_rgb_equal(const struct pwl_result_data *rgb, uint32_t num);
#endif

1414
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c Normal file
View File

File diff suppressed because it is too large Load Diff

608
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h Normal file
View File

@ -0,0 +1,608 @@
/* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DCN30_DPP_H__
#define __DCN30_DPP_H__
#include "dcn20/dcn20_dpp.h"
#define TO_DCN30_DPP(dpp)\
container_of(dpp, struct dcn3_dpp, base)
#define DPP_REG_LIST_DCN30_COMMON(id)\
SRI(CM_DEALPHA, CM, id),\
SRI(CM_MEM_PWR_STATUS, CM, id),\
SRI(CM_BIAS_CR_R, CM, id),\
SRI(CM_BIAS_Y_G_CB_B, CM, id),\
SRI(PRE_DEGAM, CNVC_CFG, id),\
SRI(CM_GAMCOR_CONTROL, CM, id),\
SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
SRI(CM_GAMCOR_LUT_DATA, CM, id),\
SRI(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),\
SRI(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),\
SRI(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),\
SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),\
SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),\
SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),\
SRI(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),\
SRI(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),\
SRI(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),\
SRI(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),\
SRI(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),\
SRI(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),\
SRI(CM_GAMCOR_RAMB_REGION_0_1, CM, id),\
SRI(CM_GAMCOR_RAMB_REGION_32_33, CM, id),\
SRI(CM_GAMCOR_RAMB_OFFSET_B, CM, id),\
SRI(CM_GAMCOR_RAMB_OFFSET_G, CM, id),\
SRI(CM_GAMCOR_RAMB_OFFSET_R, CM, id),\
SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),\
SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),\
SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),\
SRI(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),\
SRI(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),\
SRI(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),\
SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),\
SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),\
SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),\
SRI(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),\
SRI(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),\
SRI(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),\
SRI(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),\
SRI(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),\
SRI(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),\
SRI(CM_GAMCOR_RAMA_REGION_0_1, CM, id),\
SRI(CM_GAMCOR_RAMA_REGION_32_33, CM, id),\
SRI(CM_GAMCOR_RAMA_OFFSET_B, CM, id),\
SRI(CM_GAMCOR_RAMA_OFFSET_G, CM, id),\
SRI(CM_GAMCOR_RAMA_OFFSET_R, CM, id),\
SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),\
SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),\
SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),\
SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\
SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\
SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\
SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\
SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\
SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\
SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
SRI(OTG_H_BLANK, DSCL, id), \
SRI(OTG_V_BLANK, DSCL, id), \
SRI(SCL_MODE, DSCL, id), \
SRI(LB_DATA_FORMAT, DSCL, id), \
SRI(LB_MEMORY_CTRL, DSCL, id), \
SRI(DSCL_AUTOCAL, DSCL, id), \
SRI(SCL_TAP_CONTROL, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
SRI(DSCL_2TAP_CONTROL, DSCL, id), \
SRI(MPC_SIZE, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
SRI(RECOUT_START, DSCL, id), \
SRI(RECOUT_SIZE, DSCL, id), \
SRI(PRE_DEALPHA, CNVC_CFG, id), \
SRI(PRE_REALPHA, CNVC_CFG, id), \
SRI(PRE_CSC_MODE, CNVC_CFG, id), \
SRI(PRE_CSC_C11_C12, CNVC_CFG, id), \
SRI(PRE_CSC_C33_C34, CNVC_CFG, id), \
SRI(PRE_CSC_B_C11_C12, CNVC_CFG, id), \
SRI(PRE_CSC_B_C33_C34, CNVC_CFG, id), \
SRI(CM_POST_CSC_CONTROL, CM, id), \
SRI(CM_POST_CSC_C11_C12, CM, id), \
SRI(CM_POST_CSC_C33_C34, CM, id), \
SRI(CM_POST_CSC_B_C11_C12, CM, id), \
SRI(CM_POST_CSC_B_C33_C34, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI(CM_CONTROL, CM, id), \
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
SRI(DPP_CONTROL, DPP_TOP, id), \
SRI(CM_HDR_MULT_COEF, CM, id), \
SRI(CURSOR_CONTROL, CURSOR0_, id), \
SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \
SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \
SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \
SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \
SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \
SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \
SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \
SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \
SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \
SRI(COLOR_KEYER_RED, CNVC_CFG, id), \
SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
SRI(CURSOR_CONTROL, CURSOR0_, id),\
SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
#define DPP_REG_LIST_DCN30(id)\
DPP_REG_LIST_DCN30_COMMON(id), \
TF_REG_LIST_DCN20_COMMON(id), \
SRI(CM_BLNDGAM_CONTROL, CM, id), \
SRI(CM_SHAPER_LUT_DATA, CM, id),\
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM, id),\
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM, id),\
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
#define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\
TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\
TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\
TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\
TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\
TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\
TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\
TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\
TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\
TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\
TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \
TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \
TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \
TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \
TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \
TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \
TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \
TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \
TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \
TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \
TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \
TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \
TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \
TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \
TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \
TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \
TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
#define DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)\
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_HOST_SEL, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_CONFIG_MODE, mask_sh), \
TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, mask_sh), \
TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, mask_sh)
#define DPP_REG_LIST_SH_MASK_DCN30(mask_sh)\
DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh), \
TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)
#define DPP_REG_FIELD_LIST_DCN3(type) \
TF_REG_FIELD_LIST_DCN2_0(type); \
type FORMAT_CROSSBAR_R; \
type FORMAT_CROSSBAR_G; \
type FORMAT_CROSSBAR_B; \
type CM_DEALPHA_EN;\
type CM_DEALPHA_ABLND;\
type CM_BIAS_Y_G;\
type CM_BIAS_CB_B;\
type CM_BIAS_CR_R;\
type GAMCOR_MEM_PWR_DIS; \
type GAMCOR_MEM_PWR_FORCE; \
type PRE_DEGAM_MODE;\
type PRE_DEGAM_SELECT;\
type CNVC_ALPHA_PLANE_ENABLE; \
type PRE_DEALPHA_EN; \
type PRE_DEALPHA_ABLND_EN; \
type PRE_REALPHA_EN; \
type PRE_REALPHA_ABLND_EN; \
type PRE_CSC_MODE; \
type PRE_CSC_MODE_CURRENT; \
type PRE_CSC_C11; \
type PRE_CSC_C12; \
type PRE_CSC_C33; \
type PRE_CSC_C34; \
type CM_POST_CSC_MODE; \
type CM_POST_CSC_MODE_CURRENT; \
type CM_POST_CSC_C11; \
type CM_POST_CSC_C12; \
type CM_POST_CSC_C33; \
type CM_POST_CSC_C34; \
type CM_GAMCOR_MODE; \
type CM_GAMCOR_SELECT; \
type CM_GAMCOR_PWL_DISABLE; \
type CM_GAMCOR_MODE_CURRENT; \
type CM_GAMCOR_SELECT_CURRENT; \
type CM_GAMCOR_LUT_INDEX; \
type CM_GAMCOR_LUT_DATA; \
type CM_GAMCOR_LUT_WRITE_COLOR_MASK; \
type CM_GAMCOR_LUT_READ_COLOR_SEL; \
type CM_GAMCOR_LUT_READ_DBG; \
type CM_GAMCOR_LUT_HOST_SEL; \
type CM_GAMCOR_LUT_CONFIG_MODE; \
type CM_GAMCOR_LUT_STATUS; \
type CM_GAMCOR_RAMA_EXP_REGION_START_B; \
type CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B; \
type CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; \
type CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; \
type CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; \
type CM_GAMCOR_RAMA_EXP_REGION_END_B; \
type CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; \
type CM_GAMCOR_RAMA_OFFSET_B; \
type CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; \
type CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; \
type CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; \
type CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;\
type CM_GAMUT_REMAP_MODE_CURRENT;\
type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B; \
type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G; \
type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R; \
type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; \
type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G; \
type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R; \
type CM_BLNDGAM_LUT_WRITE_COLOR_MASK; \
type CM_BLNDGAM_LUT_HOST_SEL; \
type CM_BLNDGAM_LUT_CONFIG_MODE; \
type CM_3DLUT_MODE_CURRENT; \
type CM_SHAPER_MODE_CURRENT; \
type CM_BLNDGAM_MODE; \
type CM_BLNDGAM_MODE_CURRENT; \
type CM_BLNDGAM_SELECT_CURRENT; \
type CM_BLNDGAM_SELECT; \
type GAMCOR_MEM_PWR_STATE
struct dcn3_dpp_shift {
DPP_REG_FIELD_LIST_DCN3(uint8_t);
};
struct dcn3_dpp_mask {
DPP_REG_FIELD_LIST_DCN3(uint32_t);
};
#define DPP_DCN3_REG_VARIABLE_LIST_COMMON \
DPP_DCN2_REG_VARIABLE_LIST; \
uint32_t CM_MEM_PWR_STATUS;\
uint32_t CM_DEALPHA;\
uint32_t CM_BIAS_CR_R;\
uint32_t CM_BIAS_Y_G_CB_B;\
uint32_t PRE_DEGAM;\
uint32_t PRE_DEALPHA; \
uint32_t PRE_REALPHA; \
uint32_t PRE_CSC_MODE; \
uint32_t PRE_CSC_C11_C12; \
uint32_t PRE_CSC_C33_C34; \
uint32_t PRE_CSC_B_C11_C12; \
uint32_t PRE_CSC_B_C33_C34; \
uint32_t CM_POST_CSC_CONTROL; \
uint32_t CM_POST_CSC_C11_C12; \
uint32_t CM_POST_CSC_C33_C34; \
uint32_t CM_POST_CSC_B_C11_C12; \
uint32_t CM_POST_CSC_B_C33_C34; \
uint32_t CM_GAMUT_REMAP_B_C11_C12; \
uint32_t CM_GAMUT_REMAP_B_C13_C14; \
uint32_t CM_GAMUT_REMAP_B_C21_C22; \
uint32_t CM_GAMUT_REMAP_B_C23_C24; \
uint32_t CM_GAMUT_REMAP_B_C31_C32; \
uint32_t CM_GAMUT_REMAP_B_C33_C34; \
uint32_t CM_GAMCOR_CONTROL; \
uint32_t CM_GAMCOR_LUT_CONTROL; \
uint32_t CM_GAMCOR_LUT_INDEX; \
uint32_t CM_GAMCOR_LUT_DATA; \
uint32_t CM_GAMCOR_RAMB_START_CNTL_B; \
uint32_t CM_GAMCOR_RAMB_START_CNTL_G; \
uint32_t CM_GAMCOR_RAMB_START_CNTL_R; \
uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_B; \
uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_G; \
uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_R; \
uint32_t CM_GAMCOR_RAMB_END_CNTL1_B; \
uint32_t CM_GAMCOR_RAMB_END_CNTL2_B; \
uint32_t CM_GAMCOR_RAMB_END_CNTL1_G; \
uint32_t CM_GAMCOR_RAMB_END_CNTL2_G; \
uint32_t CM_GAMCOR_RAMB_END_CNTL1_R; \
uint32_t CM_GAMCOR_RAMB_END_CNTL2_R; \
uint32_t CM_GAMCOR_RAMB_REGION_0_1; \
uint32_t CM_GAMCOR_RAMB_REGION_32_33; \
uint32_t CM_GAMCOR_RAMB_OFFSET_B; \
uint32_t CM_GAMCOR_RAMB_OFFSET_G; \
uint32_t CM_GAMCOR_RAMB_OFFSET_R; \
uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_B; \
uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_G; \
uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_R; \
uint32_t CM_GAMCOR_RAMA_START_CNTL_B; \
uint32_t CM_GAMCOR_RAMA_START_CNTL_G; \
uint32_t CM_GAMCOR_RAMA_START_CNTL_R; \
uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_B; \
uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_G; \
uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_R; \
uint32_t CM_GAMCOR_RAMA_END_CNTL1_B; \
uint32_t CM_GAMCOR_RAMA_END_CNTL2_B; \
uint32_t CM_GAMCOR_RAMA_END_CNTL1_G; \
uint32_t CM_GAMCOR_RAMA_END_CNTL2_G; \
uint32_t CM_GAMCOR_RAMA_END_CNTL1_R; \
uint32_t CM_GAMCOR_RAMA_END_CNTL2_R; \
uint32_t CM_GAMCOR_RAMA_REGION_0_1; \
uint32_t CM_GAMCOR_RAMA_REGION_32_33; \
uint32_t CM_GAMCOR_RAMA_OFFSET_B; \
uint32_t CM_GAMCOR_RAMA_OFFSET_G; \
uint32_t CM_GAMCOR_RAMA_OFFSET_R; \
uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_B; \
uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_G; \
uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_R; \
uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B; \
uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G; \
uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R; \
uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B; \
uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G; \
uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R; \
uint32_t CM_BLNDGAM_LUT_CONTROL
struct dcn3_dpp_registers {
DPP_DCN3_REG_VARIABLE_LIST_COMMON;
};
struct dcn3_dpp {
struct dpp base;
const struct dcn3_dpp_registers *tf_regs;
const struct dcn3_dpp_shift *tf_shift;
const struct dcn3_dpp_mask *tf_mask;
const uint16_t *filter_v;
const uint16_t *filter_h;
const uint16_t *filter_v_c;
const uint16_t *filter_h_c;
int lb_pixel_depth_supported;
int lb_memory_size;
int lb_bits_per_entry;
bool is_write_to_ram_a_safe;
struct scaler_data scl_data;
struct pwl_params pwl_data;
};
bool dpp3_construct(struct dcn3_dpp *dpp3,
struct dc_context *ctx,
uint32_t inst,
const struct dcn3_dpp_registers *tf_regs,
const struct dcn3_dpp_shift *tf_shift,
const struct dcn3_dpp_mask *tf_mask);
bool dpp3_program_gamcor_lut(
struct dpp *dpp_base, const struct pwl_params *params);
void dpp3_program_CM_dealpha(
struct dpp *dpp_base,
uint32_t enable, uint32_t additive_blending);
void dpp3_program_CM_bias(
struct dpp *dpp_base,
struct CM_bias_params *bias_params);
void dpp3_set_hdr_multiplier(
struct dpp *dpp_base,
uint32_t multiplier);
void dpp3_cm_set_gamut_remap(
struct dpp *dpp_base,
const struct dpp_grph_csc_adjustment *adjust);
void dpp3_set_pre_degam(struct dpp *dpp_base,
uint32_t degamma_lut_selection);
void dpp3_set_cursor_attributes(
struct dpp *dpp_base,
struct dc_cursor_attributes *cursor_attributes);
void dpp3_program_post_csc(
struct dpp *dpp_base,
enum dc_color_space color_space,
enum dcn10_input_csc_select input_select,
const struct out_csc_color_matrix *tbl_entry);
void dpp3_program_cm_bias(
struct dpp *dpp_base,
struct CM_bias_params *bias_params);
void dpp3_program_cm_dealpha(
struct dpp *dpp_base,
uint32_t enable, uint32_t additive_blending);
#endif /* __DC_HWSS_DCN30_H__ */

410
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c Normal file
View File

@ -0,0 +1,410 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "core_types.h"
#include "reg_helper.h"
#include "dcn30_dpp.h"
#include "basics/conversion.h"
#include "dcn30_cm_common.h"
#define REG(reg)\
dpp->tf_regs->reg
#define CTX \
dpp->base.ctx
#undef FN
#define FN(reg_name, field_name) \
dpp->tf_shift->field_name, dpp->tf_mask->field_name
static void dpp3_enable_cm_block(
struct dpp *dpp_base)
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
unsigned int cm_bypass_mode = 0;
// debug option: put CM in bypass mode
if (dpp_base->ctx->dc->debug.cm_in_bypass)
cm_bypass_mode = 1;
REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);
}
static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base)
{
enum dc_lut_mode mode;
uint32_t state_mode;
uint32_t lut_mode;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_GET(CM_GAMCOR_CONTROL,
CM_GAMCOR_MODE_CURRENT, &state_mode);
if (state_mode == 0)
mode = LUT_BYPASS;
if (state_mode == 2) {//Programmable RAM LUT
REG_GET(CM_GAMCOR_CONTROL,
CM_GAMCOR_SELECT_CURRENT, &lut_mode);
if (lut_mode == 0)
mode = LUT_RAM_A;
else
mode = LUT_RAM_B;
}
return mode;
}
static void dpp3_program_gammcor_lut(
struct dpp *dpp_base,
const struct pwl_result_data *rgb,
uint32_t num,
bool is_ram_a)
{
uint32_t i;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
/*fill in the LUT with all base values to be used by pwl module
* HW auto increments the LUT index: back-to-back write
*/
if (is_rgb_equal(rgb, num)) {
for (i = 0 ; i < num; i++)
REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);
REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);
} else {
REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
CM_GAMCOR_LUT_WRITE_COLOR_MASK, 4);
for (i = 0 ; i < num; i++)
REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);
REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);
REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
CM_GAMCOR_LUT_WRITE_COLOR_MASK, 2);
for (i = 0 ; i < num; i++)
REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg);
REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green);
REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
CM_GAMCOR_LUT_WRITE_COLOR_MASK, 1);
for (i = 0 ; i < num; i++)
REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg);
REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_blue);
}
}
static void dpp3_power_on_gamcor_lut(
struct dpp *dpp_base,
bool power_on)
{
uint32_t power_status;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_SET(CM_MEM_PWR_CTRL, 0,
GAMCOR_MEM_PWR_DIS, power_on == true ? 0:1);
REG_GET(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, &power_status);
if (power_status != 0)
BREAK_TO_DEBUGGER();
}
void dpp3_program_cm_dealpha(
struct dpp *dpp_base,
uint32_t enable, uint32_t additive_blending)
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_SET_2(CM_DEALPHA, 0,
CM_DEALPHA_EN, enable,
CM_DEALPHA_ABLND, additive_blending);
}
void dpp3_program_cm_bias(
struct dpp *dpp_base,
struct CM_bias_params *bias_params)
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_SET(CM_BIAS_CR_R, 0, CM_BIAS_CR_R, bias_params->cm_bias_cr_r);
REG_SET_2(CM_BIAS_Y_G_CB_B, 0,
CM_BIAS_Y_G, bias_params->cm_bias_y_g,
CM_BIAS_CB_B, bias_params->cm_bias_cb_b);
}
static void dpp3_gamcor_reg_field(
struct dcn3_dpp *dpp,
struct dcn3_xfer_func_reg *reg)
{
reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B;
reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B;
reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B;
reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B;
reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;
reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;
reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B;
reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B;
reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;
}
static void dpp3_configure_gamcor_lut(
struct dpp *dpp_base,
bool is_ram_a)
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
CM_GAMCOR_LUT_WRITE_COLOR_MASK, 7);
REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
CM_GAMCOR_LUT_HOST_SEL, is_ram_a == true ? 0:1);
REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
}
bool dpp3_program_gamcor_lut(
struct dpp *dpp_base, const struct pwl_params *params)
{
enum dc_lut_mode current_mode;
enum dc_lut_mode next_mode;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
struct dcn3_xfer_func_reg gam_regs;
dpp3_enable_cm_block(dpp_base);
if (params == NULL) { //bypass if we have no pwl data
REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 0);
return false;
}
dpp3_power_on_gamcor_lut(dpp_base, true);
REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 2);
current_mode = dpp30_get_gamcor_current(dpp_base);
if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
next_mode = LUT_RAM_B;
else
next_mode = LUT_RAM_A;
dpp3_power_on_gamcor_lut(dpp_base, true);
dpp3_configure_gamcor_lut(dpp_base, next_mode == LUT_RAM_A ? true:false);
if (next_mode == LUT_RAM_B) {
gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B);
gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G);
gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R);
gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B);
gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G);
gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R);
gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B);
gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B);
gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G);
gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMB_END_CNTL2_G);
gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMB_END_CNTL1_R);
gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMB_END_CNTL2_R);
gam_regs.region_start = REG(CM_GAMCOR_RAMB_REGION_0_1);
gam_regs.region_end = REG(CM_GAMCOR_RAMB_REGION_32_33);
//New registers in DCN3AG/DCN GAMCOR block
gam_regs.offset_b = REG(CM_GAMCOR_RAMB_OFFSET_B);
gam_regs.offset_g = REG(CM_GAMCOR_RAMB_OFFSET_G);
gam_regs.offset_r = REG(CM_GAMCOR_RAMB_OFFSET_R);
gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_B);
gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_G);
gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_R);
} else {
gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMA_START_CNTL_B);
gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMA_START_CNTL_G);
gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMA_START_CNTL_R);
gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B);
gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G);
gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R);
gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMA_END_CNTL1_B);
gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMA_END_CNTL2_B);
gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMA_END_CNTL1_G);
gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMA_END_CNTL2_G);
gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMA_END_CNTL1_R);
gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMA_END_CNTL2_R);
gam_regs.region_start = REG(CM_GAMCOR_RAMA_REGION_0_1);
gam_regs.region_end = REG(CM_GAMCOR_RAMA_REGION_32_33);
//New registers in DCN3AG/DCN GAMCOR block
gam_regs.offset_b = REG(CM_GAMCOR_RAMA_OFFSET_B);
gam_regs.offset_g = REG(CM_GAMCOR_RAMA_OFFSET_G);
gam_regs.offset_r = REG(CM_GAMCOR_RAMA_OFFSET_R);
gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_B);
gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_G);
gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_R);
}
//get register fields
dpp3_gamcor_reg_field(dpp, &gam_regs);
//program register set for LUTA/LUTB
cm_helper_program_gamcor_xfer_func(dpp_base->ctx, params, &gam_regs);
dpp3_program_gammcor_lut(dpp_base, params->rgb_resulted, params->hw_points_num,
next_mode == LUT_RAM_A ? true:false);
//select Gamma LUT to use for next frame
REG_UPDATE(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, next_mode == LUT_RAM_A ? 0:1);
return true;
}
void dpp3_set_hdr_multiplier(
struct dpp *dpp_base,
uint32_t multiplier)
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);
}
static void program_gamut_remap(
struct dcn3_dpp *dpp,
const uint16_t *regval,
int select)
{
uint16_t selection = 0;
struct color_matrices_reg gam_regs;
if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
CM_GAMUT_REMAP_MODE, 0);
return;
}
switch (select) {
case GAMUT_REMAP_COEFF:
selection = 1;
break;
/*this corresponds to GAMUT_REMAP coefficients set B
*we don't have common coefficient sets in dcn3ag/dcn3
*/
case GAMUT_REMAP_COMA_COEFF:
selection = 2;
break;
default:
break;
}
gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
if (select == GAMUT_REMAP_COEFF) {
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
cm_helper_program_color_matrices(
dpp->base.ctx,
regval,
&gam_regs);
} else if (select == GAMUT_REMAP_COMA_COEFF) {
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
cm_helper_program_color_matrices(
dpp->base.ctx,
regval,
&gam_regs);
}
//select coefficient set to use
REG_SET(
CM_GAMUT_REMAP_CONTROL, 0,
CM_GAMUT_REMAP_MODE, selection);
}
void dpp3_cm_set_gamut_remap(
struct dpp *dpp_base,
const struct dpp_grph_csc_adjustment *adjust)
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
int i = 0;
int gamut_mode;
if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
/* Bypass if type is bypass or hw */
program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);
else {
struct fixed31_32 arr_matrix[12];
uint16_t arr_reg_val[12];
for (i = 0; i < 12; i++)
arr_matrix[i] = adjust->temperature_matrix[i];
convert_float_matrix(
arr_reg_val, arr_matrix, 12);
//current coefficient set in use
REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &gamut_mode);
if (gamut_mode == 0)
gamut_mode = 1; //use coefficient set A
else if (gamut_mode == 1)
gamut_mode = 2;
else
gamut_mode = 1;
//follow dcn2 approach for now - using only coefficient set A
program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);
}
}

7
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
View File

@ -121,6 +121,13 @@ struct CM_bias_params {
};
struct dpp_funcs {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool (*dpp_program_gamcor_lut)(
struct dpp *dpp_base, const struct pwl_params *params);
void (*dpp_set_pre_degam)(struct dpp *dpp_base,
enum dc_transfer_func_predefined tr);
#endif
void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
uint32_t enable, uint32_t additive_blending);