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Merge branch 'remove-virt_to_bus-drivers'

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Jakub Kicinski says:

====================
net: remove non-Ethernet drivers using virt_to_bus()

Networking is currently the main offender in using virt_to_bus().
Frankly all the drivers which use it are super old and unlikely
to be used today. They are just an ongoing maintenance burden.

In other words this series is using virt_to_bus() as an excuse
to shed some old stuff. Having done the tree-wide dev_addr_set()
conversion recently I have limited sympathy for carrying dead
code.

Obviously please scream if any of these drivers _is_ in fact
still being used. Otherwise let's take the chance, we can always
apologize and revert if users show up later.

Also I should say thanks to everyone who contributed to this code!
The work continues to be appreciated although realistically in more
of a "history book" fashion...
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2022-04-27 12:22:56 +01:00
commit 03fa8fc93e
30 changed files with 1 additions and 15143 deletions
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2
Documentation/admin-guide/devices.txt
View File

@ -1933,7 +1933,7 @@
...
255= /dev/umem/d15p15 15th partition of 16th board.
117 char COSA/SRP synchronous serial card
117 char [REMOVED] COSA/SRP synchronous serial card
0 = /dev/cosa0c0 1st board, 1st channel
1 = /dev/cosa0c1 1st board, 2nd channel
...

1
Documentation/networking/device_drivers/index.rst
View File

@ -17,7 +17,6 @@ Contents:
fddi/index
hamradio/index
qlogic/index
wan/index
wifi/index
wwan/index

18
Documentation/networking/device_drivers/wan/index.rst
View File

@ -1,18 +0,0 @@
.. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Classic WAN Device Drivers
==========================
Contents:
.. toctree::
:maxdepth: 2
z8530book
.. only:: subproject and html
Indices
=======
* :ref:`genindex`

256
Documentation/networking/device_drivers/wan/z8530book.rst
View File

@ -1,256 +0,0 @@
=======================
Z8530 Programming Guide
=======================
:Author: Alan Cox
Introduction
============
The Z85x30 family synchronous/asynchronous controller chips are used on
a large number of cheap network interface cards. The kernel provides a
core interface layer that is designed to make it easy to provide WAN
services using this chip.
The current driver only support synchronous operation. Merging the
asynchronous driver support into this code to allow any Z85x30 device to
be used as both a tty interface and as a synchronous controller is a
project for Linux post the 2.4 release
Driver Modes
============
The Z85230 driver layer can drive Z8530, Z85C30 and Z85230 devices in
three different modes. Each mode can be applied to an individual channel
on the chip (each chip has two channels).
The PIO synchronous mode supports the most common Z8530 wiring. Here the
chip is interface to the I/O and interrupt facilities of the host
machine but not to the DMA subsystem. When running PIO the Z8530 has
extremely tight timing requirements. Doing high speeds, even with a
Z85230 will be tricky. Typically you should expect to achieve at best
9600 baud with a Z8C530 and 64Kbits with a Z85230.
The DMA mode supports the chip when it is configured to use dual DMA
channels on an ISA bus. The better cards tend to support this mode of
operation for a single channel. With DMA running the Z85230 tops out
when it starts to hit ISA DMA constraints at about 512Kbits. It is worth
noting here that many PC machines hang or crash when the chip is driven
fast enough to hold the ISA bus solid.
Transmit DMA mode uses a single DMA channel. The DMA channel is used for
transmission as the transmit FIFO is smaller than the receive FIFO. it
gives better performance than pure PIO mode but is nowhere near as ideal
as pure DMA mode.
Using the Z85230 driver
=======================
The Z85230 driver provides the back end interface to your board. To
configure a Z8530 interface you need to detect the board and to identify
its ports and interrupt resources. It is also your problem to verify the
resources are available.
Having identified the chip you need to fill in a struct z8530_dev,
which describes each chip. This object must exist until you finally
shutdown the board. Firstly zero the active field. This ensures nothing
goes off without you intending it. The irq field should be set to the
interrupt number of the chip. (Each chip has a single interrupt source
rather than each channel). You are responsible for allocating the
interrupt line. The interrupt handler should be set to
:c:func:`z8530_interrupt()`. The device id should be set to the
z8530_dev structure pointer. Whether the interrupt can be shared or not
is board dependent, and up to you to initialise.
The structure holds two channel structures. Initialise chanA.ctrlio and
chanA.dataio with the address of the control and data ports. You can or
this with Z8530_PORT_SLEEP to indicate your interface needs the 5uS
delay for chip settling done in software. The PORT_SLEEP option is
architecture specific. Other flags may become available on future
platforms, eg for MMIO. Initialise the chanA.irqs to &z8530_nop to
start the chip up as disabled and discarding interrupt events. This
ensures that stray interrupts will be mopped up and not hang the bus.
Set chanA.dev to point to the device structure itself. The private and
name field you may use as you wish. The private field is unused by the
Z85230 layer. The name is used for error reporting and it may thus make
sense to make it match the network name.
Repeat the same operation with the B channel if your chip has both
channels wired to something useful. This isn't always the case. If it is
not wired then the I/O values do not matter, but you must initialise
chanB.dev.
If your board has DMA facilities then initialise the txdma and rxdma
fields for the relevant channels. You must also allocate the ISA DMA
channels and do any necessary board level initialisation to configure
them. The low level driver will do the Z8530 and DMA controller
programming but not board specific magic.
Having initialised the device you can then call
:c:func:`z8530_init()`. This will probe the chip and reset it into
a known state. An identification sequence is then run to identify the
chip type. If the checks fail to pass the function returns a non zero
error code. Typically this indicates that the port given is not valid.
After this call the type field of the z8530_dev structure is
initialised to either Z8530, Z85C30 or Z85230 according to the chip
found.
Once you have called z8530_init you can also make use of the utility
function :c:func:`z8530_describe()`. This provides a consistent
reporting format for the Z8530 devices, and allows all the drivers to
provide consistent reporting.
Attaching Network Interfaces
============================
If you wish to use the network interface facilities of the driver, then
you need to attach a network device to each channel that is present and
in use. In addition to use the generic HDLC you need to follow some
additional plumbing rules. They may seem complex but a look at the
example hostess_sv11 driver should reassure you.
The network device used for each channel should be pointed to by the
netdevice field of each channel. The hdlc-> priv field of the network
device points to your private data - you will need to be able to find
your private data from this.
The way most drivers approach this particular problem is to create a
structure holding the Z8530 device definition and put that into the
private field of the network device. The network device fields of the
channels then point back to the network devices.
If you wish to use the generic HDLC then you need to register the HDLC
device.
Before you register your network device you will also need to provide
suitable handlers for most of the network device callbacks. See the
network device documentation for more details on this.
Configuring And Activating The Port
===================================
The Z85230 driver provides helper functions and tables to load the port
registers on the Z8530 chips. When programming the register settings for
a channel be aware that the documentation recommends initialisation
orders. Strange things happen when these are not followed.
:c:func:`z8530_channel_load()` takes an array of pairs of
initialisation values in an array of u8 type. The first value is the
Z8530 register number. Add 16 to indicate the alternate register bank on
the later chips. The array is terminated by a 255.
The driver provides a pair of public tables. The z8530_hdlc_kilostream
table is for the UK 'Kilostream' service and also happens to cover most
other end host configurations. The z8530_hdlc_kilostream_85230 table
is the same configuration using the enhancements of the 85230 chip. The
configuration loaded is standard NRZ encoded synchronous data with HDLC
bitstuffing. All of the timing is taken from the other end of the link.
When writing your own tables be aware that the driver internally tracks
register values. It may need to reload values. You should therefore be
sure to set registers 1-7, 9-11, 14 and 15 in all configurations. Where
the register settings depend on DMA selection the driver will update the
bits itself when you open or close. Loading a new table with the
interface open is not recommended.
There are three standard configurations supported by the core code. In
PIO mode the interface is programmed up to use interrupt driven PIO.
This places high demands on the host processor to avoid latency. The
driver is written to take account of latency issues but it cannot avoid
latencies caused by other drivers, notably IDE in PIO mode. Because the
drivers allocate buffers you must also prevent MTU changes while the
port is open.
Once the port is open it will call the rx_function of each channel
whenever a completed packet arrived. This is invoked from interrupt
context and passes you the channel and a network buffer (struct
sk_buff) holding the data. The data includes the CRC bytes so most
users will want to trim the last two bytes before processing the data.
This function is very timing critical. When you wish to simply discard
data the support code provides the function
:c:func:`z8530_null_rx()` to discard the data.
To active PIO mode sending and receiving the ``z8530_sync_open`` is called.
This expects to be passed the network device and the channel. Typically
this is called from your network device open callback. On a failure a
non zero error status is returned.
The :c:func:`z8530_sync_close()` function shuts down a PIO
channel. This must be done before the channel is opened again and before
the driver shuts down and unloads.
The ideal mode of operation is dual channel DMA mode. Here the kernel
driver will configure the board for DMA in both directions. The driver
also handles ISA DMA issues such as controller programming and the
memory range limit for you. This mode is activated by calling the
:c:func:`z8530_sync_dma_open()` function. On failure a non zero
error value is returned. Once this mode is activated it can be shut down
by calling the :c:func:`z8530_sync_dma_close()`. You must call
the close function matching the open mode you used.
The final supported mode uses a single DMA channel to drive the transmit
side. As the Z85C30 has a larger FIFO on the receive channel this tends
to increase the maximum speed a little. This is activated by calling the
``z8530_sync_txdma_open``. This returns a non zero error code on failure. The
:c:func:`z8530_sync_txdma_close()` function closes down the Z8530
interface from this mode.
Network Layer Functions
=======================
The Z8530 layer provides functions to queue packets for transmission.
The driver internally buffers the frame currently being transmitted and
one further frame (in order to keep back to back transmission running).
Any further buffering is up to the caller.
The function :c:func:`z8530_queue_xmit()` takes a network buffer
in sk_buff format and queues it for transmission. The caller must
provide the entire packet with the exception of the bitstuffing and CRC.
This is normally done by the caller via the generic HDLC interface
layer. It returns 0 if the buffer has been queued and non zero values
for queue full. If the function accepts the buffer it becomes property
of the Z8530 layer and the caller should not free it.
The function :c:func:`z8530_get_stats()` returns a pointer to an
internally maintained per interface statistics block. This provides most
of the interface code needed to implement the network layer get_stats
callback.
Porting The Z8530 Driver
========================
The Z8530 driver is written to be portable. In DMA mode it makes
assumptions about the use of ISA DMA. These are probably warranted in
most cases as the Z85230 in particular was designed to glue to PC type
machines. The PIO mode makes no real assumptions.
Should you need to retarget the Z8530 driver to another architecture the
only code that should need changing are the port I/O functions. At the
moment these assume PC I/O port accesses. This may not be appropriate
for all platforms. Replacing :c:func:`z8530_read_port()` and
``z8530_write_port`` is intended to be all that is required to port
this driver layer.
Known Bugs And Assumptions
==========================
Interrupt Locking
The locking in the driver is done via the global cli/sti lock. This
makes for relatively poor SMP performance. Switching this to use a
per device spin lock would probably materially improve performance.
Occasional Failures
We have reports of occasional failures when run for very long
periods of time and the driver starts to receive junk frames. At the
moment the cause of this is not clear.
Public Functions Provided
=========================
.. kernel-doc:: drivers/net/wan/z85230.c
:export:
Internal Functions
==================
.. kernel-doc:: drivers/net/wan/z85230.c
:internal:

7
MAINTAINERS
View File

@ -5047,12 +5047,6 @@ S: Maintained
F: Documentation/hwmon/corsair-psu.rst
F: drivers/hwmon/corsair-psu.c
COSA/SRP SYNC SERIAL DRIVER
M: Jan "Yenya" Kasprzak <kas@fi.muni.cz>
S: Maintained
W: http://www.fi.muni.cz/~kas/cosa/
F: drivers/net/wan/cosa*
COUNTER SUBSYSTEM
M: William Breathitt Gray <vilhelm.gray@gmail.com>
L: linux-iio@vger.kernel.org
@ -8772,7 +8766,6 @@ F: kernel/time/timer_*.c
HIGH-SPEED SCC DRIVER FOR AX.25
L: linux-hams@vger.kernel.org
S: Orphan
F: drivers/net/hamradio/dmascc.c
F: drivers/net/hamradio/scc.c
HIGHPOINT ROCKETRAID 3xxx RAID DRIVER

3
arch/mips/configs/gpr_defconfig
View File

@ -178,11 +178,8 @@ CONFIG_NETCONSOLE=m
CONFIG_ATM_TCP=m
CONFIG_ATM_LANAI=m
CONFIG_ATM_ENI=m
CONFIG_ATM_FIRESTREAM=m
CONFIG_ATM_ZATM=m
CONFIG_ATM_NICSTAR=m
CONFIG_ATM_IDT77252=m
CONFIG_ATM_HORIZON=m
CONFIG_ATM_IA=m
CONFIG_ATM_FORE200E=m
CONFIG_ATM_HE=m

3
arch/mips/configs/mtx1_defconfig
View File

@ -255,11 +255,8 @@ CONFIG_ARCNET_COM20020_CS=m
CONFIG_ATM_TCP=m
CONFIG_ATM_LANAI=m
CONFIG_ATM_ENI=m
CONFIG_ATM_FIRESTREAM=m
CONFIG_ATM_ZATM=m
CONFIG_ATM_NICSTAR=m
CONFIG_ATM_IDT77252=m
CONFIG_ATM_HORIZON=m
CONFIG_ATM_IA=m
CONFIG_ATM_FORE200E=m
CONFIG_ATM_HE=m

54
drivers/atm/Kconfig
View File

@ -146,36 +146,6 @@ config ATM_ENI_BURST_RX_2W
try this if you have disabled 4W and 8W bursts. Enabling 2W if 4W or
8W are also set may or may not improve throughput.
config ATM_FIRESTREAM
tristate "Fujitsu FireStream (FS50/FS155) "
depends on PCI && VIRT_TO_BUS
help
Driver for the Fujitsu FireStream 155 (MB86697) and
FireStream 50 (MB86695) ATM PCI chips.
To compile this driver as a module, choose M here: the module will
be called firestream.
config ATM_ZATM
tristate "ZeitNet ZN1221/ZN1225"
depends on PCI && VIRT_TO_BUS
help
Driver for the ZeitNet ZN1221 (MMF) and ZN1225 (UTP-5) 155 Mbps ATM
adapters.
To compile this driver as a module, choose M here: the module will
be called zatm.
config ATM_ZATM_DEBUG
bool "Enable extended debugging"
depends on ATM_ZATM
help
Extended debugging records various events and displays that list
when an inconsistency is detected. This mechanism is faster than
generally using printks, but still has some impact on performance.
Note that extended debugging may create certain race conditions
itself. Enable this ONLY if you suspect problems with the driver.
config ATM_NICSTAR
tristate "IDT 77201 (NICStAR) (ForeRunnerLE)"
depends on PCI
@ -244,30 +214,6 @@ config ATM_IDT77252_USE_SUNI
depends on ATM_IDT77252
default y
config ATM_HORIZON
tristate "Madge Horizon [Ultra] (Collage PCI 25 and Collage PCI 155 Client)"
depends on PCI && VIRT_TO_BUS
help
This is a driver for the Horizon chipset ATM adapter cards once
produced by Madge Networks Ltd. Say Y (or M to compile as a module
named horizon) here if you have one of these cards.
config ATM_HORIZON_DEBUG
bool "Enable debugging messages"
depends on ATM_HORIZON
help
Somewhat useful debugging messages are available. The choice of
messages is controlled by a bitmap. This may be specified as a
module argument (kernel command line argument as well?), changed
dynamically using an ioctl (not yet) or changed by sending the
string "Dxxxx" to VCI 1023 (where x is a hex digit). See the file
<file:drivers/atm/horizon.h> for the meanings of the bits in the
mask.
When active, these messages can have a significant impact on the
speed of the driver, and the size of your syslog files! When
inactive, they will have only a modest impact on performance.
config ATM_IA
tristate "Interphase ATM PCI x575/x525/x531"
depends on PCI

3
drivers/atm/Makefile
View File

@ -5,9 +5,7 @@
fore_200e-y := fore200e.o
obj-$(CONFIG_ATM_ZATM) += zatm.o uPD98402.o
obj-$(CONFIG_ATM_NICSTAR) += nicstar.o
obj-$(CONFIG_ATM_HORIZON) += horizon.o
obj-$(CONFIG_ATM_IA) += iphase.o suni.o
obj-$(CONFIG_ATM_FORE200E) += fore_200e.o
obj-$(CONFIG_ATM_ENI) += eni.o suni.o
@ -26,7 +24,6 @@ endif
obj-$(CONFIG_ATM_DUMMY) += adummy.o
obj-$(CONFIG_ATM_TCP) += atmtcp.o
obj-$(CONFIG_ATM_FIRESTREAM) += firestream.o
obj-$(CONFIG_ATM_LANAI) += lanai.o
obj-$(CONFIG_ATM_HE) += he.o

2057
drivers/atm/firestream.c
View File

File diff suppressed because it is too large Load Diff

502
drivers/atm/firestream.h
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@ -1,502 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* drivers/atm/firestream.h - FireStream 155 (MB86697) and
* FireStream 50 (MB86695) device driver
*/
/* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
* Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
* and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
*/
/*
*/
/***********************************************************************
* first the defines for the chip. *
***********************************************************************/
/********************* General chip parameters. ************************/
#define FS_NR_FREE_POOLS 8
#define FS_NR_RX_QUEUES 4
/********************* queues and queue access macros ******************/
/* A queue entry. */
struct FS_QENTRY {
u32 cmd;
u32 p0, p1, p2;
};
/* A freepool entry. */
struct FS_BPENTRY {
u32 flags;
u32 next;
u32 bsa;
u32 aal_bufsize;
/* The hardware doesn't look at this, but we need the SKB somewhere... */
struct sk_buff *skb;
struct freepool *fp;
struct fs_dev *dev;
};
#define STATUS_CODE(qe) ((qe->cmd >> 22) & 0x3f)
/* OFFSETS against the base of a QUEUE... */
#define QSA 0x00
#define QEA 0x04
#define QRP 0x08
#define QWP 0x0c
#define QCNF 0x10 /* Only for Release queues! */
/* Not for the transmit pending queue. */
/* OFFSETS against the base of a FREE POOL... */
#define FPCNF 0x00
#define FPSA 0x04
#define FPEA 0x08
#define FPCNT 0x0c
#define FPCTU 0x10
#define Q_SA(b) (b + QSA )
#define Q_EA(b) (b + QEA )
#define Q_RP(b) (b + QRP )
#define Q_WP(b) (b + QWP )
#define Q_CNF(b) (b + QCNF)
#define FP_CNF(b) (b + FPCNF)
#define FP_SA(b) (b + FPSA)
#define FP_EA(b) (b + FPEA)
#define FP_CNT(b) (b + FPCNT)
#define FP_CTU(b) (b + FPCTU)
/* bits in a queue register. */
#define Q_FULL 0x1
#define Q_EMPTY 0x2
#define Q_INCWRAP 0x4
#define Q_ADDR_MASK 0xfffffff0
/* bits in a FreePool config register */
#define RBFP_RBS (0x1 << 16)
#define RBFP_RBSVAL (0x1 << 15)
#define RBFP_CME (0x1 << 12)
#define RBFP_DLP (0x1 << 11)
#define RBFP_BFPWT (0x1 << 0)
/* FireStream commands. */
#define QE_CMD_NULL (0x00 << 22)
#define QE_CMD_REG_RD (0x01 << 22)
#define QE_CMD_REG_RDM (0x02 << 22)
#define QE_CMD_REG_WR (0x03 << 22)
#define QE_CMD_REG_WRM (0x04 << 22)
#define QE_CMD_CONFIG_TX (0x05 << 22)
#define QE_CMD_CONFIG_RX (0x06 << 22)
#define QE_CMD_PRP_RD (0x07 << 22)
#define QE_CMD_PRP_RDM (0x2a << 22)
#define QE_CMD_PRP_WR (0x09 << 22)
#define QE_CMD_PRP_WRM (0x2b << 22)
#define QE_CMD_RX_EN (0x0a << 22)
#define QE_CMD_RX_PURGE (0x0b << 22)
#define QE_CMD_RX_PURGE_INH (0x0c << 22)
#define QE_CMD_TX_EN (0x0d << 22)
#define QE_CMD_TX_PURGE (0x0e << 22)
#define QE_CMD_TX_PURGE_INH (0x0f << 22)
#define QE_CMD_RST_CG (0x10 << 22)
#define QE_CMD_SET_CG (0x11 << 22)
#define QE_CMD_RST_CLP (0x12 << 22)
#define QE_CMD_SET_CLP (0x13 << 22)
#define QE_CMD_OVERRIDE (0x14 << 22)
#define QE_CMD_ADD_BFP (0x15 << 22)
#define QE_CMD_DUMP_TX (0x16 << 22)
#define QE_CMD_DUMP_RX (0x17 << 22)
#define QE_CMD_LRAM_RD (0x18 << 22)
#define QE_CMD_LRAM_RDM (0x28 << 22)
#define QE_CMD_LRAM_WR (0x19 << 22)
#define QE_CMD_LRAM_WRM (0x29 << 22)
#define QE_CMD_LRAM_BSET (0x1a << 22)
#define QE_CMD_LRAM_BCLR (0x1b << 22)
#define QE_CMD_CONFIG_SEGM (0x1c << 22)
#define QE_CMD_READ_SEGM (0x1d << 22)
#define QE_CMD_CONFIG_ROUT (0x1e << 22)
#define QE_CMD_READ_ROUT (0x1f << 22)
#define QE_CMD_CONFIG_TM (0x20 << 22)
#define QE_CMD_READ_TM (0x21 << 22)
#define QE_CMD_CONFIG_TXBM (0x22 << 22)
#define QE_CMD_READ_TXBM (0x23 << 22)
#define QE_CMD_CONFIG_RXBM (0x24 << 22)
#define QE_CMD_READ_RXBM (0x25 << 22)
#define QE_CMD_CONFIG_REAS (0x26 << 22)
#define QE_CMD_READ_REAS (0x27 << 22)
#define QE_TRANSMIT_DE (0x0 << 30)
#define QE_CMD_LINKED (0x1 << 30)
#define QE_CMD_IMM (0x2 << 30)
#define QE_CMD_IMM_INQ (0x3 << 30)
#define TD_EPI (0x1 << 27)
#define TD_COMMAND (0x1 << 28)
#define TD_DATA (0x0 << 29)
#define TD_RM_CELL (0x1 << 29)
#define TD_OAM_CELL (0x2 << 29)
#define TD_OAM_CELL_SEGMENT (0x3 << 29)
#define TD_BPI (0x1 << 20)
#define FP_FLAGS_EPI (0x1 << 27)
#define TX_PQ(i) (0x00 + (i) * 0x10)
#define TXB_RQ (0x20)
#define ST_Q (0x48)
#define RXB_FP(i) (0x90 + (i) * 0x14)
#define RXB_RQ(i) (0x134 + (i) * 0x14)
#define TXQ_HP 0
#define TXQ_LP 1
/* Phew. You don't want to know how many revisions these simple queue
* address macros went through before I got them nice and compact as
* they are now. -- REW
*/
/* And now for something completely different:
* The rest of the registers... */
#define CMDR0 0x34
#define CMDR1 0x38
#define CMDR2 0x3c
#define CMDR3 0x40
#define SARMODE0 0x5c
#define SARMODE0_TXVCS_0 (0x0 << 0)
#define SARMODE0_TXVCS_1k (0x1 << 0)
#define SARMODE0_TXVCS_2k (0x2 << 0)
#define SARMODE0_TXVCS_4k (0x3 << 0)
#define SARMODE0_TXVCS_8k (0x4 << 0)
#define SARMODE0_TXVCS_16k (0x5 << 0)
#define SARMODE0_TXVCS_32k (0x6 << 0)
#define SARMODE0_TXVCS_64k (0x7 << 0)
#define SARMODE0_TXVCS_32 (0x8 << 0)
#define SARMODE0_ABRVCS_0 (0x0 << 4)
#define SARMODE0_ABRVCS_512 (0x1 << 4)
#define SARMODE0_ABRVCS_1k (0x2 << 4)
#define SARMODE0_ABRVCS_2k (0x3 << 4)
#define SARMODE0_ABRVCS_4k (0x4 << 4)
#define SARMODE0_ABRVCS_8k (0x5 << 4)
#define SARMODE0_ABRVCS_16k (0x6 << 4)
#define SARMODE0_ABRVCS_32k (0x7 << 4)
#define SARMODE0_ABRVCS_32 (0x9 << 4) /* The others are "8", this one really has to
be 9. Tell me you don't believe me. -- REW */
#define SARMODE0_RXVCS_0 (0x0 << 8)
#define SARMODE0_RXVCS_1k (0x1 << 8)
#define SARMODE0_RXVCS_2k (0x2 << 8)
#define SARMODE0_RXVCS_4k (0x3 << 8)
#define SARMODE0_RXVCS_8k (0x4 << 8)
#define SARMODE0_RXVCS_16k (0x5 << 8)
#define SARMODE0_RXVCS_32k (0x6 << 8)
#define SARMODE0_RXVCS_64k (0x7 << 8)
#define SARMODE0_RXVCS_32 (0x8 << 8)
#define SARMODE0_CALSUP_1 (0x0 << 12)
#define SARMODE0_CALSUP_2 (0x1 << 12)
#define SARMODE0_CALSUP_3 (0x2 << 12)
#define SARMODE0_CALSUP_4 (0x3 << 12)
#define SARMODE0_PRPWT_FS50_0 (0x0 << 14)
#define SARMODE0_PRPWT_FS50_2 (0x1 << 14)
#define SARMODE0_PRPWT_FS50_5 (0x2 << 14)
#define SARMODE0_PRPWT_FS50_11 (0x3 << 14)
#define SARMODE0_PRPWT_FS155_0 (0x0 << 14)
#define SARMODE0_PRPWT_FS155_1 (0x1 << 14)
#define SARMODE0_PRPWT_FS155_2 (0x2 << 14)
#define SARMODE0_PRPWT_FS155_3 (0x3 << 14)
#define SARMODE0_SRTS0 (0x1 << 23)
#define SARMODE0_SRTS1 (0x1 << 24)
#define SARMODE0_RUN (0x1 << 25)
#define SARMODE0_UNLOCK (0x1 << 26)
#define SARMODE0_CWRE (0x1 << 27)
#define SARMODE0_INTMODE_READCLEAR (0x0 << 28)
#define SARMODE0_INTMODE_READNOCLEAR (0x1 << 28)
#define SARMODE0_INTMODE_READNOCLEARINHIBIT (0x2 << 28)
#define SARMODE0_INTMODE_READCLEARINHIBIT (0x3 << 28) /* Tell me you don't believe me. */
#define SARMODE0_GINT (0x1 << 30)
#define SARMODE0_SHADEN (0x1 << 31)
#define SARMODE1 0x60
#define SARMODE1_TRTL_SHIFT 0 /* Program to 0 */
#define SARMODE1_RRTL_SHIFT 4 /* Program to 0 */
#define SARMODE1_TAGM (0x1 << 8) /* Program to 0 */
#define SARMODE1_HECM0 (0x1 << 9)
#define SARMODE1_HECM1 (0x1 << 10)
#define SARMODE1_HECM2 (0x1 << 11)
#define SARMODE1_GFCE (0x1 << 14)
#define SARMODE1_GFCR (0x1 << 15)
#define SARMODE1_PMS (0x1 << 18)
#define SARMODE1_GPRI (0x1 << 19)
#define SARMODE1_GPAS (0x1 << 20)
#define SARMODE1_GVAS (0x1 << 21)
#define SARMODE1_GNAM (0x1 << 22)
#define SARMODE1_GPLEN (0x1 << 23)
#define SARMODE1_DUMPE (0x1 << 24)
#define SARMODE1_OAMCRC (0x1 << 25)
#define SARMODE1_DCOAM (0x1 << 26)
#define SARMODE1_DCRM (0x1 << 27)
#define SARMODE1_TSTLP (0x1 << 28)
#define SARMODE1_DEFHEC (0x1 << 29)
#define ISR 0x64
#define IUSR 0x68
#define IMR 0x6c
#define ISR_LPCO (0x1 << 0)
#define ISR_DPCO (0x1 << 1)
#define ISR_RBRQ0_W (0x1 << 2)
#define ISR_RBRQ1_W (0x1 << 3)
#define ISR_RBRQ2_W (0x1 << 4)
#define ISR_RBRQ3_W (0x1 << 5)
#define ISR_RBRQ0_NF (0x1 << 6)
#define ISR_RBRQ1_NF (0x1 << 7)
#define ISR_RBRQ2_NF (0x1 << 8)
#define ISR_RBRQ3_NF (0x1 << 9)
#define ISR_BFP_SC (0x1 << 10)
#define ISR_INIT (0x1 << 11)
#define ISR_INIT_ERR (0x1 << 12) /* Documented as "reserved" */
#define ISR_USCEO (0x1 << 13)
#define ISR_UPEC0 (0x1 << 14)
#define ISR_VPFCO (0x1 << 15)
#define ISR_CRCCO (0x1 << 16)
#define ISR_HECO (0x1 << 17)
#define ISR_TBRQ_W (0x1 << 18)
#define ISR_TBRQ_NF (0x1 << 19)
#define ISR_CTPQ_E (0x1 << 20)
#define ISR_GFC_C0 (0x1 << 21)
#define ISR_PCI_FTL (0x1 << 22)
#define ISR_CSQ_W (0x1 << 23)
#define ISR_CSQ_NF (0x1 << 24)
#define ISR_EXT_INT (0x1 << 25)
#define ISR_RXDMA_S (0x1 << 26)
#define TMCONF 0x78
/* Bits? */
#define CALPRESCALE 0x7c
/* Bits? */
#define CELLOSCONF 0x84
#define CELLOSCONF_COTS (0x1 << 28)
#define CELLOSCONF_CEN (0x1 << 27)
#define CELLOSCONF_SC8 (0x3 << 24)
#define CELLOSCONF_SC4 (0x2 << 24)
#define CELLOSCONF_SC2 (0x1 << 24)
#define CELLOSCONF_SC1 (0x0 << 24)
#define CELLOSCONF_COBS (0x1 << 16)
#define CELLOSCONF_COPK (0x1 << 8)
#define CELLOSCONF_COST (0x1 << 0)
/* Bits? */
#define RAS0 0x1bc
#define RAS0_DCD_XHLT (0x1 << 31)
#define RAS0_VPSEL (0x1 << 16)
#define RAS0_VCSEL (0x1 << 0)
#define RAS1 0x1c0
#define RAS1_UTREG (0x1 << 5)
#define DMAMR 0x1cc
#define DMAMR_TX_MODE_FULL (0x0 << 0)
#define DMAMR_TX_MODE_PART (0x1 << 0)
#define DMAMR_TX_MODE_NONE (0x2 << 0) /* And 3 */
#define RAS2 0x280
#define RAS2_NNI (0x1 << 0)
#define RAS2_USEL (0x1 << 1)
#define RAS2_UBS (0x1 << 2)
struct fs_transmit_config {
u32 flags;
u32 atm_hdr;
u32 TMC[4];
u32 spec;
u32 rtag[3];
};
#define TC_FLAGS_AAL5 (0x0 << 29)
#define TC_FLAGS_TRANSPARENT_PAYLOAD (0x1 << 29)
#define TC_FLAGS_TRANSPARENT_CELL (0x2 << 29)
#define TC_FLAGS_STREAMING (0x1 << 28)
#define TC_FLAGS_PACKET (0x0)
#define TC_FLAGS_TYPE_ABR (0x0 << 22)
#define TC_FLAGS_TYPE_CBR (0x1 << 22)
#define TC_FLAGS_TYPE_VBR (0x2 << 22)
#define TC_FLAGS_TYPE_UBR (0x3 << 22)
#define TC_FLAGS_CAL0 (0x0 << 20)
#define TC_FLAGS_CAL1 (0x1 << 20)
#define TC_FLAGS_CAL2 (0x2 << 20)
#define TC_FLAGS_CAL3 (0x3 << 20)
#define RC_FLAGS_NAM (0x1 << 13)
#define RC_FLAGS_RXBM_PSB (0x0 << 14)
#define RC_FLAGS_RXBM_CIF (0x1 << 14)
#define RC_FLAGS_RXBM_PMB (0x2 << 14)
#define RC_FLAGS_RXBM_STR (0x4 << 14)
#define RC_FLAGS_RXBM_SAF (0x6 << 14)
#define RC_FLAGS_RXBM_POS (0x6 << 14)
#define RC_FLAGS_BFPS (0x1 << 17)
#define RC_FLAGS_BFPS_BFP (0x1 << 17)
#define RC_FLAGS_BFPS_BFP0 (0x0 << 17)
#define RC_FLAGS_BFPS_BFP1 (0x1 << 17)
#define RC_FLAGS_BFPS_BFP2 (0x2 << 17)
#define RC_FLAGS_BFPS_BFP3 (0x3 << 17)
#define RC_FLAGS_BFPS_BFP4 (0x4 << 17)
#define RC_FLAGS_BFPS_BFP5 (0x5 << 17)
#define RC_FLAGS_BFPS_BFP6 (0x6 << 17)
#define RC_FLAGS_BFPS_BFP7 (0x7 << 17)
#define RC_FLAGS_BFPS_BFP01 (0x8 << 17)
#define RC_FLAGS_BFPS_BFP23 (0x9 << 17)
#define RC_FLAGS_BFPS_BFP45 (0xa << 17)
#define RC_FLAGS_BFPS_BFP67 (0xb << 17)
#define RC_FLAGS_BFPS_BFP07 (0xc << 17)
#define RC_FLAGS_BFPS_BFP27 (0xd << 17)
#define RC_FLAGS_BFPS_BFP47 (0xe << 17)
#define RC_FLAGS_BFPP (0x1 << 21)
#define RC_FLAGS_TEVC (0x1 << 22)
#define RC_FLAGS_TEP (0x1 << 23)
#define RC_FLAGS_AAL5 (0x0 << 24)
#define RC_FLAGS_TRANSP (0x1 << 24)
#define RC_FLAGS_TRANSC (0x2 << 24)
#define RC_FLAGS_ML (0x1 << 27)
#define RC_FLAGS_TRBRM (0x1 << 28)
#define RC_FLAGS_PRI (0x1 << 29)
#define RC_FLAGS_HOAM (0x1 << 30)
#define RC_FLAGS_CRC10 (0x1 << 31)
#define RAC 0x1c8
#define RAM 0x1c4
/************************************************************************
* Then the datastructures that the DRIVER uses. *
************************************************************************/
#define TXQ_NENTRIES 32
#define RXRQ_NENTRIES 1024
struct fs_vcc {
int channo;
wait_queue_head_t close_wait;
struct sk_buff *last_skb;
};
struct queue {
struct FS_QENTRY *sa, *ea;
int offset;
};
struct freepool {
int offset;
int bufsize;
int nr_buffers;
int n;
};
struct fs_dev {
struct fs_dev *next; /* other FS devices */
int flags;
unsigned char irq; /* IRQ */
struct pci_dev *pci_dev; /* PCI stuff */
struct atm_dev *atm_dev;
struct timer_list timer;
unsigned long hw_base; /* mem base address */
void __iomem *base; /* Mapping of base address */
int channo;
unsigned long channel_mask;
struct queue hp_txq, lp_txq, tx_relq, st_q;
struct freepool rx_fp[FS_NR_FREE_POOLS];
struct queue rx_rq[FS_NR_RX_QUEUES];
int nchannels;
struct atm_vcc **atm_vccs;
void *tx_inuse;
int ntxpckts;
};
/* Number of channesl that the FS50 supports. */
#define FS50_CHANNEL_BITS 5
#define FS50_NR_CHANNELS (1 << FS50_CHANNEL_BITS)
#define FS_DEV(atm_dev) ((struct fs_dev *) (atm_dev)->dev_data)
#define FS_VCC(atm_vcc) ((struct fs_vcc *) (atm_vcc)->dev_data)
#define FS_IS50 0x1
#define FS_IS155 0x2
#define IS_FS50(dev) (dev->flags & FS_IS50)
#define IS_FS155(dev) (dev->flags & FS_IS155)
/* Within limits this is user-configurable. */
/* Note: Currently the sum (10 -> 1k channels) is hardcoded in the driver. */
#define FS155_VPI_BITS 4
#define FS155_VCI_BITS 6
#define FS155_CHANNEL_BITS (FS155_VPI_BITS + FS155_VCI_BITS)
#define FS155_NR_CHANNELS (1 << FS155_CHANNEL_BITS)

2853
drivers/atm/horizon.c
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drivers/atm/horizon.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
Madge Horizon ATM Adapter driver.
Copyright (C) 1995-1999 Madge Networks Ltd.
*/
/*
IMPORTANT NOTE: Madge Networks no longer makes the adapters
supported by this driver and makes no commitment to maintain it.
*/
/* too many macros - change to inline functions */
#ifndef DRIVER_ATM_HORIZON_H
#define DRIVER_ATM_HORIZON_H
#ifdef CONFIG_ATM_HORIZON_DEBUG
#define DEBUG_HORIZON
#endif
#define DEV_LABEL "hrz"
#ifndef PCI_VENDOR_ID_MADGE
#define PCI_VENDOR_ID_MADGE 0x10B6
#endif
#ifndef PCI_DEVICE_ID_MADGE_HORIZON
#define PCI_DEVICE_ID_MADGE_HORIZON 0x1000
#endif
// diagnostic output
#define PRINTK(severity,format,args...) \
printk(severity DEV_LABEL ": " format "\n" , ## args)
#ifdef DEBUG_HORIZON
#define DBG_ERR 0x0001
#define DBG_WARN 0x0002
#define DBG_INFO 0x0004
#define DBG_VCC 0x0008
#define DBG_QOS 0x0010
#define DBG_TX 0x0020
#define DBG_RX 0x0040
#define DBG_SKB 0x0080
#define DBG_IRQ 0x0100
#define DBG_FLOW 0x0200
#define DBG_BUS 0x0400
#define DBG_REGS 0x0800
#define DBG_DATA 0x1000
#define DBG_MASK 0x1fff
/* the ## prevents the annoying double expansion of the macro arguments */
/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
#define PRINTDB(bits,format,args...) \
( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
#define PRINTDM(bits,format,args...) \
( (debug & (bits)) ? printk (format , ## args) : 1 )
#define PRINTDE(bits,format,args...) \
( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
#define PRINTD(bits,format,args...) \
( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
#else
#define PRINTD(bits,format,args...)
#define PRINTDB(bits,format,args...)
#define PRINTDM(bits,format,args...)
#define PRINTDE(bits,format,args...)
#endif
#define PRINTDD(sec,fmt,args...)
#define PRINTDDB(sec,fmt,args...)
#define PRINTDDM(sec,fmt,args...)
#define PRINTDDE(sec,fmt,args...)
// fixed constants
#define SPARE_BUFFER_POOL_SIZE MAX_VCS
#define HRZ_MAX_VPI 4
#define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL
/* Horizon specific bits */
/* Register offsets */
#define HRZ_IO_EXTENT 0x80
#define DATA_PORT_OFF 0x00
#define TX_CHANNEL_PORT_OFF 0x04
#define TX_DESCRIPTOR_PORT_OFF 0x08
#define MEMORY_PORT_OFF 0x0C
#define MEM_WR_ADDR_REG_OFF 0x14
#define MEM_RD_ADDR_REG_OFF 0x18
#define CONTROL_0_REG 0x1C
#define INT_SOURCE_REG_OFF 0x20
#define INT_ENABLE_REG_OFF 0x24
#define MASTER_RX_ADDR_REG_OFF 0x28
#define MASTER_RX_COUNT_REG_OFF 0x2C
#define MASTER_TX_ADDR_REG_OFF 0x30
#define MASTER_TX_COUNT_REG_OFF 0x34
#define TX_DESCRIPTOR_REG_OFF 0x38
#define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40
#define TX_CHANNEL_CONFIG_DATA_OFF 0x44
#define TX_FREE_BUFFER_COUNT_OFF 0x48
#define RX_FREE_BUFFER_COUNT_OFF 0x4C
#define TX_CONFIG_OFF 0x50
#define TX_STATUS_OFF 0x54
#define RX_CONFIG_OFF 0x58
#define RX_LINE_CONFIG_OFF 0x5C
#define RX_QUEUE_RD_PTR_OFF 0x60
#define RX_QUEUE_WR_PTR_OFF 0x64
#define MAX_AAL5_CELL_COUNT_OFF 0x68
#define RX_CHANNEL_PORT_OFF 0x6C
#define TX_CELL_COUNT_OFF 0x70
#define RX_CELL_COUNT_OFF 0x74
#define HEC_ERROR_COUNT_OFF 0x78
#define UNASSIGNED_CELL_COUNT_OFF 0x7C
/* Register bit definitions */
/* Control 0 register */
#define SEEPROM_DO 0x00000001
#define SEEPROM_DI 0x00000002
#define SEEPROM_SK 0x00000004
#define SEEPROM_CS 0x00000008
#define DEBUG_BIT_0 0x00000010
#define DEBUG_BIT_1 0x00000020
#define DEBUG_BIT_2 0x00000040
// RESERVED 0x00000080
#define DEBUG_BIT_0_OE 0x00000100
#define DEBUG_BIT_1_OE 0x00000200
#define DEBUG_BIT_2_OE 0x00000400
// RESERVED 0x00000800
#define DEBUG_BIT_0_STATE 0x00001000
#define DEBUG_BIT_1_STATE 0x00002000
#define DEBUG_BIT_2_STATE 0x00004000
// RESERVED 0x00008000
#define GENERAL_BIT_0 0x00010000
#define GENERAL_BIT_1 0x00020000
#define GENERAL_BIT_2 0x00040000
#define GENERAL_BIT_3 0x00080000
#define RESET_HORIZON 0x00100000
#define RESET_ATM 0x00200000
#define RESET_RX 0x00400000
#define RESET_TX 0x00800000
#define RESET_HOST 0x01000000
// RESERVED 0x02000000
#define TARGET_RETRY_DISABLE 0x04000000
#define ATM_LAYER_SELECT 0x08000000
#define ATM_LAYER_STATUS 0x10000000
// RESERVED 0xE0000000
/* Interrupt source and enable registers */
#define RX_DATA_AV 0x00000001
#define RX_DISABLED 0x00000002
#define TIMING_MARKER 0x00000004
#define FORCED 0x00000008
#define RX_BUS_MASTER_COMPLETE 0x00000010
#define TX_BUS_MASTER_COMPLETE 0x00000020
#define ABR_TX_CELL_COUNT_INT 0x00000040
#define DEBUG_INT 0x00000080
// RESERVED 0xFFFFFF00
/* PIO and Bus Mastering */
#define MAX_PIO_COUNT 0x000000ff // 255 - make tunable?
// 8188 is a hard limit for bus mastering
#define MAX_TRANSFER_COUNT 0x00001ffc // 8188
#define MASTER_TX_AUTO_APPEND_DESC 0x80000000
/* TX channel config command port */
#define PCR_TIMER_ACCESS 0x0000
#define SCR_TIMER_ACCESS 0x0001
#define BUCKET_CAPACITY_ACCESS 0x0002
#define BUCKET_FULLNESS_ACCESS 0x0003
#define RATE_TYPE_ACCESS 0x0004
// UNUSED 0x00F8
#define TX_CHANNEL_CONFIG_MULT 0x0100
// UNUSED 0xF800
#define BUCKET_MAX_SIZE 0x003f
/* TX channel config data port */
#define CLOCK_SELECT_SHIFT 4
#define CLOCK_DISABLE 0x00ff
#define IDLE_RATE_TYPE 0x0
#define ABR_RATE_TYPE 0x1
#define VBR_RATE_TYPE 0x2
#define CBR_RATE_TYPE 0x3
/* TX config register */
#define DRVR_DRVRBAR_ENABLE 0x0001
#define TXCLK_MUX_SELECT_RCLK 0x0002
#define TRANSMIT_TIMING_MARKER 0x0004
#define LOOPBACK_TIMING_MARKER 0x0008
#define TX_TEST_MODE_16MHz 0x0000
#define TX_TEST_MODE_8MHz 0x0010
#define TX_TEST_MODE_5_33MHz 0x0020
#define TX_TEST_MODE_4MHz 0x0030
#define TX_TEST_MODE_3_2MHz 0x0040
#define TX_TEST_MODE_2_66MHz 0x0050
#define TX_TEST_MODE_2_29MHz 0x0060
#define TX_NORMAL_OPERATION 0x0070
#define ABR_ROUND_ROBIN 0x0080
/* TX status register */
#define IDLE_CHANNELS_MASK 0x00FF
#define ABR_CELL_COUNT_REACHED_MULT 0x0100
#define ABR_CELL_COUNT_REACHED_MASK 0xFF
/* RX config register */
#define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008
#define RX_ENABLE 0x0010
#define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000
#define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020
#define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040
/* RX line config register */
#define SIGNAL_LOSS 0x0001
#define FREQUENCY_DETECT_ERROR 0x0002
#define LOCK_DETECT_ERROR 0x0004
#define SELECT_INTERNAL_LOOPBACK 0x0008
#define LOCK_DETECT_ENABLE 0x0010
#define FREQUENCY_DETECT_ENABLE 0x0020
#define USER_FRAQ 0x0040
#define GXTALOUT_SELECT_DIV4 0x0080
#define GXTALOUT_SELECT_NO_GATING 0x0100
#define TIMING_MARKER_RECEIVED 0x0200
/* RX channel port */
#define RX_CHANNEL_MASK 0x03FF
// UNUSED 0x3C00
#define FLUSH_CHANNEL 0x4000
#define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000
/* Receive queue entry */
#define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF
#define RX_Q_ENTRY_CHANNEL_SHIFT 16
#define SIMONS_DODGEY_MARKER 0x08000000
#define RX_CONGESTION_EXPERIENCED 0x10000000
#define RX_CRC_10_OK 0x20000000
#define RX_CRC_32_OK 0x40000000
#define RX_COMPLETE_FRAME 0x80000000
/* Offsets and constants for use with the buffer memory */
/* Buffer pointers and channel types */
#define BUFFER_PTR_MASK 0x0000FFFF
#define RX_INT_THRESHOLD_MULT 0x00010000
#define RX_INT_THRESHOLD_MASK 0x07FF
#define INT_EVERY_N_CELLS 0x08000000
#define CONGESTION_EXPERIENCED 0x10000000
#define FIRST_CELL_OF_AAL5_FRAME 0x20000000
#define CHANNEL_TYPE_AAL5 0x00000000
#define CHANNEL_TYPE_RAW_CELLS 0x40000000
#define CHANNEL_TYPE_AAL3_4 0x80000000
/* Buffer status stuff */
#define BUFF_STATUS_MASK 0x00030000
#define BUFF_STATUS_EMPTY 0x00000000
#define BUFF_STATUS_CELL_AV 0x00010000
#define BUFF_STATUS_LAST_CELL_AV 0x00020000
/* Transmit channel stuff */
/* Receive channel stuff */
#define RX_CHANNEL_DISABLED 0x00000000
#define RX_CHANNEL_IDLE 0x00000001
/* General things */
#define INITIAL_CRC 0xFFFFFFFF
// A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit)
// word addresses and so standard C pointer operations break (as they
// assume byte addresses); so we pretend that Horizon words (and word
// pointers) are bytes (and byte pointers) for the purposes of having
// a memory map that works.
typedef u8 HDW;
typedef struct cell_buf {
HDW payload[12];
HDW next;
HDW cell_count; // AAL5 rx bufs
HDW res;
union {
HDW partial_crc; // AAL5 rx bufs
HDW cell_header; // RAW bufs
} u;
} cell_buf;
typedef struct tx_ch_desc {
HDW rd_buf_type;
HDW wr_buf_type;
HDW partial_crc;
HDW cell_header;
} tx_ch_desc;
typedef struct rx_ch_desc {
HDW wr_buf_type;
HDW rd_buf_type;
} rx_ch_desc;
typedef struct rx_q_entry {
HDW entry;
} rx_q_entry;
#define TX_CHANS 8
#define RX_CHANS 1024
#define RX_QS 1024
#define MAX_VCS RX_CHANS
/* Horizon buffer memory map */
// TX Channel Descriptors 2
// TX Initial Buffers 8 // TX_CHANS
#define BUFN1_SIZE 118 // (126 - TX_CHANS)
// RX/TX Start/End Buffers 4
#define BUFN2_SIZE 124
// RX Queue Entries 64
#define BUFN3_SIZE 192
// RX Channel Descriptors 128
#define BUFN4_SIZE 1408
// TOTAL cell_buff chunks 2048
// cell_buf bufs[2048];
// HDW dws[32768];
typedef struct MEMMAP {
tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020
cell_buf inittxbufs[TX_CHANS]; // these are really
cell_buf bufn1[BUFN1_SIZE]; // part of this pool
cell_buf txfreebufstart;
cell_buf txfreebufend;
cell_buf rxfreebufstart;
cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254
cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000
rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400
cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000
rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800
cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000
} MEMMAP;
#define memmap ((MEMMAP *)0)
/* end horizon specific bits */
typedef enum {
aal0,
aal34,
aal5
} hrz_aal;
typedef enum {
tx_busy,
rx_busy,
ultra
} hrz_flags;
// a single struct pointed to by atm_vcc->dev_data
typedef struct {
unsigned int tx_rate;
unsigned int rx_rate;
u16 channel;
u16 tx_xbr_bits;
u16 tx_pcr_bits;
#if 0
u16 tx_scr_bits;
u16 tx_bucket_bits;
#endif
hrz_aal aal;
} hrz_vcc;
struct hrz_dev {
u32 iobase;
u32 * membase;
struct sk_buff * rx_skb; // skb being RXed
unsigned int rx_bytes; // bytes remaining to RX within region
void * rx_addr; // addr to send bytes to (for PIO)
unsigned int rx_channel; // channel that the skb is going out on
struct sk_buff * tx_skb; // skb being TXed
unsigned int tx_bytes; // bytes remaining to TX within region
void * tx_addr; // addr to send bytes from (for PIO)
struct iovec * tx_iovec; // remaining regions
unsigned int tx_regions; // number of remaining regions
spinlock_t mem_lock;
wait_queue_head_t tx_queue;
u8 irq;
unsigned long flags;
u8 tx_last;
u8 tx_idle;
rx_q_entry * rx_q_reset;
rx_q_entry * rx_q_entry;
rx_q_entry * rx_q_wrap;
struct atm_dev * atm_dev;
u32 last_vc;
int noof_spare_buffers;
u16 spare_buffers[SPARE_BUFFER_POOL_SIZE];
u16 tx_channel_record[TX_CHANS];
// this is what we follow when we get incoming data
u32 txer[MAX_VCS/32];
struct atm_vcc * rxer[MAX_VCS];
// cell rate allocation
spinlock_t rate_lock;
unsigned int rx_avail;
unsigned int tx_avail;
// dev stats
unsigned long tx_cell_count;
unsigned long rx_cell_count;
unsigned long hec_error_count;
unsigned long unassigned_cell_count;
struct pci_dev * pci_dev;
struct timer_list housekeeping;
};
typedef struct hrz_dev hrz_dev;
/* macros for use later */
#define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0)
#define INTERESTING_INTERRUPTS \
(RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE)
// 190 cells by default (192 TX buffers - 2 elbow room, see docs)
#define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112
// Have enough RX buffers (unless we allow other buffer splits)
#define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU
/* multi-statement macro protector */
#define DW(x) do{ x } while(0)
#define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data)
#define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data)
/* Turn the LEDs on and off */
// The LEDs bits are upside down in that setting the bit in the debug
// register will turn the appropriate LED off.
#define YELLOW_LED DEBUG_BIT_0
#define GREEN_LED DEBUG_BIT_1
#define YELLOW_LED_OE DEBUG_BIT_0_OE
#define GREEN_LED_OE DEBUG_BIT_1_OE
#define GREEN_LED_OFF(dev) \
wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
#define GREEN_LED_ON(dev) \
wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
#define YELLOW_LED_OFF(dev) \
wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
#define YELLOW_LED_ON(dev) \
wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
typedef enum {
round_up,
round_down,
round_nearest
} rounding;
#endif /* DRIVER_ATM_HORIZON_H */

293
drivers/atm/uPD98401.h
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@ -1,293 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/uPD98401.h - NEC uPD98401 (SAR) declarations */
/* Written 1995 by Werner Almesberger, EPFL LRC */
#ifndef DRIVERS_ATM_uPD98401_H
#define DRIVERS_ATM_uPD98401_H
#define MAX_CRAM_SIZE (1 << 18) /* 2^18 words */
#define RAM_INCREMENT 1024 /* check in 4 kB increments */
#define uPD98401_PORTS 0x24 /* probably more ? */
/*
* Commands
*/
#define uPD98401_OPEN_CHAN 0x20000000 /* open channel */
#define uPD98401_CHAN_ADDR 0x0003fff8 /* channel address */
#define uPD98401_CHAN_ADDR_SHIFT 3
#define uPD98401_CLOSE_CHAN 0x24000000 /* close channel */
#define uPD98401_CHAN_RT 0x02000000 /* RX/TX (0 TX, 1 RX) */
#define uPD98401_DEACT_CHAN 0x28000000 /* deactivate channel */
#define uPD98401_TX_READY 0x30000000 /* TX ready */
#define uPD98401_ADD_BAT 0x34000000 /* add batches */
#define uPD98401_POOL 0x000f0000 /* pool number */
#define uPD98401_POOL_SHIFT 16
#define uPD98401_POOL_NUMBAT 0x0000ffff /* number of batches */
#define uPD98401_NOP 0x3f000000 /* NOP */
#define uPD98401_IND_ACC 0x00000000 /* Indirect Access */
#define uPD98401_IA_RW 0x10000000 /* Read/Write (0 W, 1 R) */
#define uPD98401_IA_B3 0x08000000 /* Byte select, 1 enable */
#define uPD98401_IA_B2 0x04000000
#define uPD98401_IA_B1 0x02000000
#define uPD98401_IA_B0 0x01000000
#define uPD98401_IA_BALL 0x0f000000 /* whole longword */
#define uPD98401_IA_TGT 0x000c0000 /* Target */
#define uPD98401_IA_TGT_SHIFT 18
#define uPD98401_IA_TGT_CM 0 /* - Control Memory */
#define uPD98401_IA_TGT_SAR 1 /* - uPD98401 registers */
#define uPD98401_IA_TGT_PHY 3 /* - PHY device */
#define uPD98401_IA_ADDR 0x0003ffff
/*
* Command Register Status
*/
#define uPD98401_BUSY 0x80000000 /* SAR is busy */
#define uPD98401_LOCKED 0x40000000 /* SAR is locked by other CPU */
/*
* Indications
*/
/* Normal (AAL5) Receive Indication */
#define uPD98401_AAL5_UINFO 0xffff0000 /* user-supplied information */
#define uPD98401_AAL5_UINFO_SHIFT 16
#define uPD98401_AAL5_SIZE 0x0000ffff /* PDU size (in _CELLS_ !!) */
#define uPD98401_AAL5_CHAN 0x7fff0000 /* Channel number */
#define uPD98401_AAL5_CHAN_SHIFT 16
#define uPD98401_AAL5_ERR 0x00008000 /* Error indication */
#define uPD98401_AAL5_CI 0x00004000 /* Congestion Indication */
#define uPD98401_AAL5_CLP 0x00002000 /* CLP (>= 1 cell had CLP=1) */
#define uPD98401_AAL5_ES 0x00000f00 /* Error Status */
#define uPD98401_AAL5_ES_SHIFT 8
#define uPD98401_AAL5_ES_NONE 0 /* No error */
#define uPD98401_AAL5_ES_FREE 1 /* Receiver free buf underflow */
#define uPD98401_AAL5_ES_FIFO 2 /* Receiver FIFO overrun */
#define uPD98401_AAL5_ES_TOOBIG 3 /* Maximum length violation */
#define uPD98401_AAL5_ES_CRC 4 /* CRC error */
#define uPD98401_AAL5_ES_ABORT 5 /* User abort */
#define uPD98401_AAL5_ES_LENGTH 6 /* Length violation */
#define uPD98401_AAL5_ES_T1 7 /* T1 error (timeout) */
#define uPD98401_AAL5_ES_DEACT 8 /* Deactivated with DEACT_CHAN */
#define uPD98401_AAL5_POOL 0x0000001f /* Free buffer pool number */
/* Raw Cell Indication */
#define uPD98401_RAW_UINFO uPD98401_AAL5_UINFO
#define uPD98401_RAW_UINFO_SHIFT uPD98401_AAL5_UINFO_SHIFT
#define uPD98401_RAW_HEC 0x000000ff /* HEC */
#define uPD98401_RAW_CHAN uPD98401_AAL5_CHAN
#define uPD98401_RAW_CHAN_SHIFT uPD98401_AAL5_CHAN_SHIFT
/* Transmit Indication */
#define uPD98401_TXI_CONN 0x7fff0000 /* Connection Number */
#define uPD98401_TXI_CONN_SHIFT 16
#define uPD98401_TXI_ACTIVE 0x00008000 /* Channel remains active */
#define uPD98401_TXI_PQP 0x00007fff /* Packet Queue Pointer */
/*
* Directly Addressable Registers
*/
#define uPD98401_GMR 0x00 /* General Mode Register */
#define uPD98401_GSR 0x01 /* General Status Register */
#define uPD98401_IMR 0x02 /* Interrupt Mask Register */
#define uPD98401_RQU 0x03 /* Receive Queue Underrun */
#define uPD98401_RQA 0x04 /* Receive Queue Alert */
#define uPD98401_ADDR 0x05 /* Last Burst Address */
#define uPD98401_VER 0x06 /* Version Number */
#define uPD98401_SWR 0x07 /* Software Reset */
#define uPD98401_CMR 0x08 /* Command Register */
#define uPD98401_CMR_L 0x09 /* Command Register and Lock/Unlock */
#define uPD98401_CER 0x0a /* Command Extension Register */
#define uPD98401_CER_L 0x0b /* Command Ext Reg and Lock/Unlock */
#define uPD98401_MSH(n) (0x10+(n)) /* Mailbox n Start Address High */
#define uPD98401_MSL(n) (0x14+(n)) /* Mailbox n Start Address High */
#define uPD98401_MBA(n) (0x18+(n)) /* Mailbox n Bottom Address */
#define uPD98401_MTA(n) (0x1c+(n)) /* Mailbox n Tail Address */
#define uPD98401_MWA(n) (0x20+(n)) /* Mailbox n Write Address */
/* GMR is at 0x00 */
#define uPD98401_GMR_ONE 0x80000000 /* Must be set to one */
#define uPD98401_GMR_SLM 0x40000000 /* Address mode (0 word, 1 byte) */
#define uPD98401_GMR_CPE 0x00008000 /* Control Memory Parity Enable */
#define uPD98401_GMR_LP 0x00004000 /* Loopback */
#define uPD98401_GMR_WA 0x00002000 /* Early Bus Write Abort/RDY */
#define uPD98401_GMR_RA 0x00001000 /* Early Read Abort/RDY */
#define uPD98401_GMR_SZ 0x00000f00 /* Burst Size Enable */
#define uPD98401_BURST16 0x00000800 /* 16-word burst */
#define uPD98401_BURST8 0x00000400 /* 8-word burst */
#define uPD98401_BURST4 0x00000200 /* 4-word burst */
#define uPD98401_BURST2 0x00000100 /* 2-word burst */
#define uPD98401_GMR_AD 0x00000080 /* Address (burst resolution) Disable */
#define uPD98401_GMR_BO 0x00000040 /* Byte Order (0 little, 1 big) */
#define uPD98401_GMR_PM 0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/
#define uPD98401_GMR_PC 0x00000010 /* Bus Parity Control (0even,1odd) */
#define uPD98401_GMR_BPE 0x00000008 /* Bus Parity Enable */
#define uPD98401_GMR_DR 0x00000004 /* Receive Drop Mode (0drop,1don't)*/
#define uPD98401_GMR_SE 0x00000002 /* Shapers Enable */
#define uPD98401_GMR_RE 0x00000001 /* Receiver Enable */
/* GSR is at 0x01, IMR is at 0x02 */
#define uPD98401_INT_PI 0x80000000 /* PHY interrupt */
#define uPD98401_INT_RQA 0x40000000 /* Receive Queue Alert */
#define uPD98401_INT_RQU 0x20000000 /* Receive Queue Underrun */
#define uPD98401_INT_RD 0x10000000 /* Receiver Deactivated */
#define uPD98401_INT_SPE 0x08000000 /* System Parity Error */
#define uPD98401_INT_CPE 0x04000000 /* Control Memory Parity Error */
#define uPD98401_INT_SBE 0x02000000 /* System Bus Error */
#define uPD98401_INT_IND 0x01000000 /* Initialization Done */
#define uPD98401_INT_RCR 0x0000ff00 /* Raw Cell Received */
#define uPD98401_INT_RCR_SHIFT 8
#define uPD98401_INT_MF 0x000000f0 /* Mailbox Full */
#define uPD98401_INT_MF_SHIFT 4
#define uPD98401_INT_MM 0x0000000f /* Mailbox Modified */
/* VER is at 0x06 */
#define uPD98401_MAJOR 0x0000ff00 /* Major revision */
#define uPD98401_MAJOR_SHIFT 8
#define uPD98401_MINOR 0x000000ff /* Minor revision */
/*
* Indirectly Addressable Registers
*/
#define uPD98401_IM(n) (0x40000+(n)) /* Scheduler n I and M */
#define uPD98401_X(n) (0x40010+(n)) /* Scheduler n X */
#define uPD98401_Y(n) (0x40020+(n)) /* Scheduler n Y */
#define uPD98401_PC(n) (0x40030+(n)) /* Scheduler n P, C, p and c */
#define uPD98401_PS(n) (0x40040+(n)) /* Scheduler n priority and status */
/* IM contents */
#define uPD98401_IM_I 0xff000000 /* I */
#define uPD98401_IM_I_SHIFT 24
#define uPD98401_IM_M 0x00ffffff /* M */
/* PC contents */
#define uPD98401_PC_P 0xff000000 /* P */
#define uPD98401_PC_P_SHIFT 24
#define uPD98401_PC_C 0x00ff0000 /* C */
#define uPD98401_PC_C_SHIFT 16
#define uPD98401_PC_p 0x0000ff00 /* p */
#define uPD98401_PC_p_SHIFT 8
#define uPD98401_PC_c 0x000000ff /* c */
/* PS contents */
#define uPD98401_PS_PRIO 0xf0 /* Priority level (0 high, 15 low) */
#define uPD98401_PS_PRIO_SHIFT 4
#define uPD98401_PS_S 0x08 /* Scan - must be 0 (internal) */
#define uPD98401_PS_R 0x04 /* Round Robin (internal) */
#define uPD98401_PS_A 0x02 /* Active (internal) */
#define uPD98401_PS_E 0x01 /* Enabled */
#define uPD98401_TOS 0x40100 /* Top of Stack Control Memory Address */
#define uPD98401_SMA 0x40200 /* Shapers Control Memory Start Address */
#define uPD98401_PMA 0x40201 /* Receive Pool Control Memory Start Address */
#define uPD98401_T1R 0x40300 /* T1 Register */
#define uPD98401_VRR 0x40301 /* VPI/VCI Reduction Register/Recv. Shutdown */
#define uPD98401_TSR 0x40302 /* Time-Stamp Register */
/* VRR is at 0x40301 */
#define uPD98401_VRR_SDM 0x80000000 /* Shutdown Mode */
#define uPD98401_VRR_SHIFT 0x000f0000 /* VPI/VCI Shift */
#define uPD98401_VRR_SHIFT_SHIFT 16
#define uPD98401_VRR_MASK 0x0000ffff /* VPI/VCI mask */
/*
* TX packet descriptor
*/
#define uPD98401_TXPD_SIZE 16 /* descriptor size (in bytes) */
#define uPD98401_TXPD_V 0x80000000 /* Valid bit */
#define uPD98401_TXPD_DP 0x40000000 /* Descriptor (1) or Pointer (0) */
#define uPD98401_TXPD_SM 0x20000000 /* Single (1) or Multiple (0) */
#define uPD98401_TXPD_CLPM 0x18000000 /* CLP mode */
#define uPD98401_CLPM_0 0 /* 00 CLP = 0 */
#define uPD98401_CLPM_1 3 /* 11 CLP = 1 */
#define uPD98401_CLPM_LAST 1 /* 01 CLP unless last cell */
#define uPD98401_TXPD_CLPM_SHIFT 27
#define uPD98401_TXPD_PTI 0x07000000 /* PTI pattern */
#define uPD98401_TXPD_PTI_SHIFT 24
#define uPD98401_TXPD_GFC 0x00f00000 /* GFC pattern */
#define uPD98401_TXPD_GFC_SHIFT 20
#define uPD98401_TXPD_C10 0x00040000 /* insert CRC-10 */
#define uPD98401_TXPD_AAL5 0x00020000 /* AAL5 processing */
#define uPD98401_TXPD_MB 0x00010000 /* TX mailbox number */
#define uPD98401_TXPD_UU 0x0000ff00 /* CPCS-UU */
#define uPD98401_TXPD_UU_SHIFT 8
#define uPD98401_TXPD_CPI 0x000000ff /* CPI */
/*
* TX buffer descriptor
*/
#define uPD98401_TXBD_SIZE 8 /* descriptor size (in bytes) */
#define uPD98401_TXBD_LAST 0x80000000 /* last buffer in packet */
/*
* TX VC table
*/
/* 1st word has the same structure as in a TX packet descriptor */
#define uPD98401_TXVC_L 0x80000000 /* last buffer */
#define uPD98401_TXVC_SHP 0x0f000000 /* shaper number */
#define uPD98401_TXVC_SHP_SHIFT 24
#define uPD98401_TXVC_VPI 0x00ff0000 /* VPI */
#define uPD98401_TXVC_VPI_SHIFT 16
#define uPD98401_TXVC_VCI 0x0000ffff /* VCI */
#define uPD98401_TXVC_QRP 6 /* Queue Read Pointer is in word 6 */
/*
* RX free buffer pools descriptor
*/
#define uPD98401_RXFP_ALERT 0x70000000 /* low water mark */
#define uPD98401_RXFP_ALERT_SHIFT 28
#define uPD98401_RXFP_BFSZ 0x0f000000 /* buffer size, 64*2^n */
#define uPD98401_RXFP_BFSZ_SHIFT 24
#define uPD98401_RXFP_BTSZ 0x00ff0000 /* batch size, n+1 */
#define uPD98401_RXFP_BTSZ_SHIFT 16
#define uPD98401_RXFP_REMAIN 0x0000ffff /* remaining batches in pool */
/*
* RX VC table
*/
#define uPD98401_RXVC_BTSZ 0xff000000 /* remaining free buffers in batch */
#define uPD98401_RXVC_BTSZ_SHIFT 24
#define uPD98401_RXVC_MB 0x00200000 /* RX mailbox number */
#define uPD98401_RXVC_POOL 0x001f0000 /* free buffer pool number */
#define uPD98401_RXVC_POOL_SHIFT 16
#define uPD98401_RXVC_UINFO 0x0000ffff /* user-supplied information */
#define uPD98401_RXVC_T1 0xffff0000 /* T1 timestamp */
#define uPD98401_RXVC_T1_SHIFT 16
#define uPD98401_RXVC_PR 0x00008000 /* Packet Reception, 1 if busy */
#define uPD98401_RXVC_DR 0x00004000 /* FIFO Drop */
#define uPD98401_RXVC_OD 0x00001000 /* Drop OAM cells */
#define uPD98401_RXVC_AR 0x00000800 /* AAL5 or raw cell; 1 if AAL5 */
#define uPD98401_RXVC_MAXSEG 0x000007ff /* max number of segments per PDU */
#define uPD98401_RXVC_REM 0xfffe0000 /* remaining words in curr buffer */
#define uPD98401_RXVC_REM_SHIFT 17
#define uPD98401_RXVC_CLP 0x00010000 /* CLP received */
#define uPD98401_RXVC_BFA 0x00008000 /* Buffer Assigned */
#define uPD98401_RXVC_BTA 0x00004000 /* Batch Assigned */
#define uPD98401_RXVC_CI 0x00002000 /* Congestion Indication */
#define uPD98401_RXVC_DD 0x00001000 /* Dropping incoming cells */
#define uPD98401_RXVC_DP 0x00000800 /* like PR ? */
#define uPD98401_RXVC_CURSEG 0x000007ff /* Current Segment count */
/*
* RX lookup table
*/
#define uPD98401_RXLT_ENBL 0x8000 /* Enable */
#endif

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drivers/atm/uPD98402.c
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// SPDX-License-Identifier: GPL-2.0-only
/* drivers/atm/uPD98402.c - NEC uPD98402 (PHY) declarations */
/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/atmdev.h>
#include <linux/sonet.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/atomic.h>
#include "uPD98402.h"
#if 0
#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
#else
#define DPRINTK(format,args...)
#endif
struct uPD98402_priv {
struct k_sonet_stats sonet_stats;/* link diagnostics */
unsigned char framing; /* SONET/SDH framing */
int loop_mode; /* loopback mode */
spinlock_t lock;
};
#define PRIV(dev) ((struct uPD98402_priv *) dev->phy_data)
#define PUT(val,reg) dev->ops->phy_put(dev,val,uPD98402_##reg)
#define GET(reg) dev->ops->phy_get(dev,uPD98402_##reg)
static int fetch_stats(struct atm_dev *dev,struct sonet_stats __user *arg,int zero)
{
struct sonet_stats tmp;
int error = 0;
atomic_add(GET(HECCT),&PRIV(dev)->sonet_stats.uncorr_hcs);
sonet_copy_stats(&PRIV(dev)->sonet_stats,&tmp);
if (arg) error = copy_to_user(arg,&tmp,sizeof(tmp));
if (zero && !error) {
/* unused fields are reported as -1, but we must not "adjust"
them */
tmp.corr_hcs = tmp.tx_cells = tmp.rx_cells = 0;
sonet_subtract_stats(&PRIV(dev)->sonet_stats,&tmp);
}
return error ? -EFAULT : 0;
}
static int set_framing(struct atm_dev *dev,unsigned char framing)
{
static const unsigned char sonet[] = { 1,2,3,0 };
static const unsigned char sdh[] = { 1,0,0,2 };
const char *set;
unsigned long flags;
switch (framing) {
case SONET_FRAME_SONET:
set = sonet;
break;
case SONET_FRAME_SDH:
set = sdh;
break;
default:
return -EINVAL;
}
spin_lock_irqsave(&PRIV(dev)->lock, flags);
PUT(set[0],C11T);
PUT(set[1],C12T);
PUT(set[2],C13T);
PUT((GET(MDR) & ~uPD98402_MDR_SS_MASK) | (set[3] <<
uPD98402_MDR_SS_SHIFT),MDR);
spin_unlock_irqrestore(&PRIV(dev)->lock, flags);
return 0;
}
static int get_sense(struct atm_dev *dev,u8 __user *arg)
{
unsigned long flags;
unsigned char s[3];
spin_lock_irqsave(&PRIV(dev)->lock, flags);
s[0] = GET(C11R);
s[1] = GET(C12R);
s[2] = GET(C13R);
spin_unlock_irqrestore(&PRIV(dev)->lock, flags);
return (put_user(s[0], arg) || put_user(s[1], arg+1) ||
put_user(s[2], arg+2) || put_user(0xff, arg+3) ||
put_user(0xff, arg+4) || put_user(0xff, arg+5)) ? -EFAULT : 0;
}
static int set_loopback(struct atm_dev *dev,int mode)
{
unsigned char mode_reg;
mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP |
uPD98402_MDR_RPLP);
switch (__ATM_LM_XTLOC(mode)) {
case __ATM_LM_NONE:
break;
case __ATM_LM_PHY:
mode_reg |= uPD98402_MDR_TPLP;
break;
case __ATM_LM_ATM:
mode_reg |= uPD98402_MDR_ALP;
break;
default:
return -EINVAL;
}
switch (__ATM_LM_XTRMT(mode)) {
case __ATM_LM_NONE:
break;
case __ATM_LM_PHY:
mode_reg |= uPD98402_MDR_RPLP;
break;
default:
return -EINVAL;
}
PUT(mode_reg,MDR);
PRIV(dev)->loop_mode = mode;
return 0;
}
static int uPD98402_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
{
switch (cmd) {
case SONET_GETSTATZ:
case SONET_GETSTAT:
return fetch_stats(dev,arg, cmd == SONET_GETSTATZ);
case SONET_SETFRAMING:
return set_framing(dev, (int)(unsigned long)arg);
case SONET_GETFRAMING:
return put_user(PRIV(dev)->framing,(int __user *)arg) ?
-EFAULT : 0;
case SONET_GETFRSENSE:
return get_sense(dev,arg);
case ATM_SETLOOP:
return set_loopback(dev, (int)(unsigned long)arg);
case ATM_GETLOOP:
return put_user(PRIV(dev)->loop_mode,(int __user *)arg) ?
-EFAULT : 0;
case ATM_QUERYLOOP:
return put_user(ATM_LM_LOC_PHY | ATM_LM_LOC_ATM |
ATM_LM_RMT_PHY,(int __user *)arg) ? -EFAULT : 0;
default:
return -ENOIOCTLCMD;
}
}
#define ADD_LIMITED(s,v) \
{ atomic_add(GET(v),&PRIV(dev)->sonet_stats.s); \
if (atomic_read(&PRIV(dev)->sonet_stats.s) < 0) \
atomic_set(&PRIV(dev)->sonet_stats.s,INT_MAX); }
static void stat_event(struct atm_dev *dev)
{
unsigned char events;
events = GET(PCR);
if (events & uPD98402_PFM_PFEB) ADD_LIMITED(path_febe,PFECB);
if (events & uPD98402_PFM_LFEB) ADD_LIMITED(line_febe,LECCT);
if (events & uPD98402_PFM_B3E) ADD_LIMITED(path_bip,B3ECT);
if (events & uPD98402_PFM_B2E) ADD_LIMITED(line_bip,B2ECT);
if (events & uPD98402_PFM_B1E) ADD_LIMITED(section_bip,B1ECT);
}
#undef ADD_LIMITED
static void uPD98402_int(struct atm_dev *dev)
{
static unsigned long silence = 0;
unsigned char reason;
while ((reason = GET(PICR))) {
if (reason & uPD98402_INT_LOS)
printk(KERN_NOTICE "%s(itf %d): signal lost\n",
dev->type,dev->number);
if (reason & uPD98402_INT_PFM) stat_event(dev);
if (reason & uPD98402_INT_PCO) {
(void) GET(PCOCR); /* clear interrupt cause */
atomic_add(GET(HECCT),
&PRIV(dev)->sonet_stats.uncorr_hcs);
}
if ((reason & uPD98402_INT_RFO) &&
(time_after(jiffies, silence) || silence == 0)) {
printk(KERN_WARNING "%s(itf %d): uPD98402 receive "
"FIFO overflow\n",dev->type,dev->number);
silence = (jiffies+HZ/2)|1;
}
}
}
static int uPD98402_start(struct atm_dev *dev)
{
DPRINTK("phy_start\n");
if (!(dev->phy_data = kmalloc(sizeof(struct uPD98402_priv),GFP_KERNEL)))
return -ENOMEM;
spin_lock_init(&PRIV(dev)->lock);
memset(&PRIV(dev)->sonet_stats,0,sizeof(struct k_sonet_stats));
(void) GET(PCR); /* clear performance events */
PUT(uPD98402_PFM_FJ,PCMR); /* ignore frequency adj */
(void) GET(PCOCR); /* clear overflows */
PUT(~uPD98402_PCO_HECC,PCOMR);
(void) GET(PICR); /* clear interrupts */
PUT(~(uPD98402_INT_PFM | uPD98402_INT_ALM | uPD98402_INT_RFO |
uPD98402_INT_LOS),PIMR); /* enable them */
(void) fetch_stats(dev,NULL,1); /* clear kernel counters */
atomic_set(&PRIV(dev)->sonet_stats.corr_hcs,-1);
atomic_set(&PRIV(dev)->sonet_stats.tx_cells,-1);
atomic_set(&PRIV(dev)->sonet_stats.rx_cells,-1);
return 0;
}
static int uPD98402_stop(struct atm_dev *dev)
{
/* let SAR driver worry about stopping interrupts */
kfree(PRIV(dev));
return 0;
}
static const struct atmphy_ops uPD98402_ops = {
.start = uPD98402_start,
.ioctl = uPD98402_ioctl,
.interrupt = uPD98402_int,
.stop = uPD98402_stop,
};
int uPD98402_init(struct atm_dev *dev)
{
DPRINTK("phy_init\n");
dev->phy = &uPD98402_ops;
return 0;
}
MODULE_LICENSE("GPL");
EXPORT_SYMBOL(uPD98402_init);
static __init int uPD98402_module_init(void)
{
return 0;
}
module_init(uPD98402_module_init);
/* module_exit not defined so not unloadable */

107
drivers/atm/uPD98402.h
View File

@ -1,107 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/uPD98402.h - NEC uPD98402 (PHY) declarations */
/* Written 1995 by Werner Almesberger, EPFL LRC */
#ifndef DRIVERS_ATM_uPD98402_H
#define DRIVERS_ATM_uPD98402_H
/*
* Registers
*/
#define uPD98402_CMR 0x00 /* Command Register */
#define uPD98402_MDR 0x01 /* Mode Register */
#define uPD98402_PICR 0x02 /* PHY Interrupt Cause Register */
#define uPD98402_PIMR 0x03 /* PHY Interrupt Mask Register */
#define uPD98402_ACR 0x04 /* Alarm Cause Register */
#define uPD98402_ACMR 0x05 /* Alarm Cause Mask Register */
#define uPD98402_PCR 0x06 /* Performance Cause Register */
#define uPD98402_PCMR 0x07 /* Performance Cause Mask Register */
#define uPD98402_IACM 0x08 /* Internal Alarm Cause Mask Register */
#define uPD98402_B1ECT 0x09 /* B1 Error Count Register */
#define uPD98402_B2ECT 0x0a /* B2 Error Count Register */
#define uPD98402_B3ECT 0x0b /* B3 Error Count Regster */
#define uPD98402_PFECB 0x0c /* Path FEBE Count Register */
#define uPD98402_LECCT 0x0d /* Line FEBE Count Register */
#define uPD98402_HECCT 0x0e /* HEC Error Count Register */
#define uPD98402_FJCT 0x0f /* Frequence Justification Count Reg */
#define uPD98402_PCOCR 0x10 /* Perf. Counter Overflow Cause Reg */
#define uPD98402_PCOMR 0x11 /* Perf. Counter Overflow Mask Reg */
#define uPD98402_C11T 0x20 /* C11T Data Register */
#define uPD98402_C12T 0x21 /* C12T Data Register */
#define uPD98402_C13T 0x22 /* C13T Data Register */
#define uPD98402_F1T 0x23 /* F1T Data Register */
#define uPD98402_K2T 0x25 /* K2T Data Register */
#define uPD98402_C2T 0x26 /* C2T Data Register */
#define uPD98402_F2T 0x27 /* F2T Data Register */
#define uPD98402_C11R 0x30 /* C11T Data Register */
#define uPD98402_C12R 0x31 /* C12T Data Register */
#define uPD98402_C13R 0x32 /* C13T Data Register */
#define uPD98402_F1R 0x33 /* F1T Data Register */
#define uPD98402_K2R 0x35 /* K2T Data Register */
#define uPD98402_C2R 0x36 /* C2T Data Register */
#define uPD98402_F2R 0x37 /* F2T Data Register */
/* CMR is at 0x00 */
#define uPD98402_CMR_PFRF 0x01 /* Send path FERF */
#define uPD98402_CMR_LFRF 0x02 /* Send line FERF */
#define uPD98402_CMR_PAIS 0x04 /* Send path AIS */
#define uPD98402_CMR_LAIS 0x08 /* Send line AIS */
/* MDR is at 0x01 */
#define uPD98402_MDR_ALP 0x01 /* ATM layer loopback */
#define uPD98402_MDR_TPLP 0x02 /* PMD loopback, to host */
#define uPD98402_MDR_RPLP 0x04 /* PMD loopback, to network */
#define uPD98402_MDR_SS0 0x08 /* SS0 */
#define uPD98402_MDR_SS1 0x10 /* SS1 */
#define uPD98402_MDR_SS_MASK 0x18 /* mask */
#define uPD98402_MDR_SS_SHIFT 3 /* shift */
#define uPD98402_MDR_HEC 0x20 /* disable HEC inbound processing */
#define uPD98402_MDR_FSR 0x40 /* disable frame scrambler */
#define uPD98402_MDR_CSR 0x80 /* disable cell scrambler */
/* PICR is at 0x02, PIMR is at 0x03 */
#define uPD98402_INT_PFM 0x01 /* performance counter has changed */
#define uPD98402_INT_ALM 0x02 /* line fault */
#define uPD98402_INT_RFO 0x04 /* receive FIFO overflow */
#define uPD98402_INT_PCO 0x08 /* performance counter overflow */
#define uPD98402_INT_OTD 0x20 /* OTD has occurred */
#define uPD98402_INT_LOS 0x40 /* Loss Of Signal */
#define uPD98402_INT_LOF 0x80 /* Loss Of Frame */
/* ACR is as 0x04, ACMR is at 0x05 */
#define uPD98402_ALM_PFRF 0x01 /* path FERF */
#define uPD98402_ALM_LFRF 0x02 /* line FERF */
#define uPD98402_ALM_PAIS 0x04 /* path AIS */
#define uPD98402_ALM_LAIS 0x08 /* line AIS */
#define uPD98402_ALM_LOD 0x10 /* loss of delineation */
#define uPD98402_ALM_LOP 0x20 /* loss of pointer */
#define uPD98402_ALM_OOF 0x40 /* out of frame */
/* PCR is at 0x06, PCMR is at 0x07 */
#define uPD98402_PFM_PFEB 0x01 /* path FEBE */
#define uPD98402_PFM_LFEB 0x02 /* line FEBE */
#define uPD98402_PFM_B3E 0x04 /* B3 error */
#define uPD98402_PFM_B2E 0x08 /* B2 error */
#define uPD98402_PFM_B1E 0x10 /* B1 error */
#define uPD98402_PFM_FJ 0x20 /* frequency justification */
/* IACM is at 0x08 */
#define uPD98402_IACM_PFRF 0x01 /* don't generate path FERF */
#define uPD98402_IACM_LFRF 0x02 /* don't generate line FERF */
/* PCOCR is at 0x010, PCOMR is at 0x11 */
#define uPD98402_PCO_B1EC 0x01 /* B1ECT overflow */
#define uPD98402_PCO_B2EC 0x02 /* B2ECT overflow */
#define uPD98402_PCO_B3EC 0x04 /* B3ECT overflow */
#define uPD98402_PCO_PFBC 0x08 /* PFEBC overflow */
#define uPD98402_PCO_LFBC 0x10 /* LFEVC overflow */
#define uPD98402_PCO_HECC 0x20 /* HECCT overflow */
#define uPD98402_PCO_FJC 0x40 /* FJCT overflow */
int uPD98402_init(struct atm_dev *dev);
#endif

1652
drivers/atm/zatm.c
View File

File diff suppressed because it is too large Load Diff

104
drivers/atm/zatm.h
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@ -1,104 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/zatm.h - ZeitNet ZN122x device driver declarations */
/* Written 1995-1998 by Werner Almesberger, EPFL LRC/ICA */
#ifndef DRIVER_ATM_ZATM_H
#define DRIVER_ATM_ZATM_H
#include <linux/skbuff.h>
#include <linux/atm.h>
#include <linux/atmdev.h>
#include <linux/sonet.h>
#include <linux/pci.h>
#define DEV_LABEL "zatm"
#define MAX_AAL5_PDU 10240 /* allocate for AAL5 PDUs of this size */
#define MAX_RX_SIZE_LD 14 /* ceil(log2((MAX_AAL5_PDU+47)/48)) */
#define LOW_MARK 12 /* start adding new buffers if less than 12 */
#define HIGH_MARK 30 /* stop adding buffers after reaching 30 */
#define OFF_CNG_THRES 5 /* threshold for offset changes */
#define RX_SIZE 2 /* RX lookup entry size (in bytes) */
#define NR_POOLS 32 /* number of free buffer pointers */
#define POOL_SIZE 8 /* buffer entry size (in bytes) */
#define NR_SHAPERS 16 /* number of shapers */
#define SHAPER_SIZE 4 /* shaper entry size (in bytes) */
#define VC_SIZE 32 /* VC dsc (TX or RX) size (in bytes) */
#define RING_ENTRIES 32 /* ring entries (without back pointer) */
#define RING_WORDS 4 /* ring element size */
#define RING_SIZE (sizeof(unsigned long)*(RING_ENTRIES+1)*RING_WORDS)
#define NR_MBX 4 /* four mailboxes */
#define MBX_RX_0 0 /* mailbox indices */
#define MBX_RX_1 1
#define MBX_TX_0 2
#define MBX_TX_1 3
struct zatm_vcc {
/*-------------------------------- RX part */
int rx_chan; /* RX channel, 0 if none */
int pool; /* free buffer pool */
/*-------------------------------- TX part */
int tx_chan; /* TX channel, 0 if none */
int shaper; /* shaper, <0 if none */
struct sk_buff_head tx_queue; /* list of buffers in transit */
wait_queue_head_t tx_wait; /* for close */
u32 *ring; /* transmit ring */
int ring_curr; /* current write position */
int txing; /* number of transmits in progress */
struct sk_buff_head backlog; /* list of buffers waiting for ring */
};
struct zatm_dev {
/*-------------------------------- TX part */
int tx_bw; /* remaining bandwidth */
u32 free_shapers; /* bit set */
int ubr; /* UBR shaper; -1 if none */
int ubr_ref_cnt; /* number of VCs using UBR shaper */
/*-------------------------------- RX part */
int pool_ref[NR_POOLS]; /* free buffer pool usage counters */
volatile struct sk_buff *last_free[NR_POOLS];
/* last entry in respective pool */
struct sk_buff_head pool[NR_POOLS];/* free buffer pools */
struct zatm_pool_info pool_info[NR_POOLS]; /* pool information */
/*-------------------------------- maps */
struct atm_vcc **tx_map; /* TX VCCs */
struct atm_vcc **rx_map; /* RX VCCs */
int chans; /* map size, must be 2^n */
/*-------------------------------- mailboxes */
unsigned long mbx_start[NR_MBX];/* start addresses */
dma_addr_t mbx_dma[NR_MBX];
u16 mbx_end[NR_MBX]; /* end offset (in bytes) */
/*-------------------------------- other pointers */
u32 pool_base; /* Free buffer pool dsc (word addr) */
/*-------------------------------- ZATM links */
struct atm_dev *more; /* other ZATM devices */
/*-------------------------------- general information */
int mem; /* RAM on board (in bytes) */
int khz; /* timer clock */
int copper; /* PHY type */
unsigned char irq; /* IRQ */
unsigned int base; /* IO base address */
struct pci_dev *pci_dev; /* PCI stuff */
spinlock_t lock;
};
#define ZATM_DEV(d) ((struct zatm_dev *) (d)->dev_data)
#define ZATM_VCC(d) ((struct zatm_vcc *) (d)->dev_data)
struct zatm_skb_prv {
struct atm_skb_data _; /* reserved */
u32 *dsc; /* pointer to skb's descriptor */
};
#define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc)
#endif

34
drivers/net/hamradio/Kconfig
View File

@ -45,40 +45,6 @@ config BPQETHER
useful if some other computer on your local network has a direct
amateur radio connection.
config DMASCC
tristate "High-speed (DMA) SCC driver for AX.25"
depends on ISA && AX25 && BROKEN_ON_SMP && ISA_DMA_API
depends on VIRT_TO_BUS
help
This is a driver for high-speed SCC boards, i.e. those supporting
DMA on one port. You usually use those boards to connect your
computer to an amateur radio modem (such as the WA4DSY 56kbps
modem), in order to send and receive AX.25 packet radio network
traffic.
Currently, this driver supports Ottawa PI/PI2, Paccomm/Gracilis
PackeTwin, and S5SCC/DMA boards. They are detected automatically.
If you have one of these cards, say Y here and read the AX25-HOWTO,
available from <http://www.tldp.org/docs.html#howto>.
This driver can operate multiple boards simultaneously. If you
compile it as a module (by saying M instead of Y), it will be called
dmascc. If you don't pass any parameter to the driver, all
possible I/O addresses are probed. This could irritate other devices
that are currently not in use. You may specify the list of addresses
to be probed by "dmascc.io=addr1,addr2,..." (when compiled into the
kernel image) or "io=addr1,addr2,..." (when loaded as a module). The
network interfaces will be called dmascc0 and dmascc1 for the board
detected first, dmascc2 and dmascc3 for the second one, and so on.
Before you configure each interface with ifconfig, you MUST set
certain parameters, such as channel access timing, clock mode, and
DMA channel. This is accomplished with a small utility program,
dmascc_cfg, available at
<http://www.linux-ax25.org/wiki/Ax25-tools>. Please be sure to
get at least version 1.27 of dmascc_cfg, as older versions will not
work with the current driver.
config SCC
tristate "Z8530 SCC driver"
depends on ISA && AX25 && ISA_DMA_API

1
drivers/net/hamradio/Makefile
View File

@ -11,7 +11,6 @@
# Christoph Hellwig <hch@infradead.org>
#
obj-$(CONFIG_DMASCC) += dmascc.o
obj-$(CONFIG_SCC) += scc.o
obj-$(CONFIG_MKISS) += mkiss.o
obj-$(CONFIG_6PACK) += 6pack.o

1450
drivers/net/hamradio/dmascc.c
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File diff suppressed because it is too large Load Diff

44
drivers/net/wan/Kconfig
View File

@ -23,50 +23,6 @@ menuconfig WAN
if WAN
# There is no way to detect a comtrol sv11 - force it modular for now.
config HOSTESS_SV11
tristate "Comtrol Hostess SV-11 support"
depends on ISA && m && ISA_DMA_API && INET && HDLC && VIRT_TO_BUS
help
Driver for Comtrol Hostess SV-11 network card which
operates on low speed synchronous serial links at up to
256Kbps, supporting PPP and Cisco HDLC.
The driver will be compiled as a module: the
module will be called hostess_sv11.
# The COSA/SRP driver has not been tested as non-modular yet.
config COSA
tristate "COSA/SRP sync serial boards support"
depends on ISA && m && ISA_DMA_API && HDLC && VIRT_TO_BUS
help
Driver for COSA and SRP synchronous serial boards.
These boards allow to connect synchronous serial devices (for example
base-band modems, or any other device with the X.21, V.24, V.35 or
V.36 interface) to your Linux box. The cards can work as the
character device, synchronous PPP network device, or the Cisco HDLC
network device.
You will need user-space utilities COSA or SRP boards for downloading
the firmware to the cards and to set them up. Look at the
<http://www.fi.muni.cz/~kas/cosa/> for more information. You can also
read the comment at the top of the <file:drivers/net/wan/cosa.c> for
details about the cards and the driver itself.
The driver will be compiled as a module: the
module will be called cosa.
# There is no way to detect a Sealevel board. Force it modular
config SEALEVEL_4021
tristate "Sealevel Systems 4021 support"
depends on ISA && m && ISA_DMA_API && INET && HDLC && VIRT_TO_BUS
help
This is a driver for the Sealevel Systems ACB 56 serial I/O adapter.
The driver will be compiled as a module: the
module will be called sealevel.
# Generic HDLC
config HDLC
tristate "Generic HDLC layer"

3
drivers/net/wan/Makefile
View File

@ -14,9 +14,6 @@ obj-$(CONFIG_HDLC_FR) += hdlc_fr.o
obj-$(CONFIG_HDLC_PPP) += hdlc_ppp.o
obj-$(CONFIG_HDLC_X25) += hdlc_x25.o
obj-$(CONFIG_HOSTESS_SV11) += z85230.o hostess_sv11.o
obj-$(CONFIG_SEALEVEL_4021) += z85230.o sealevel.o
obj-$(CONFIG_COSA) += cosa.o
obj-$(CONFIG_FARSYNC) += farsync.o
obj-$(CONFIG_LAPBETHER) += lapbether.o

2052
drivers/net/wan/cosa.c
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104
drivers/net/wan/cosa.h
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@ -1,104 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* $Id: cosa.h,v 1.6 1999/01/06 14:02:44 kas Exp $ */
/*
* Copyright (C) 1995-1997 Jan "Yenya" Kasprzak <kas@fi.muni.cz>
*/
#ifndef COSA_H__
#define COSA_H__
#include <linux/ioctl.h>
#ifdef __KERNEL__
/* status register - output bits */
#define SR_RX_DMA_ENA 0x04 /* receiver DMA enable bit */
#define SR_TX_DMA_ENA 0x08 /* transmitter DMA enable bit */
#define SR_RST 0x10 /* SRP reset */
#define SR_USR_INT_ENA 0x20 /* user interrupt enable bit */
#define SR_TX_INT_ENA 0x40 /* transmitter interrupt enable bit */
#define SR_RX_INT_ENA 0x80 /* receiver interrupt enable bit */
/* status register - input bits */
#define SR_USR_RQ 0x20 /* user interrupt request pending */
#define SR_TX_RDY 0x40 /* transmitter empty (ready) */
#define SR_RX_RDY 0x80 /* receiver data ready */
#define SR_UP_REQUEST 0x02 /* request from SRP to transfer data
up to PC */
#define SR_DOWN_REQUEST 0x01 /* SRP is able to transfer data down
from PC to SRP */
#define SR_END_OF_TRANSFER 0x03 /* SRP signalize end of
transfer (up or down) */
#define SR_CMD_FROM_SRP_MASK 0x03 /* mask to get SRP command */
/* bits in driver status byte definitions : */
#define SR_RDY_RCV 0x01 /* ready to receive packet */
#define SR_RDY_SND 0x02 /* ready to send packet */
#define SR_CMD_PND 0x04 /* command pending */ /* not currently used */
/* ???? */
#define SR_PKT_UP 0x01 /* transfer of packet up in progress */
#define SR_PKT_DOWN 0x02 /* transfer of packet down in progress */
#endif /* __KERNEL__ */
#define SR_LOAD_ADDR 0x4400 /* SRP microcode load address */
#define SR_START_ADDR 0x4400 /* SRP microcode start address */
#define COSA_LOAD_ADDR 0x400 /* SRP microcode load address */
#define COSA_MAX_FIRMWARE_SIZE 0x10000
/* ioctls */
struct cosa_download {
int addr, len;
char __user *code;
};
/* Reset the device */
#define COSAIORSET _IO('C',0xf0)
/* Start microcode at given address */
#define COSAIOSTRT _IOW('C',0xf1, int)
/* Read the block from the device memory */
#define COSAIORMEM _IOWR('C',0xf2, struct cosa_download *)
/* actually the struct cosa_download itself; this is to keep
* the ioctl number same as in 2.4 in order to keep the user-space
* utils compatible. */
/* Write the block to the device memory (i.e. download the microcode) */
#define COSAIODOWNLD _IOW('C',0xf2, struct cosa_download *)
/* actually the struct cosa_download itself; this is to keep
* the ioctl number same as in 2.4 in order to keep the user-space
* utils compatible. */
/* Read the device type (one of "srp", "cosa", and "cosa8" for now) */
#define COSAIORTYPE _IOR('C',0xf3, char *)
/* Read the device identification string */
#define COSAIORIDSTR _IOR('C',0xf4, char *)
/* Maximum length of the identification string. */
#define COSA_MAX_ID_STRING 128
/* Increment/decrement the module usage count :-) */
/* #define COSAIOMINC _IO('C',0xf5) */
/* #define COSAIOMDEC _IO('C',0xf6) */
/* Get the total number of cards installed */
#define COSAIONRCARDS _IO('C',0xf7)
/* Get the number of channels on this card */
#define COSAIONRCHANS _IO('C',0xf8)
/* Set the driver for the bus-master operations */
#define COSAIOBMSET _IOW('C', 0xf9, unsigned short)
#define COSA_BM_OFF 0 /* Bus-mastering off - use ISA DMA (default) */
#define COSA_BM_ON 1 /* Bus-mastering on - faster but untested */
/* Gets the busmaster status */
#define COSAIOBMGET _IO('C', 0xfa)
#endif /* !COSA_H__ */

336
drivers/net/wan/hostess_sv11.c
View File

@ -1,336 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Comtrol SV11 card driver
*
* This is a slightly odd Z85230 synchronous driver. All you need to
* know basically is
*
* Its a genuine Z85230
*
* It supports DMA using two DMA channels in SYNC mode. The driver doesn't
* use these facilities
*
* The control port is at io+1, the data at io+3 and turning off the DMA
* is done by writing 0 to io+4
*
* The hardware does the bus handling to avoid the need for delays between
* touching control registers.
*
* Port B isn't wired (why - beats me)
*
* Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/net.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/if_arp.h>
#include <linux/delay.h>
#include <linux/hdlc.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <net/arp.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <asm/byteorder.h>
#include "z85230.h"
static int dma;
/* Network driver support routines
*/
static inline struct z8530_dev *dev_to_sv(struct net_device *dev)
{
return (struct z8530_dev *)dev_to_hdlc(dev)->priv;
}
/* Frame receive. Simple for our card as we do HDLC and there
* is no funny garbage involved
*/
static void hostess_input(struct z8530_channel *c, struct sk_buff *skb)
{
/* Drop the CRC - it's not a good idea to try and negotiate it ;) */
skb_trim(skb, skb->len - 2);
skb->protocol = hdlc_type_trans(skb, c->netdevice);
skb_reset_mac_header(skb);
skb->dev = c->netdevice;
/* Send it to the PPP layer. We don't have time to process
* it right now.
*/
netif_rx(skb);
}
/* We've been placed in the UP state
*/
static int hostess_open(struct net_device *d)
{
struct z8530_dev *sv11 = dev_to_sv(d);
int err = -1;
/* Link layer up
*/
switch (dma) {
case 0:
err = z8530_sync_open(d, &sv11->chanA);
break;
case 1:
err = z8530_sync_dma_open(d, &sv11->chanA);
break;
case 2:
err = z8530_sync_txdma_open(d, &sv11->chanA);
break;
}
if (err)
return err;
err = hdlc_open(d);
if (err) {
switch (dma) {
case 0:
z8530_sync_close(d, &sv11->chanA);
break;
case 1:
z8530_sync_dma_close(d, &sv11->chanA);
break;
case 2:
z8530_sync_txdma_close(d, &sv11->chanA);
break;
}
return err;
}
sv11->chanA.rx_function = hostess_input;
/*
* Go go go
*/
netif_start_queue(d);
return 0;
}
static int hostess_close(struct net_device *d)
{
struct z8530_dev *sv11 = dev_to_sv(d);
/* Discard new frames
*/
sv11->chanA.rx_function = z8530_null_rx;
hdlc_close(d);
netif_stop_queue(d);
switch (dma) {
case 0:
z8530_sync_close(d, &sv11->chanA);
break;
case 1:
z8530_sync_dma_close(d, &sv11->chanA);
break;
case 2:
z8530_sync_txdma_close(d, &sv11->chanA);
break;
}
return 0;
}
/* Passed network frames, fire them downwind.
*/
static netdev_tx_t hostess_queue_xmit(struct sk_buff *skb,
struct net_device *d)
{
return z8530_queue_xmit(&dev_to_sv(d)->chanA, skb);
}
static int hostess_attach(struct net_device *dev, unsigned short encoding,
unsigned short parity)
{
if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
return 0;
return -EINVAL;
}
/* Description block for a Comtrol Hostess SV11 card
*/
static const struct net_device_ops hostess_ops = {
.ndo_open = hostess_open,
.ndo_stop = hostess_close,
.ndo_start_xmit = hdlc_start_xmit,
.ndo_siocwandev = hdlc_ioctl,
};
static struct z8530_dev *sv11_init(int iobase, int irq)
{
struct z8530_dev *sv;
struct net_device *netdev;
/* Get the needed I/O space
*/
if (!request_region(iobase, 8, "Comtrol SV11")) {
pr_warn("I/O 0x%X already in use\n", iobase);
return NULL;
}
sv = kzalloc(sizeof(struct z8530_dev), GFP_KERNEL);
if (!sv)
goto err_kzalloc;
/* Stuff in the I/O addressing
*/
sv->active = 0;
sv->chanA.ctrlio = iobase + 1;
sv->chanA.dataio = iobase + 3;
sv->chanB.ctrlio = -1;
sv->chanB.dataio = -1;
sv->chanA.irqs = &z8530_nop;
sv->chanB.irqs = &z8530_nop;
outb(0, iobase + 4); /* DMA off */
/* We want a fast IRQ for this device. Actually we'd like an even faster
* IRQ ;) - This is one driver RtLinux is made for
*/
if (request_irq(irq, z8530_interrupt, 0,
"Hostess SV11", sv) < 0) {
pr_warn("IRQ %d already in use\n", irq);
goto err_irq;
}
sv->irq = irq;
sv->chanA.private = sv;
sv->chanA.dev = sv;
sv->chanB.dev = sv;
if (dma) {
/* You can have DMA off or 1 and 3 thats the lot
* on the Comtrol.
*/
sv->chanA.txdma = 3;
sv->chanA.rxdma = 1;
outb(0x03 | 0x08, iobase + 4); /* DMA on */
if (request_dma(sv->chanA.txdma, "Hostess SV/11 (TX)"))
goto err_txdma;
if (dma == 1)
if (request_dma(sv->chanA.rxdma, "Hostess SV/11 (RX)"))
goto err_rxdma;
}
/* Kill our private IRQ line the hostess can end up chattering
* until the configuration is set
*/
disable_irq(irq);
/* Begin normal initialise
*/
if (z8530_init(sv)) {
pr_err("Z8530 series device not found\n");
enable_irq(irq);
goto free_dma;
}
z8530_channel_load(&sv->chanB, z8530_dead_port);
if (sv->type == Z85C30)
z8530_channel_load(&sv->chanA, z8530_hdlc_kilostream);
else
z8530_channel_load(&sv->chanA, z8530_hdlc_kilostream_85230);
enable_irq(irq);
/* Now we can take the IRQ
*/
sv->chanA.netdevice = netdev = alloc_hdlcdev(sv);
if (!netdev)
goto free_dma;
dev_to_hdlc(netdev)->attach = hostess_attach;
dev_to_hdlc(netdev)->xmit = hostess_queue_xmit;
netdev->netdev_ops = &hostess_ops;
netdev->base_addr = iobase;
netdev->irq = irq;
if (register_hdlc_device(netdev)) {
pr_err("unable to register HDLC device\n");
free_netdev(netdev);
goto free_dma;
}
z8530_describe(sv, "I/O", iobase);
sv->active = 1;
return sv;
free_dma:
if (dma == 1)
free_dma(sv->chanA.rxdma);
err_rxdma:
if (dma)
free_dma(sv->chanA.txdma);
err_txdma:
free_irq(irq, sv);
err_irq:
kfree(sv);
err_kzalloc:
release_region(iobase, 8);
return NULL;
}
static void sv11_shutdown(struct z8530_dev *dev)
{
unregister_hdlc_device(dev->chanA.netdevice);
z8530_shutdown(dev);
free_irq(dev->irq, dev);
if (dma) {
if (dma == 1)
free_dma(dev->chanA.rxdma);
free_dma(dev->chanA.txdma);
}
release_region(dev->chanA.ctrlio - 1, 8);
free_netdev(dev->chanA.netdevice);
kfree(dev);
}
static int io = 0x200;
static int irq = 9;
module_param_hw(io, int, ioport, 0);
MODULE_PARM_DESC(io, "The I/O base of the Comtrol Hostess SV11 card");
module_param_hw(dma, int, dma, 0);
MODULE_PARM_DESC(dma, "Set this to 1 to use DMA1/DMA3 for TX/RX");
module_param_hw(irq, int, irq, 0);
MODULE_PARM_DESC(irq, "The interrupt line setting for the Comtrol Hostess SV11 card");
MODULE_AUTHOR("Alan Cox");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Modular driver for the Comtrol Hostess SV11");
static struct z8530_dev *sv11_unit;
static int sv11_module_init(void)
{
sv11_unit = sv11_init(io, irq);
if (!sv11_unit)
return -ENODEV;
return 0;
}
module_init(sv11_module_init);
static void sv11_module_cleanup(void)
{
if (sv11_unit)
sv11_shutdown(sv11_unit);
}
module_exit(sv11_module_cleanup);

352
drivers/net/wan/sealevel.c
View File

@ -1,352 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* Sealevel Systems 4021 driver.
*
* (c) Copyright 1999, 2001 Alan Cox
* (c) Copyright 2001 Red Hat Inc.
* Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/net.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/if_arp.h>
#include <linux/delay.h>
#include <linux/hdlc.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <net/arp.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <asm/byteorder.h>
#include "z85230.h"
struct slvl_device {
struct z8530_channel *chan;
int channel;
};
struct slvl_board {
struct slvl_device dev[2];
struct z8530_dev board;
int iobase;
};
/* Network driver support routines */
static inline struct slvl_device *dev_to_chan(struct net_device *dev)
{
return (struct slvl_device *)dev_to_hdlc(dev)->priv;
}
/* Frame receive. Simple for our card as we do HDLC and there
* is no funny garbage involved
*/
static void sealevel_input(struct z8530_channel *c, struct sk_buff *skb)
{
/* Drop the CRC - it's not a good idea to try and negotiate it ;) */
skb_trim(skb, skb->len - 2);
skb->protocol = hdlc_type_trans(skb, c->netdevice);
skb_reset_mac_header(skb);
skb->dev = c->netdevice;
netif_rx(skb);
}
/* We've been placed in the UP state */
static int sealevel_open(struct net_device *d)
{
struct slvl_device *slvl = dev_to_chan(d);
int err = -1;
int unit = slvl->channel;
/* Link layer up. */
switch (unit) {
case 0:
err = z8530_sync_dma_open(d, slvl->chan);
break;
case 1:
err = z8530_sync_open(d, slvl->chan);
break;
}
if (err)
return err;
err = hdlc_open(d);
if (err) {
switch (unit) {
case 0:
z8530_sync_dma_close(d, slvl->chan);
break;
case 1:
z8530_sync_close(d, slvl->chan);
break;
}
return err;
}
slvl->chan->rx_function = sealevel_input;
netif_start_queue(d);
return 0;
}
static int sealevel_close(struct net_device *d)
{
struct slvl_device *slvl = dev_to_chan(d);
int unit = slvl->channel;
/* Discard new frames */
slvl->chan->rx_function = z8530_null_rx;
hdlc_close(d);
netif_stop_queue(d);
switch (unit) {
case 0:
z8530_sync_dma_close(d, slvl->chan);
break;
case 1:
z8530_sync_close(d, slvl->chan);
break;
}
return 0;
}
/* Passed network frames, fire them downwind. */
static netdev_tx_t sealevel_queue_xmit(struct sk_buff *skb,
struct net_device *d)
{
return z8530_queue_xmit(dev_to_chan(d)->chan, skb);
}
static int sealevel_attach(struct net_device *dev, unsigned short encoding,
unsigned short parity)
{
if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
return 0;
return -EINVAL;
}
static const struct net_device_ops sealevel_ops = {
.ndo_open = sealevel_open,
.ndo_stop = sealevel_close,
.ndo_start_xmit = hdlc_start_xmit,
.ndo_siocwandev = hdlc_ioctl,
};
static int slvl_setup(struct slvl_device *sv, int iobase, int irq)
{
struct net_device *dev = alloc_hdlcdev(sv);
if (!dev)
return -1;
dev_to_hdlc(dev)->attach = sealevel_attach;
dev_to_hdlc(dev)->xmit = sealevel_queue_xmit;
dev->netdev_ops = &sealevel_ops;
dev->base_addr = iobase;
dev->irq = irq;
if (register_hdlc_device(dev)) {
pr_err("unable to register HDLC device\n");
free_netdev(dev);
return -1;
}
sv->chan->netdevice = dev;
return 0;
}
/* Allocate and setup Sealevel board. */
static __init struct slvl_board *slvl_init(int iobase, int irq,
int txdma, int rxdma, int slow)
{
struct z8530_dev *dev;
struct slvl_board *b;
/* Get the needed I/O space */
if (!request_region(iobase, 8, "Sealevel 4021")) {
pr_warn("I/O 0x%X already in use\n", iobase);
return NULL;
}
b = kzalloc(sizeof(struct slvl_board), GFP_KERNEL);
if (!b)
goto err_kzalloc;
b->dev[0].chan = &b->board.chanA;
b->dev[0].channel = 0;
b->dev[1].chan = &b->board.chanB;
b->dev[1].channel = 1;
dev = &b->board;
/* Stuff in the I/O addressing */
dev->active = 0;
b->iobase = iobase;
/* Select 8530 delays for the old board */
if (slow)
iobase |= Z8530_PORT_SLEEP;
dev->chanA.ctrlio = iobase + 1;
dev->chanA.dataio = iobase;
dev->chanB.ctrlio = iobase + 3;
dev->chanB.dataio = iobase + 2;
dev->chanA.irqs = &z8530_nop;
dev->chanB.irqs = &z8530_nop;
/* Assert DTR enable DMA */
outb(3 | (1 << 7), b->iobase + 4);
/* We want a fast IRQ for this device. Actually we'd like an even faster
* IRQ ;) - This is one driver RtLinux is made for
*/
if (request_irq(irq, z8530_interrupt, 0,
"SeaLevel", dev) < 0) {
pr_warn("IRQ %d already in use\n", irq);
goto err_request_irq;
}
dev->irq = irq;
dev->chanA.private = &b->dev[0];
dev->chanB.private = &b->dev[1];
dev->chanA.dev = dev;
dev->chanB.dev = dev;
dev->chanA.txdma = 3;
dev->chanA.rxdma = 1;
if (request_dma(dev->chanA.txdma, "SeaLevel (TX)"))
goto err_dma_tx;
if (request_dma(dev->chanA.rxdma, "SeaLevel (RX)"))
goto err_dma_rx;
disable_irq(irq);
/* Begin normal initialise */
if (z8530_init(dev) != 0) {
pr_err("Z8530 series device not found\n");
enable_irq(irq);
goto free_hw;
}
if (dev->type == Z85C30) {
z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream);
z8530_channel_load(&dev->chanB, z8530_hdlc_kilostream);
} else {
z8530_channel_load(&dev->chanA, z8530_hdlc_kilostream_85230);
z8530_channel_load(&dev->chanB, z8530_hdlc_kilostream_85230);
}
/* Now we can take the IRQ */
enable_irq(irq);
if (slvl_setup(&b->dev[0], iobase, irq))
goto free_hw;
if (slvl_setup(&b->dev[1], iobase, irq))
goto free_netdev0;
z8530_describe(dev, "I/O", iobase);
dev->active = 1;
return b;
free_netdev0:
unregister_hdlc_device(b->dev[0].chan->netdevice);
free_netdev(b->dev[0].chan->netdevice);
free_hw:
free_dma(dev->chanA.rxdma);
err_dma_rx:
free_dma(dev->chanA.txdma);
err_dma_tx:
free_irq(irq, dev);
err_request_irq:
kfree(b);
err_kzalloc:
release_region(iobase, 8);
return NULL;
}
static void __exit slvl_shutdown(struct slvl_board *b)
{
int u;
z8530_shutdown(&b->board);
for (u = 0; u < 2; u++) {
struct net_device *d = b->dev[u].chan->netdevice;
unregister_hdlc_device(d);
free_netdev(d);
}
free_irq(b->board.irq, &b->board);
free_dma(b->board.chanA.rxdma);
free_dma(b->board.chanA.txdma);
/* DMA off on the card, drop DTR */
outb(0, b->iobase);
release_region(b->iobase, 8);
kfree(b);
}
static int io = 0x238;
static int txdma = 1;
static int rxdma = 3;
static int irq = 5;
static bool slow;
module_param_hw(io, int, ioport, 0);
MODULE_PARM_DESC(io, "The I/O base of the Sealevel card");
module_param_hw(txdma, int, dma, 0);
MODULE_PARM_DESC(txdma, "Transmit DMA channel");
module_param_hw(rxdma, int, dma, 0);
MODULE_PARM_DESC(rxdma, "Receive DMA channel");
module_param_hw(irq, int, irq, 0);
MODULE_PARM_DESC(irq, "The interrupt line setting for the SeaLevel card");
module_param(slow, bool, 0);
MODULE_PARM_DESC(slow, "Set this for an older Sealevel card such as the 4012");
MODULE_AUTHOR("Alan Cox");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Modular driver for the SeaLevel 4021");
static struct slvl_board *slvl_unit;
static int __init slvl_init_module(void)
{
slvl_unit = slvl_init(io, irq, txdma, rxdma, slow);
return slvl_unit ? 0 : -ENODEV;
}
static void __exit slvl_cleanup_module(void)
{
if (slvl_unit)
slvl_shutdown(slvl_unit);
}
module_init(slvl_init_module);
module_exit(slvl_cleanup_module);

1641
drivers/net/wan/z85230.c
View File

File diff suppressed because it is too large Load Diff

407
drivers/net/wan/z85230.h
View File

@ -1,407 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Description of Z8530 Z85C30 and Z85230 communications chips
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
*/
#ifndef _Z8530_H
#define _Z8530_H
#include <linux/tty.h>
#include <linux/interrupt.h>
/* Conversion routines to/from brg time constants from/to bits
* per second.
*/
#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
/* The Zilog register set */
#define FLAG 0x7e
/* Write Register 0 */
#define R0 0 /* Register selects */
#define R1 1
#define R2 2
#define R3 3
#define R4 4
#define R5 5
#define R6 6
#define R7 7
#define R8 8
#define R9 9
#define R10 10
#define R11 11
#define R12 12
#define R13 13
#define R14 14
#define R15 15
#define RPRIME 16 /* Indicate a prime register access on 230 */
#define NULLCODE 0 /* Null Code */
#define POINT_HIGH 0x8 /* Select upper half of registers */
#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
#define SEND_ABORT 0x18 /* HDLC Abort */
#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
#define RES_Tx_P 0x28 /* Reset TxINT Pending */
#define ERR_RES 0x30 /* Error Reset */
#define RES_H_IUS 0x38 /* Reset highest IUS */
#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
#define RES_EOM_L 0xC0 /* Reset EOM latch */
/* Write Register 1 */
#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
#define TxINT_ENAB 0x2 /* Tx Int Enable */
#define PAR_SPEC 0x4 /* Parity is special condition */
#define RxINT_DISAB 0 /* Rx Int Disable */
#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
#define INT_ERR_Rx 0x18 /* Int on error only */
#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
/* Write Register #2 (Interrupt Vector) */
/* Write Register 3 */
#define RxENABLE 0x1 /* Rx Enable */
#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
#define ENT_HM 0x10 /* Enter Hunt Mode */
#define AUTO_ENAB 0x20 /* Auto Enables */
#define Rx5 0x0 /* Rx 5 Bits/Character */
#define Rx7 0x40 /* Rx 7 Bits/Character */
#define Rx6 0x80 /* Rx 6 Bits/Character */
#define Rx8 0xc0 /* Rx 8 Bits/Character */
/* Write Register 4 */
#define PAR_ENA 0x1 /* Parity Enable */
#define PAR_EVEN 0x2 /* Parity Even/Odd* */
#define SYNC_ENAB 0 /* Sync Modes Enable */
#define SB1 0x4 /* 1 stop bit/char */
#define SB15 0x8 /* 1.5 stop bits/char */
#define SB2 0xc /* 2 stop bits/char */
#define MONSYNC 0 /* 8 Bit Sync character */
#define BISYNC 0x10 /* 16 bit sync character */
#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
#define EXTSYNC 0x30 /* External Sync Mode */
#define X1CLK 0x0 /* x1 clock mode */
#define X16CLK 0x40 /* x16 clock mode */
#define X32CLK 0x80 /* x32 clock mode */
#define X64CLK 0xC0 /* x64 clock mode */
/* Write Register 5 */
#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
#define RTS 0x2 /* RTS */
#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
#define TxENAB 0x8 /* Tx Enable */
#define SND_BRK 0x10 /* Send Break */
#define Tx5 0x0 /* Tx 5 bits (or less)/character */
#define Tx7 0x20 /* Tx 7 bits/character */
#define Tx6 0x40 /* Tx 6 bits/character */
#define Tx8 0x60 /* Tx 8 bits/character */
#define DTR 0x80 /* DTR */
/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
/* Write Register 8 (transmit buffer) */
/* Write Register 9 (Master interrupt control) */
#define VIS 1 /* Vector Includes Status */
#define NV 2 /* No Vector */
#define DLC 4 /* Disable Lower Chain */
#define MIE 8 /* Master Interrupt Enable */
#define STATHI 0x10 /* Status high */
#define NORESET 0 /* No reset on write to R9 */
#define CHRB 0x40 /* Reset channel B */
#define CHRA 0x80 /* Reset channel A */
#define FHWRES 0xc0 /* Force hardware reset */
/* Write Register 10 (misc control bits) */
#define BIT6 1 /* 6 bit/8bit sync */
#define LOOPMODE 2 /* SDLC Loop mode */
#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
#define MARKIDLE 8 /* Mark/flag on idle */
#define GAOP 0x10 /* Go active on poll */
#define NRZ 0 /* NRZ mode */
#define NRZI 0x20 /* NRZI mode */
#define FM1 0x40 /* FM1 (transition = 1) */
#define FM0 0x60 /* FM0 (transition = 0) */
#define CRCPS 0x80 /* CRC Preset I/O */
/* Write Register 11 (Clock Mode control) */
#define TRxCXT 0 /* TRxC = Xtal output */
#define TRxCTC 1 /* TRxC = Transmit clock */
#define TRxCBR 2 /* TRxC = BR Generator Output */
#define TRxCDP 3 /* TRxC = DPLL output */
#define TRxCOI 4 /* TRxC O/I */
#define TCRTxCP 0 /* Transmit clock = RTxC pin */
#define TCTRxCP 8 /* Transmit clock = TRxC pin */
#define TCBR 0x10 /* Transmit clock = BR Generator output */
#define TCDPLL 0x18 /* Transmit clock = DPLL output */
#define RCRTxCP 0 /* Receive clock = RTxC pin */
#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
#define RCBR 0x40 /* Receive clock = BR Generator output */
#define RCDPLL 0x60 /* Receive clock = DPLL output */
#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
/* Write Register 12 (lower byte of baud rate generator time constant) */
/* Write Register 13 (upper byte of baud rate generator time constant) */
/* Write Register 14 (Misc control bits) */
#define BRENABL 1 /* Baud rate generator enable */
#define BRSRC 2 /* Baud rate generator source */
#define DTRREQ 4 /* DTR/Request function */
#define AUTOECHO 8 /* Auto Echo */
#define LOOPBAK 0x10 /* Local loopback */
#define SEARCH 0x20 /* Enter search mode */
#define RMC 0x40 /* Reset missing clock */
#define DISDPLL 0x60 /* Disable DPLL */
#define SSBR 0x80 /* Set DPLL source = BR generator */
#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
#define SFMM 0xc0 /* Set FM mode */
#define SNRZI 0xe0 /* Set NRZI mode */
/* Write Register 15 (external/status interrupt control) */
#define PRIME 1 /* R5' etc register access (Z85C30/230 only) */
#define ZCIE 2 /* Zero count IE */
#define FIFOE 4 /* Z85230 only */
#define DCDIE 8 /* DCD IE */
#define SYNCIE 0x10 /* Sync/hunt IE */
#define CTSIE 0x20 /* CTS IE */
#define TxUIE 0x40 /* Tx Underrun/EOM IE */
#define BRKIE 0x80 /* Break/Abort IE */
/* Read Register 0 */
#define Rx_CH_AV 0x1 /* Rx Character Available */
#define ZCOUNT 0x2 /* Zero count */
#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
#define DCD 0x8 /* DCD */
#define SYNC_HUNT 0x10 /* Sync/hunt */
#define CTS 0x20 /* CTS */
#define TxEOM 0x40 /* Tx underrun */
#define BRK_ABRT 0x80 /* Break/Abort */
/* Read Register 1 */
#define ALL_SNT 0x1 /* All sent */
/* Residue Data for 8 Rx bits/char programmed */
#define RES3 0x8 /* 0/3 */
#define RES4 0x4 /* 0/4 */
#define RES5 0xc /* 0/5 */
#define RES6 0x2 /* 0/6 */
#define RES7 0xa /* 0/7 */
#define RES8 0x6 /* 0/8 */
#define RES18 0xe /* 1/8 */
#define RES28 0x0 /* 2/8 */
/* Special Rx Condition Interrupts */
#define PAR_ERR 0x10 /* Parity error */
#define Rx_OVR 0x20 /* Rx Overrun Error */
#define CRC_ERR 0x40 /* CRC/Framing Error */
#define END_FR 0x80 /* End of Frame (SDLC) */
/* Read Register 2 (channel b only) - Interrupt vector */
/* Read Register 3 (interrupt pending register) ch a only */
#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
#define CHBTxIP 0x2 /* Channel B Tx IP */
#define CHBRxIP 0x4 /* Channel B Rx IP */
#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
#define CHATxIP 0x10 /* Channel A Tx IP */
#define CHARxIP 0x20 /* Channel A Rx IP */
/* Read Register 8 (receive data register) */
/* Read Register 10 (misc status bits) */
#define ONLOOP 2 /* On loop */
#define LOOPSEND 0x10 /* Loop sending */
#define CLK2MIS 0x40 /* Two clocks missing */
#define CLK1MIS 0x80 /* One clock missing */
/* Read Register 12 (lower byte of baud rate generator constant) */
/* Read Register 13 (upper byte of baud rate generator constant) */
/* Read Register 15 (value of WR 15) */
/*
* Interrupt handling functions for this SCC
*/
struct z8530_channel;
struct z8530_irqhandler
{
void (*rx)(struct z8530_channel *);
void (*tx)(struct z8530_channel *);
void (*status)(struct z8530_channel *);
};
/*
* A channel of the Z8530
*/
struct z8530_channel
{
struct z8530_irqhandler *irqs; /* IRQ handlers */
/*
* Synchronous
*/
u16 count; /* Buyes received */
u16 max; /* Most we can receive this frame */
u16 mtu; /* MTU of the device */
u8 *dptr; /* Pointer into rx buffer */
struct sk_buff *skb; /* Buffer dptr points into */
struct sk_buff *skb2; /* Pending buffer */
u8 status; /* Current DCD */
u8 dcdcheck; /* which bit to check for line */
u8 sync; /* Set if in sync mode */
u8 regs[32]; /* Register map for the chip */
u8 pendregs[32]; /* Pending register values */
struct sk_buff *tx_skb; /* Buffer being transmitted */
struct sk_buff *tx_next_skb; /* Next transmit buffer */
u8 *tx_ptr; /* Byte pointer into the buffer */
u8 *tx_next_ptr; /* Next pointer to use */
u8 *tx_dma_buf[2]; /* TX flip buffers for DMA */
u8 tx_dma_used; /* Flip buffer usage toggler */
u16 txcount; /* Count of bytes to transmit */
void (*rx_function)(struct z8530_channel *, struct sk_buff *);
/*
* Sync DMA
*/
u8 rxdma; /* DMA channels */
u8 txdma;
u8 rxdma_on; /* DMA active if flag set */
u8 txdma_on;
u8 dma_num; /* Buffer we are DMAing into */
u8 dma_ready; /* Is the other buffer free */
u8 dma_tx; /* TX is to use DMA */
u8 *rx_buf[2]; /* The flip buffers */
/*
* System
*/
struct z8530_dev *dev; /* Z85230 chip instance we are from */
unsigned long ctrlio; /* I/O ports */
unsigned long dataio;
/*
* For PC we encode this way.
*/
#define Z8530_PORT_SLEEP 0x80000000
#define Z8530_PORT_OF(x) ((x)&0xFFFF)
u32 rx_overrun; /* Overruns - not done yet */
u32 rx_crc_err;
/*
* Bound device pointers
*/
void *private; /* For our owner */
struct net_device *netdevice; /* Network layer device */
spinlock_t *lock; /* Device lock */
};
/*
* Each Z853x0 device.
*/
struct z8530_dev
{
char *name; /* Device instance name */
struct z8530_channel chanA; /* SCC channel A */
struct z8530_channel chanB; /* SCC channel B */
int type;
#define Z8530 0 /* NMOS dinosaur */
#define Z85C30 1 /* CMOS - better */
#define Z85230 2 /* CMOS with real FIFO */
int irq; /* Interrupt for the device */
int active; /* Soft interrupt enable - the Mac doesn't
always have a hard disable on its 8530s... */
spinlock_t lock;
};
/*
* Functions
*/
extern u8 z8530_dead_port[];
extern u8 z8530_hdlc_kilostream_85230[];
extern u8 z8530_hdlc_kilostream[];
irqreturn_t z8530_interrupt(int, void *);
void z8530_describe(struct z8530_dev *, char *mapping, unsigned long io);
int z8530_init(struct z8530_dev *);
int z8530_shutdown(struct z8530_dev *);
int z8530_sync_open(struct net_device *, struct z8530_channel *);
int z8530_sync_close(struct net_device *, struct z8530_channel *);
int z8530_sync_dma_open(struct net_device *, struct z8530_channel *);
int z8530_sync_dma_close(struct net_device *, struct z8530_channel *);
int z8530_sync_txdma_open(struct net_device *, struct z8530_channel *);
int z8530_sync_txdma_close(struct net_device *, struct z8530_channel *);
int z8530_channel_load(struct z8530_channel *, u8 *);
netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb);
void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb);
/*
* Standard interrupt vector sets
*/
extern struct z8530_irqhandler z8530_sync, z8530_async, z8530_nop;
/*
* Asynchronous Interfacing
*/
/*
* The size of the serial xmit buffer is 1 page, or 4096 bytes
*/
#define SERIAL_XMIT_SIZE 4096
#define WAKEUP_CHARS 256
/*
* Events are used to schedule things to happen at timer-interrupt
* time, instead of at rs interrupt time.
*/
#define RS_EVENT_WRITE_WAKEUP 0
/* Internal flags used only by kernel/chr_drv/serial.c */
#define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
#define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
#define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
#define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
#define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
#define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
#define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
#endif /* !(_Z8530_H) */

47
include/uapi/linux/atm_zatm.h
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@ -1,47 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/* atm_zatm.h - Driver-specific declarations of the ZATM driver (for use by
driver-specific utilities) */
/* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
#ifndef LINUX_ATM_ZATM_H
#define LINUX_ATM_ZATM_H
/*
* Note: non-kernel programs including this file must also include
* sys/types.h for struct timeval
*/
#include <linux/atmapi.h>
#include <linux/atmioc.h>
#define ZATM_GETPOOL _IOW('a',ATMIOC_SARPRV+1,struct atmif_sioc)
/* get pool statistics */
#define ZATM_GETPOOLZ _IOW('a',ATMIOC_SARPRV+2,struct atmif_sioc)
/* get statistics and zero */
#define ZATM_SETPOOL _IOW('a',ATMIOC_SARPRV+3,struct atmif_sioc)
/* set pool parameters */
struct zatm_pool_info {
int ref_count; /* free buffer pool usage counters */
int low_water,high_water; /* refill parameters */
int rqa_count,rqu_count; /* queue condition counters */
int offset,next_off; /* alignment optimizations: offset */
int next_cnt,next_thres; /* repetition counter and threshold */
};
struct zatm_pool_req {
int pool_num; /* pool number */
struct zatm_pool_info info; /* actual information */
};
#define ZATM_OAM_POOL 0 /* free buffer pool for OAM cells */
#define ZATM_AAL0_POOL 1 /* free buffer pool for AAL0 cells */
#define ZATM_AAL5_POOL_BASE 2 /* first AAL5 free buffer pool */
#define ZATM_LAST_POOL ZATM_AAL5_POOL_BASE+10 /* max. 64 kB */
#define ZATM_TIMER_HISTORY_SIZE 16 /* number of timer adjustments to
record; must be 2^n */
#endif