pinctrl: renesas: Updates for v6.6
- Use the new devm_clk_get_enabled() helper. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZMOrCgAKCRCKwlD9ZEnx cCz/AQC9R6tDDnUVANXXgDIQgqZU/tOX19mLsnOa+m2e2UsrmwEA+u1HdgXwtXpq VvjtCN/bG1jJVNDlK1/qKJnytsU+sAc= =QdlY -----END PGP SIGNATURE----- Merge tag 'renesas-pinctrl-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.6 - Use the new devm_clk_get_enabled() helper. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
commit
046d354675
@ -145,7 +145,6 @@ struct rzg2l_pinctrl {
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const struct rzg2l_pinctrl_data *data;
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void __iomem *base;
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struct device *dev;
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struct clk *clk;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range gpio_range;
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@ -250,6 +249,7 @@ static int rzg2l_map_add_config(struct pinctrl_map *map,
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static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np,
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struct device_node *parent,
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struct pinctrl_map **map,
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unsigned int *num_maps,
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unsigned int *index)
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@ -267,6 +267,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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struct property *prop;
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int ret, gsel, fsel;
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const char **pin_fn;
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const char *name;
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const char *pin;
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pinmux = of_find_property(np, "pinmux", NULL);
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@ -350,8 +351,19 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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psel_val[i] = MUX_FUNC(value);
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}
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if (parent) {
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name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
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parent, np);
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if (!name) {
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ret = -ENOMEM;
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goto done;
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}
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} else {
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name = np->name;
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}
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/* Register a single pin group listing all the pins we read from DT */
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gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
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gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
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if (gsel < 0) {
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ret = gsel;
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goto done;
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@ -361,17 +373,16 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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* Register a single group function where the 'data' is an array PSEL
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* register values read from DT.
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*/
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pin_fn[0] = np->name;
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fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
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psel_val);
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pin_fn[0] = name;
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fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
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if (fsel < 0) {
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ret = fsel;
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goto remove_group;
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}
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maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
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maps[idx].data.mux.group = np->name;
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maps[idx].data.mux.function = np->name;
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maps[idx].data.mux.group = name;
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maps[idx].data.mux.function = name;
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idx++;
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dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
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@ -418,7 +429,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
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index = 0;
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for_each_child_of_node(np, child) {
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ret = rzg2l_dt_subnode_to_map(pctldev, child, map,
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ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,
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num_maps, &index);
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if (ret < 0) {
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of_node_put(child);
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@ -427,7 +438,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
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}
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if (*num_maps == 0) {
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ret = rzg2l_dt_subnode_to_map(pctldev, np, map,
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ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
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num_maps, &index);
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if (ret < 0)
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goto done;
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@ -1459,14 +1470,10 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
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return 0;
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}
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static void rzg2l_pinctrl_clk_disable(void *data)
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{
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clk_disable_unprepare(data);
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}
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static int rzg2l_pinctrl_probe(struct platform_device *pdev)
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{
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struct rzg2l_pinctrl *pctrl;
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struct clk *clk;
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int ret;
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BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT >
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@ -1489,33 +1496,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
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if (IS_ERR(pctrl->base))
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return PTR_ERR(pctrl->base);
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pctrl->clk = devm_clk_get(pctrl->dev, NULL);
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if (IS_ERR(pctrl->clk)) {
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ret = PTR_ERR(pctrl->clk);
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dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
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return ret;
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}
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clk = devm_clk_get_enabled(pctrl->dev, NULL);
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if (IS_ERR(clk))
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return dev_err_probe(pctrl->dev, PTR_ERR(clk),
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"failed to enable GPIO clk\n");
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spin_lock_init(&pctrl->lock);
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spin_lock_init(&pctrl->bitmap_lock);
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platform_set_drvdata(pdev, pctrl);
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ret = clk_prepare_enable(pctrl->clk);
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if (ret) {
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dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret);
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return ret;
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}
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ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable,
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pctrl->clk);
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if (ret) {
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dev_err(pctrl->dev,
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"failed to register GPIO clk disable action, %i\n",
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ret);
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return ret;
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}
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ret = rzg2l_pinctrl_register(pctrl);
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if (ret)
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return ret;
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@ -119,7 +119,6 @@ struct rzv2m_pinctrl {
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const struct rzv2m_pinctrl_data *data;
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void __iomem *base;
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struct device *dev;
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struct clk *clk;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range gpio_range;
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@ -210,6 +209,7 @@ static int rzv2m_map_add_config(struct pinctrl_map *map,
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static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np,
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struct device_node *parent,
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struct pinctrl_map **map,
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unsigned int *num_maps,
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unsigned int *index)
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@ -227,6 +227,7 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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struct property *prop;
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int ret, gsel, fsel;
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const char **pin_fn;
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const char *name;
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const char *pin;
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pinmux = of_find_property(np, "pinmux", NULL);
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@ -310,8 +311,19 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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psel_val[i] = MUX_FUNC(value);
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}
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if (parent) {
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name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
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parent, np);
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if (!name) {
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ret = -ENOMEM;
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goto done;
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}
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} else {
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name = np->name;
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}
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/* Register a single pin group listing all the pins we read from DT */
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gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
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gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
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if (gsel < 0) {
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ret = gsel;
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goto done;
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@ -321,17 +333,16 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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* Register a single group function where the 'data' is an array PSEL
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* register values read from DT.
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*/
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pin_fn[0] = np->name;
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fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
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psel_val);
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pin_fn[0] = name;
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fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
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if (fsel < 0) {
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ret = fsel;
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goto remove_group;
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}
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maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
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maps[idx].data.mux.group = np->name;
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maps[idx].data.mux.function = np->name;
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maps[idx].data.mux.group = name;
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maps[idx].data.mux.function = name;
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idx++;
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dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
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@ -378,7 +389,7 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
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index = 0;
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for_each_child_of_node(np, child) {
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ret = rzv2m_dt_subnode_to_map(pctldev, child, map,
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ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map,
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num_maps, &index);
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if (ret < 0) {
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of_node_put(child);
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@ -387,7 +398,7 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
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}
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if (*num_maps == 0) {
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ret = rzv2m_dt_subnode_to_map(pctldev, np, map,
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ret = rzv2m_dt_subnode_to_map(pctldev, np, NULL, map,
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num_maps, &index);
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if (ret < 0)
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goto done;
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@ -1028,14 +1039,10 @@ static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl)
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return 0;
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}
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static void rzv2m_pinctrl_clk_disable(void *data)
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{
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clk_disable_unprepare(data);
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}
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static int rzv2m_pinctrl_probe(struct platform_device *pdev)
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{
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struct rzv2m_pinctrl *pctrl;
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struct clk *clk;
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int ret;
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pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
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@ -1052,32 +1059,15 @@ static int rzv2m_pinctrl_probe(struct platform_device *pdev)
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if (IS_ERR(pctrl->base))
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return PTR_ERR(pctrl->base);
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pctrl->clk = devm_clk_get(pctrl->dev, NULL);
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if (IS_ERR(pctrl->clk)) {
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ret = PTR_ERR(pctrl->clk);
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dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
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return ret;
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}
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clk = devm_clk_get_enabled(pctrl->dev, NULL);
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if (IS_ERR(clk))
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return dev_err_probe(pctrl->dev, PTR_ERR(clk),
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"failed to enable GPIO clk\n");
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spin_lock_init(&pctrl->lock);
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platform_set_drvdata(pdev, pctrl);
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ret = clk_prepare_enable(pctrl->clk);
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if (ret) {
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dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret);
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return ret;
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}
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ret = devm_add_action_or_reset(&pdev->dev, rzv2m_pinctrl_clk_disable,
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pctrl->clk);
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if (ret) {
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dev_err(pctrl->dev,
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"failed to register GPIO clk disable action, %i\n",
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ret);
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return ret;
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}
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ret = rzv2m_pinctrl_register(pctrl);
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if (ret)
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return ret;
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