From dd8314739a1ff8ed081d3a06f5f87045f7384636 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 22 Feb 2023 13:24:22 +0000 Subject: [PATCH 1/8] MIPS: Remove DMA_PERDEV_COHERENT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As now we are always managing DMA coherence on per dev bias, there is no need to have such option. And it's not selected by any platform. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 37072e15b263..a1170f0a0c04 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1080,11 +1080,6 @@ config FW_CFE config ARCH_SUPPORTS_UPROBES bool -config DMA_PERDEV_COHERENT - bool - select ARCH_HAS_SETUP_DMA_OPS - select DMA_NONCOHERENT - config DMA_NONCOHERENT bool # From fea8826d5fdc4ff5c93e883a738597129614039c Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Mon, 27 Feb 2023 18:46:13 +0000 Subject: [PATCH 2/8] MIPS: smp-cps: Don't rely on CP0_CMGCRBASE CP0_CMGCRBASE is not always available on CPS enabled system such as early proAptiv. For early SMP bring up where we can't safely access memeory, we patch the entry of CPS NMI vector to inject CMGCR address directly into register during early core bringup. For VPE bringup as the core is already coherenct at that point we just read the variable to obtain the address. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/smp-cps.h | 4 ++++ arch/mips/kernel/cps-vec.S | 35 ++++++++++++++------------------- arch/mips/kernel/smp-cps.c | 2 ++ 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 7e5b9411faee..22a572b70fe3 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -7,6 +7,8 @@ #ifndef __MIPS_ASM_SMP_CPS_H__ #define __MIPS_ASM_SMP_CPS_H__ +#define CPS_ENTRY_PATCH_INSNS 6 + #ifndef __ASSEMBLY__ struct vpe_boot_config { @@ -30,6 +32,8 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); extern void mips_cps_pm_save(void); extern void mips_cps_pm_restore(void); +extern void *mips_cps_core_entry_patch_end; + #ifdef CONFIG_MIPS_CPS extern bool mips_cps_smp_in_use(void); diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 975343240148..8ef492da827f 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -13,6 +13,7 @@ #include #include #include +#include #define GCR_CPC_BASE_OFS 0x0088 #define GCR_CL_COHERENCE_OFS 0x2008 @@ -80,25 +81,20 @@ nop .endm - /* Calculate an uncached address for the CM GCRs */ - .macro cmgcrb dest - .set push - .set noat - MFC0 $1, CP0_CMGCRBASE - PTR_SLL $1, $1, 4 - PTR_LI \dest, UNCAC_BASE - PTR_ADDU \dest, \dest, $1 - .set pop - .endm .balign 0x1000 LEAF(mips_cps_core_entry) /* - * These first 4 bytes will be patched by cps_smp_setup to load the - * CCA to use into register s0. + * These first several instructions will be patched by cps_smp_setup to load the + * CCA to use into register s0 and GCR base address to register s1. */ - .word 0 + .rept CPS_ENTRY_PATCH_INSNS + nop + .endr + + .global mips_cps_core_entry_patch_end +mips_cps_core_entry_patch_end: /* Check whether we're here due to an NMI */ mfc0 k0, CP0_STATUS @@ -121,8 +117,7 @@ not_nmi: mtc0 t0, CP0_STATUS /* Skip cache & coherence setup if we're already coherent */ - cmgcrb v1 - lw s7, GCR_CL_COHERENCE_OFS(v1) + lw s7, GCR_CL_COHERENCE_OFS(s1) bnez s7, 1f nop @@ -132,7 +127,7 @@ not_nmi: /* Enter the coherent domain */ li t0, 0xff - sw t0, GCR_CL_COHERENCE_OFS(v1) + sw t0, GCR_CL_COHERENCE_OFS(s1) ehb /* Set Kseg0 CCA to that in s0 */ @@ -305,8 +300,7 @@ LEAF(mips_cps_core_init) */ LEAF(mips_cps_get_bootcfg) /* Calculate a pointer to this cores struct core_boot_config */ - cmgcrb t0 - lw t0, GCR_CL_ID_OFS(t0) + lw t0, GCR_CL_ID_OFS(s1) li t1, COREBOOTCFG_SIZE mul t0, t0, t1 PTR_LA t1, mips_cps_core_bootcfg @@ -366,8 +360,9 @@ LEAF(mips_cps_boot_vpes) has_vp t0, 5f /* Find base address of CPC */ - cmgcrb t3 - PTR_L t1, GCR_CPC_BASE_OFS(t3) + PTR_LA t1, mips_gcr_base + PTR_L t1, 0(t1) + PTR_L t1, GCR_CPC_BASE_OFS(t1) PTR_LI t2, ~0x7fff and t1, t1, t2 PTR_LI t2, UNCAC_BASE diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index f2df0cae1b4d..4fc288bb85b9 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -162,6 +162,8 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) */ entry_code = (u32 *)&mips_cps_core_entry; uasm_i_addiu(&entry_code, 16, 0, cca); + UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); + BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); blast_dcache_range((unsigned long)&mips_cps_core_entry, (unsigned long)entry_code); bc_wback_inv((unsigned long)&mips_cps_core_entry, From 5ae7e037de566c3106c0fa951bbf35fd6370fdf6 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Mon, 27 Feb 2023 18:46:14 +0000 Subject: [PATCH 3/8] MIPS: cevt-r4k: Offset the value used to clear compare interrupt In c0_compare_int_usable we clear compare interrupt by write value just read out from counter to compare register. However sometimes if those all instructions are graduated together then it's possible that at the time compare register is written, the counter haven't progressed, thus the interrupt is triggered again. It also applies to QEMU that instructions is executed significantly faster then counter. Offset the value used to clear interrupt by one to prevent that happen. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cevt-r4k.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 32ec67c9ab67..368e8475870f 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -200,7 +200,7 @@ int c0_compare_int_usable(void) */ if (c0_compare_int_pending()) { cnt = read_c0_count(); - write_c0_compare(cnt); + write_c0_compare(cnt - 1); back_to_back_c0_hazard(); while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) if (!c0_compare_int_pending()) @@ -228,7 +228,7 @@ int c0_compare_int_usable(void) if (!c0_compare_int_pending()) return 0; cnt = read_c0_count(); - write_c0_compare(cnt); + write_c0_compare(cnt - 1); back_to_back_c0_hazard(); while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) if (!c0_compare_int_pending()) From f2b95d7a9fa43bd72d442a9df01e29274b1769b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Tue, 21 Feb 2023 12:24:34 +0300 Subject: [PATCH 4/8] mips: remove SYS_HAS_CPU_MIPS32_R1 from RALINK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All MIPS processors on the Ralink SoCs implement the MIPS32 Release 2 Architecture. Remove SYS_HAS_CPU_MIPS32_R1. Signed-off-by: Arınç ÜNAL Acked-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a1170f0a0c04..875c29246555 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -610,7 +610,6 @@ config RALINK select DMA_NONCOHERENT select IRQ_MIPS_CPU select USE_OF - select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN From 27fd82726995bd75b68df9ce6a1eda8f6b3ad498 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Tue, 21 Feb 2023 12:24:35 +0300 Subject: [PATCH 5/8] mips: ralink: make SOC_MT7621 select PINCTRL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, out of every Ralink SoC, only the dt-binding of the MT7621 SoC uses pinctrl. Because of this, PINCTRL is not selected at all. Make SOC_MT7621 select PINCTRL. Remove PINCTRL_MT7621, enabling it for the MT7621 SoC will be handled under the PINCTRL_MT7621 option. Signed-off-by: Arınç ÜNAL Acked-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 06031796c87b..83e61e147b90 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -54,7 +54,7 @@ choice select HAVE_PCI select PCI_DRIVERS_GENERIC select SOC_BUS - select PINCTRL_MT7621 + select PINCTRL help The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc From 79f76e574c3690261d6165f008b7054e54c6dca9 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Tue, 14 Feb 2023 11:39:33 +0100 Subject: [PATCH 6/8] mips: dts: ralink: mt7621: rename watchdog node from 'wdt' into 'watchdog' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Watchdog nodes must use 'watchdog' for node name. When a 'make dtbs_check' is performed the following warning appears: wdt@100: $nodename:0: 'wdt@100' does not match '^watchdog(@.*|-[0-9a-f])?$' Fix this warning up properly renaming the node into 'watchdog'. Reviewed-by: Arınç ÜNAL Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Sergio Paracuellos Acked-by: Guenter Roeck Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 290d47fbcfbb..c16295d27fa6 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -70,7 +70,7 @@ "250m", "270m"; }; - wdt: wdt@100 { + wdt: watchdog@100 { compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x100>; }; From 70f864d1084734f8816a247c24e6876d2dfb5f89 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Tue, 14 Feb 2023 11:39:34 +0100 Subject: [PATCH 7/8] mips: dts: ralink: mt7621: add phandle to system controller node for watchdog MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To allow to access system controller registers from watchdog driver code add a phandle in the watchdog 'wdt' node. This avoid using arch dependent operations in driver code. Reviewed-by: Arınç ÜNAL Signed-off-by: Sergio Paracuellos Acked-by: Guenter Roeck Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index c16295d27fa6..7caed0d14f11 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -73,6 +73,7 @@ wdt: watchdog@100 { compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x100>; + mediatek,sysctl = <&sysc>; }; gpio: gpio@600 { From 1a2c73f4834dd79e4f2c590ac75358fb44137650 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 28 Feb 2023 19:34:59 +0000 Subject: [PATCH 8/8] MIPS: Workaround clang inline compat branch issue Clang is unable to handle the situation that a chunk of inline assembly ends with a compat branch instruction and then compiler generates another control transfer instruction immediately after this compat branch. The later instruction will end up in forbidden slot and cause exception. Workaround by add a option to control the use of compact branch. Currently it's selected by CC_IS_CLANG and hopefully we can change it to a version check in future if clang manages to fix it. Fix boot on boston board. Link: https://github.com/llvm/llvm-project/issues/61045 Signed-off-by: Jiaxun Yang Acked-by: Nathan Chancellor Acked-by: Nick Desaulniers Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 4 ++++ arch/mips/include/asm/asm.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 875c29246555..e2f3ca73f40d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3200,6 +3200,10 @@ config CC_HAS_MNO_BRANCH_LIKELY def_bool y depends on $(cc-option,-mno-branch-likely) +# https://github.com/llvm/llvm-project/issues/61045 +config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH + def_bool y if CC_IS_CLANG + menu "Power management options" config ARCH_HIBERNATION_POSSIBLE diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 336ac9b65235..2e99450f4228 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -336,7 +336,7 @@ symbol = value */ #ifdef CONFIG_WAR_R10000_LLSC # define SC_BEQZ beqzl -#elif MIPS_ISA_REV >= 6 +#elif !defined(CONFIG_CC_HAS_BROKEN_INLINE_COMPAT_BRANCH) && MIPS_ISA_REV >= 6 # define SC_BEQZ beqzc #else # define SC_BEQZ beqz