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perf vendor events: Add Bonnell V4 event file

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Add a Intel event file for perf.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-7r1wcyb5ucqxsqzcljt3iz3b@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Andi Kleen 2016-10-05 09:53:08 -07:00 committed by Arnaldo Carvalho de Melo
parent 19c0389b60
commit 052aa3cce3
8 changed files with 2187 additions and 0 deletions
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746
tools/perf/pmu-events/arch/x86/bonnell/cache.json Normal file
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[
{
"EventCode": "0x21",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_ADS.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Cycles L2 address bus is in use."
},
{
"EventCode": "0x22",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_DBUS_BUSY.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Cycles the L2 cache data bus is busy."
},
{
"EventCode": "0x23",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_DBUS_BUSY_RD.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Cycles the L2 transfers data to the core."
},
{
"EventCode": "0x24",
"Counter": "0,1",
"UMask": "0x70",
"EventName": "L2_LINES_IN.SELF.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache misses."
},
{
"EventCode": "0x24",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_LINES_IN.SELF.DEMAND",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache misses."
},
{
"EventCode": "0x24",
"Counter": "0,1",
"UMask": "0x50",
"EventName": "L2_LINES_IN.SELF.PREFETCH",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache misses."
},
{
"EventCode": "0x25",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_M_LINES_IN.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache line modifications."
},
{
"EventCode": "0x26",
"Counter": "0,1",
"UMask": "0x70",
"EventName": "L2_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache lines evicted."
},
{
"EventCode": "0x26",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache lines evicted."
},
{
"EventCode": "0x26",
"Counter": "0,1",
"UMask": "0x50",
"EventName": "L2_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache lines evicted."
},
{
"EventCode": "0x27",
"Counter": "0,1",
"UMask": "0x70",
"EventName": "L2_M_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "Modified lines evicted from the L2 cache"
},
{
"EventCode": "0x27",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_M_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
"BriefDescription": "Modified lines evicted from the L2 cache"
},
{
"EventCode": "0x27",
"Counter": "0,1",
"UMask": "0x50",
"EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
"BriefDescription": "Modified lines evicted from the L2 cache"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x74",
"EventName": "L2_LD.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x71",
"EventName": "L2_LD.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x78",
"EventName": "L2_LD.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x72",
"EventName": "L2_LD.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "L2_LD.SELF.ANY.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_LD.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_LD.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_LD.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_LD.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_LD.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x54",
"EventName": "L2_LD.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x51",
"EventName": "L2_LD.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x58",
"EventName": "L2_LD.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x52",
"EventName": "L2_LD.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x5f",
"EventName": "L2_LD.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_ST.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_ST.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_ST.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_ST.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_ST.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_LOCK.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_LOCK.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_LOCK.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_LOCK.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_LOCK.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_DATA_RQSTS.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_DATA_RQSTS.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_DATA_RQSTS.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_DATA_RQSTS.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_DATA_RQSTS.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_LD_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_LD_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_LD_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_LD_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_LD_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x74",
"EventName": "L2_RQSTS.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x71",
"EventName": "L2_RQSTS.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x78",
"EventName": "L2_RQSTS.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x72",
"EventName": "L2_RQSTS.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "L2_RQSTS.SELF.ANY.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x54",
"EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x51",
"EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x58",
"EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x52",
"EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x5f",
"EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache demand requests from this core that missed the L2"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_RQSTS.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache demand requests from this core"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x74",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x71",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x78",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x72",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x54",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x51",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x58",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x52",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x5f",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x32",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_NO_REQ.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Cycles no L2 cache requests are pending"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0xa1",
"EventName": "L1D_CACHE.LD",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 Cacheable Data Reads"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0xa2",
"EventName": "L1D_CACHE.ST",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 Cacheable Data Writes"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0x83",
"EventName": "L1D_CACHE.ALL_REF",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 Data reads and writes"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0xa3",
"EventName": "L1D_CACHE.ALL_CACHE_REF",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 Data Cacheable reads and writes"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "L1D_CACHE.REPL",
"SampleAfterValue": "200000",
"BriefDescription": "L1 Data line replacements"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L1D_CACHE.REPLM",
"SampleAfterValue": "200000",
"BriefDescription": "Modified cache lines allocated in the L1 data cache"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "L1D_CACHE.EVICT",
"SampleAfterValue": "200000",
"BriefDescription": "Modified cache lines evicted from the L1 data cache"
},
{
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that hit the L2 cache (precise event)."
},
{
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"SampleAfterValue": "10000",
"BriefDescription": "Retired loads that miss the L2 cache"
}
]

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[
{
"EventCode": "0x10",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "X87_COMP_OPS_EXE.ANY.S",
"SampleAfterValue": "2000000",
"BriefDescription": "Floating point computational micro-ops executed."
},
{
"PEBS": "2",
"EventCode": "0x10",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "X87_COMP_OPS_EXE.ANY.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "Floating point computational micro-ops retired."
},
{
"EventCode": "0x10",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "X87_COMP_OPS_EXE.FXCH.S",
"SampleAfterValue": "2000000",
"BriefDescription": "FXCH uops executed."
},
{
"PEBS": "2",
"EventCode": "0x10",
"Counter": "0,1",
"UMask": "0x82",
"EventName": "X87_COMP_OPS_EXE.FXCH.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "FXCH uops retired."
},
{
"EventCode": "0x11",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "FP_ASSIST.S",
"SampleAfterValue": "10000",
"BriefDescription": "Floating point assists."
},
{
"EventCode": "0x11",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "FP_ASSIST.AR",
"SampleAfterValue": "10000",
"BriefDescription": "Floating point assists for retired operations."
},
{
"EventCode": "0xB0",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_UOPS_EXEC.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD micro-ops executed (excluding stores)."
},
{
"PEBS": "2",
"EventCode": "0xB0",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "SIMD_UOPS_EXEC.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD micro-ops retired (excluding stores)."
},
{
"EventCode": "0xB1",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_SAT_UOP_EXEC.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD saturated arithmetic micro-ops executed."
},
{
"EventCode": "0xB1",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "SIMD_SAT_UOP_EXEC.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD saturated arithmetic micro-ops retired."
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed multiply micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed multiply micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed shift micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x82",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed shift micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x84",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD unpacked micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x88",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD unpacked micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed logical micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x90",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed logical micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed arithmetic micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0xa0",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed arithmetic micro-ops retired"
},
{
"EventCode": "0xC7",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions."
},
{
"EventCode": "0xC7",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions."
},
{
"EventCode": "0xC7",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions."
},
{
"EventCode": "0xC7",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "SIMD_INST_RETIRED.VECTOR",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions."
},
{
"EventCode": "0xCD",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_ASSIST",
"SampleAfterValue": "100000",
"BriefDescription": "SIMD assists invoked."
},
{
"EventCode": "0xCE",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_INSTR_RETIRED",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD Instructions retired."
},
{
"EventCode": "0xCF",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_SAT_INSTR_RETIRED",
"SampleAfterValue": "2000000",
"BriefDescription": "Saturated arithmetic instructions retired."
}
]

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[
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200000",
"BriefDescription": "Instruction fetches."
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "Icache hit"
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200000",
"BriefDescription": "Icache miss"
},
{
"EventCode": "0x86",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles during which instruction fetches are stalled."
},
{
"EventCode": "0x87",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "DECODE_STALL.PFB_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Decode stall due to PFB empty"
},
{
"EventCode": "0x87",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "DECODE_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
"BriefDescription": "Decode stall due to IQ full"
},
{
"EventCode": "0xAA",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MACRO_INSTS.NON_CISC_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Non-CISC nacro instructions decoded"
},
{
"EventCode": "0xAA",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "MACRO_INSTS.CISC_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "CISC macro instructions decoded"
},
{
"EventCode": "0xAA",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "MACRO_INSTS.ALL_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "All Instructions decoded"
},
{
"EventCode": "0xA9",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "UOPS.MS_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ",
"CounterMask": "1"
}
]

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[
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0xf",
"EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "Memory references that cross an 8-byte boundary."
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x9",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "Load splits"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0xa",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "Store splits"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x8f",
"EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x89",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Load splits (At Retirement)"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x8a",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Store splits (Ar Retirement)"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x8c",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "ld-op-st splits"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x97",
"EventName": "MISALIGN_MEM_REF.BUBBLE",
"SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase 1 bubble"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x91",
"EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase load 1 bubble"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x92",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase store 1 bubble"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x94",
"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed."
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x82",
"EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed."
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x84",
"EventName": "PREFETCH.PREFETCHT2",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed."
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x86",
"EventName": "PREFETCH.SW_L2",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x88",
"EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "PREFETCH.HW_PREFETCH",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 hardware prefetch request"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0xf",
"EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000",
"BriefDescription": "Any Software prefetch"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x8f",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Any Software prefetch"
}
]

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[
{
"EventCode": "0x6",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "SEGMENT_REG_LOADS.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "Number of segment register loads."
},
{
"EventCode": "0x9",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "DISPATCH_BLOCKED.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
},
{
"EventCode": "0x3A",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "EIST_TRANS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
},
{
"EventCode": "0x3B",
"Counter": "0,1",
"UMask": "0xc0",
"EventName": "THERMAL_TRIP",
"SampleAfterValue": "200000",
"BriefDescription": "Number of thermal trips"
},
{
"EventCode": "0x60",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Outstanding cacheable data read bus requests duration."
},
{
"EventCode": "0x60",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_REQUEST_OUTSTANDING.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Outstanding cacheable data read bus requests duration."
},
{
"EventCode": "0x61",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "BUS_BNR_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of Bus Not Ready signals asserted."
},
{
"EventCode": "0x61",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BUS_BNR_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
"BriefDescription": "Number of Bus Not Ready signals asserted."
},
{
"EventCode": "0x62",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Bus cycles when data is sent on the bus."
},
{
"EventCode": "0x62",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
"SampleAfterValue": "200000",
"BriefDescription": "Bus cycles when data is sent on the bus."
},
{
"EventCode": "0x63",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Bus cycles when a LOCK signal is asserted."
},
{
"EventCode": "0x63",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_LOCK_CLOCKS.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Bus cycles when a LOCK signal is asserted."
},
{
"EventCode": "0x64",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_DATA_RCV.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Bus cycles while processor receives data."
},
{
"EventCode": "0x65",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_BRD.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Burst read bus transactions."
},
{
"EventCode": "0x65",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_BRD.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Burst read bus transactions."
},
{
"EventCode": "0x66",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_RFO.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "RFO bus transactions."
},
{
"EventCode": "0x66",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_RFO.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "RFO bus transactions."
},
{
"EventCode": "0x67",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_WB.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Explicit writeback bus transactions."
},
{
"EventCode": "0x67",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_WB.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Explicit writeback bus transactions."
},
{
"EventCode": "0x68",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Instruction-fetch bus transactions."
},
{
"EventCode": "0x68",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_IFETCH.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Instruction-fetch bus transactions."
},
{
"EventCode": "0x69",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Invalidate bus transactions."
},
{
"EventCode": "0x69",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_INVAL.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Invalidate bus transactions."
},
{
"EventCode": "0x6A",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_PWR.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Partial write bus transaction."
},
{
"EventCode": "0x6A",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_PWR.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Partial write bus transaction."
},
{
"EventCode": "0x6B",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_P.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Partial bus transactions."
},
{
"EventCode": "0x6B",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_P.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Partial bus transactions."
},
{
"EventCode": "0x6C",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_IO.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "IO bus transactions."
},
{
"EventCode": "0x6C",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_IO.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "IO bus transactions."
},
{
"EventCode": "0x6D",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_DEF.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Deferred bus transactions."
},
{
"EventCode": "0x6D",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_DEF.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Deferred bus transactions."
},
{
"EventCode": "0x6E",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_BURST.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Burst (full cache-line) bus transactions."
},
{
"EventCode": "0x6E",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_BURST.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Burst (full cache-line) bus transactions."
},
{
"EventCode": "0x6F",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_MEM.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Memory bus transactions."
},
{
"EventCode": "0x6F",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_MEM.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Memory bus transactions."
},
{
"EventCode": "0x70",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "BUS_TRANS_ANY.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "All bus transactions."
},
{
"EventCode": "0x70",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_TRANS_ANY.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "All bus transactions."
},
{
"EventCode": "0x77",
"Counter": "0,1",
"UMask": "0xb",
"EventName": "EXT_SNOOP.THIS_AGENT.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "External snoops."
},
{
"EventCode": "0x77",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
"SampleAfterValue": "200000",
"BriefDescription": "External snoops."
},
{
"EventCode": "0x77",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "EXT_SNOOP.THIS_AGENT.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "External snoops."
},
{
"EventCode": "0x77",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "EXT_SNOOP.THIS_AGENT.HITM",
"SampleAfterValue": "200000",
"BriefDescription": "External snoops."
},
{
"EventCode": "0x77",
"Counter": "0,1",
"UMask": "0x2b",
"EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "External snoops."
},
{
"EventCode": "0x77",
"Counter": "0,1",
"UMask": "0x21",
"EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
"SampleAfterValue": "200000",
"BriefDescription": "External snoops."
},
{
"EventCode": "0x77",
"Counter": "0,1",
"UMask": "0x22",
"EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "External snoops."
},
{
"EventCode": "0x77",
"Counter": "0,1",
"UMask": "0x28",
"EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
"SampleAfterValue": "200000",
"BriefDescription": "External snoops."
},
{
"EventCode": "0x7A",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "BUS_HIT_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "HIT signal asserted."
},
{
"EventCode": "0x7A",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BUS_HIT_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
"BriefDescription": "HIT signal asserted."
},
{
"EventCode": "0x7B",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "BUS_HITM_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "HITM signal asserted."
},
{
"EventCode": "0x7B",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BUS_HITM_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
"BriefDescription": "HITM signal asserted."
},
{
"EventCode": "0x7D",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUSQ_EMPTY.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Bus queue is empty."
},
{
"EventCode": "0x7E",
"Counter": "0,1",
"UMask": "0xe0",
"EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
"BriefDescription": "Bus stalled for snoops."
},
{
"EventCode": "0x7E",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "SNOOP_STALL_DRV.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Bus stalled for snoops."
},
{
"EventCode": "0x7F",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "BUS_IO_WAIT.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "IO requests waiting in the bus queue."
},
{
"EventCode": "0xC6",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles during which interrupts are disabled."
},
{
"EventCode": "0xC6",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles during which interrupts are pending and disabled."
},
{
"EventCode": "0xC8",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "HW_INT_RCV",
"SampleAfterValue": "200000",
"BriefDescription": "Hardware interrupts received."
}
]

364
tools/perf/pmu-events/arch/x86/bonnell/pipeline.json Normal file
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@ -0,0 +1,364 @@
[
{
"EventCode": "0x2",
"Counter": "0,1",
"UMask": "0x83",
"EventName": "STORE_FORWARDS.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "All store forwards"
},
{
"EventCode": "0x2",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "STORE_FORWARDS.GOOD",
"SampleAfterValue": "200000",
"BriefDescription": "Good store forwards"
},
{
"EventCode": "0x3",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "REISSUE.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "Micro-op reissues for any cause"
},
{
"EventCode": "0x3",
"Counter": "0,1",
"UMask": "0xff",
"EventName": "REISSUE.ANY.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Micro-op reissues for any cause (At Retirement)"
},
{
"EventCode": "0x12",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MUL.S",
"SampleAfterValue": "2000000",
"BriefDescription": "Multiply operations executed."
},
{
"EventCode": "0x12",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "MUL.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "Multiply operations retired"
},
{
"EventCode": "0x13",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "DIV.S",
"SampleAfterValue": "2000000",
"BriefDescription": "Divide operations executed."
},
{
"EventCode": "0x13",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "DIV.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "Divide operations retired"
},
{
"EventCode": "0x14",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles the divider is busy."
},
{
"EventCode": "0x3C",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"SampleAfterValue": "2000000",
"BriefDescription": "Core cycles when core is not halted"
},
{
"EventCode": "0x3C",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CPU_CLK_UNHALTED.BUS",
"SampleAfterValue": "200000",
"BriefDescription": "Bus cycles when core is not halted"
},
{
"EventCode": "0xA",
"Counter": "Fixed counter 2",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000000",
"BriefDescription": "Core cycles when core is not halted"
},
{
"EventCode": "0xA",
"Counter": "Fixed counter 3",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000",
"BriefDescription": "Reference cycles when core is not halted."
},
{
"EventCode": "0x88",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "BR_INST_TYPE_RETIRED.COND",
"SampleAfterValue": "2000000",
"BriefDescription": "All macro conditional branch instructions."
},
{
"EventCode": "0x88",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "BR_INST_TYPE_RETIRED.UNCOND",
"SampleAfterValue": "2000000",
"BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects"
},
{
"EventCode": "0x88",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "BR_INST_TYPE_RETIRED.IND",
"SampleAfterValue": "2000000",
"BriefDescription": "All indirect branches that are not calls."
},
{
"EventCode": "0x88",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "BR_INST_TYPE_RETIRED.RET",
"SampleAfterValue": "2000000",
"BriefDescription": "All indirect branches that have a return mnemonic"
},
{
"EventCode": "0x88",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
"SampleAfterValue": "2000000",
"BriefDescription": "All non-indirect calls"
},
{
"EventCode": "0x88",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "2000000",
"BriefDescription": "All indirect calls, including both register and memory indirect."
},
{
"EventCode": "0x88",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "2000000",
"BriefDescription": "Only taken macro conditional branch instructions"
},
{
"EventCode": "0x89",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "BR_MISSP_TYPE_RETIRED.COND",
"SampleAfterValue": "200000",
"BriefDescription": "Mispredicted cond branch instructions retired"
},
{
"EventCode": "0x89",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "BR_MISSP_TYPE_RETIRED.IND",
"SampleAfterValue": "200000",
"BriefDescription": "Mispredicted ind branches that are not calls"
},
{
"EventCode": "0x89",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
"SampleAfterValue": "200000",
"BriefDescription": "Mispredicted return branches"
},
{
"EventCode": "0x89",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "200000",
"BriefDescription": "Mispredicted indirect calls, including both register and memory indirect. "
},
{
"EventCode": "0x89",
"Counter": "0,1",
"UMask": "0x11",
"EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "200000",
"BriefDescription": "Mispredicted and taken cond branch instructions retired"
},
{
"PEBS": "2",
"EventCode": "0xC0",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions retired (precise event)."
},
{
"EventCode": "0xA",
"Counter": "Fixed counter 1",
"UMask": "0x0",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions retired."
},
{
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "UOPS_RETIRED.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "Micro-ops retired."
},
{
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "UOPS_RETIRED.STALLED_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles no micro-ops retired."
},
{
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "UOPS_RETIRED.STALLS",
"SampleAfterValue": "2000000",
"BriefDescription": "Periods no micro-ops retired."
},
{
"EventCode": "0xC3",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200000",
"BriefDescription": "Self-Modifying Code detected."
},
{
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BR_INST_RETIRED.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired branch instructions."
},
{
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired branch instructions that were predicted not-taken."
},
{
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
"SampleAfterValue": "200000",
"BriefDescription": "Retired branch instructions that were mispredicted not-taken."
},
{
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "BR_INST_RETIRED.PRED_TAKEN",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired branch instructions that were predicted taken."
},
{
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
"SampleAfterValue": "200000",
"BriefDescription": "Retired branch instructions that were mispredicted taken."
},
{
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xc",
"EventName": "BR_INST_RETIRED.TAKEN",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired taken branch instructions."
},
{
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xf",
"EventName": "BR_INST_RETIRED.ANY1",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired branch instructions."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BR_INST_RETIRED.MISPRED",
"SampleAfterValue": "200000",
"BriefDescription": "Retired mispredicted branch instructions (precise event)."
},
{
"EventCode": "0xDC",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "RESOURCE_STALLS.DIV_BUSY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles issue is stalled due to div busy."
},
{
"EventCode": "0xE0",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Branch instructions decoded"
},
{
"EventCode": "0xE4",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "BOGUS_BR",
"SampleAfterValue": "2000000",
"BriefDescription": "Bogus branches"
},
{
"EventCode": "0xE6",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "BACLEARS asserted."
},
{
"EventCode": "0x3",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "REISSUE.OVERLAP_STORE",
"SampleAfterValue": "200000",
"BriefDescription": "Micro-op reissues on a store-load collision"
},
{
"EventCode": "0x3",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "REISSUE.OVERLAP_STORE.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)"
}
]

124
tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json Normal file
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@ -0,0 +1,124 @@
[
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0x7",
"EventName": "DATA_TLB_MISSES.DTLB_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "Memory accesses that missed the DTLB."
},
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0x5",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses due to load operations."
},
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0x9",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
"SampleAfterValue": "200000",
"BriefDescription": "L0 DTLB misses due to load operations."
},
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0x6",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses due to store operations."
},
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0xa",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
"SampleAfterValue": "200000",
"BriefDescription": "L0 DTLB misses due to store operations"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of page-walks executed."
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Duration of page-walks in core cycles"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of D-side only page walks"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Duration of D-side only page walks"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of I-Side page walks"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Duration of I-Side page walks"
},
{
"EventCode": "0x82",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "ITLB.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB hits."
},
{
"EventCode": "0x82",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "ITLB.FLUSH",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB flushes."
},
{
"PEBS": "2",
"EventCode": "0x82",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "ITLB.MISSES",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB misses."
},
{
"PEBS": "1",
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that miss the DTLB (precise event)."
}
]

5
tools/perf/pmu-events/arch/x86/mapfile.csv
View File

@ -3,3 +3,8 @@ GenuineIntel-6-56,v5,broadwellde,core
GenuineIntel-6-3D,v17,broadwell,core
GenuineIntel-6-47,v17,broadwell,core
GenuineIntel-6-4F,v10,broadwellx,core
GenuineIntel-6-1C,v4,bonnell,core
GenuineIntel-6-26,v4,bonnell,core
GenuineIntel-6-27,v4,bonnell,core
GenuineIntel-6-36,v4,bonnell,core
GenuineIntel-6-35,v4,bonnell,core

1 Family-model Version Filename EventType
3 GenuineIntel-6-3D v17 broadwell core
4 GenuineIntel-6-47 v17 broadwell core
5 GenuineIntel-6-4F v10 broadwellx core
6 GenuineIntel-6-1C v4 bonnell core
7 GenuineIntel-6-26 v4 bonnell core
8 GenuineIntel-6-27 v4 bonnell core
9 GenuineIntel-6-36 v4 bonnell core
10 GenuineIntel-6-35 v4 bonnell core