net: phy: marvell10g: update header comments
Update header comments to indicate the newly found behaviour with XAUI interfaces. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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*
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*
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* There appears to be several different data paths through the PHY which
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* There appears to be several different data paths through the PHY which
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* are automatically managed by the PHY. The following has been determined
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* are automatically managed by the PHY. The following has been determined
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* via observation and experimentation:
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* via observation and experimentation for a setup using single-lane Serdes:
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*
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*
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* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
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* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
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* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
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* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
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* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
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* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
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*
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*
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* With XAUI, observation shows:
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*
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* XAUI PHYXS -- <appropriate PCS as above>
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*
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* and no switching of the host interface mode occurs.
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*
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* If both the fiber and copper ports are connected, the first to gain
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* If both the fiber and copper ports are connected, the first to gain
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* link takes priority and the other port is completely locked out.
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* link takes priority and the other port is completely locked out.
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*/
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*/
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