ARM: dts: add Protonic PRTI6G board
Protonic PRTI6G is a reference platform for industrial, safety critical applications Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Oleksij Rempel
Shawn Guo
parent
2e0e77e4b8
commit
062bf67d83
@ -634,6 +634,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
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imx6ul-pico-pi.dtb \
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imx6ul-phytec-segin-ff-rdk-emmc.dtb \
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imx6ul-phytec-segin-ff-rdk-nand.dtb \
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imx6ul-prti6g.dtb \
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imx6ul-tx6ul-0010.dtb \
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imx6ul-tx6ul-0011.dtb \
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imx6ul-tx6ul-mainboard.dtb \
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356
arch/arm/boot/dts/imx6ul-prti6g.dts
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356
arch/arm/boot/dts/imx6ul-prti6g.dts
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@ -0,0 +1,356 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) 2016 Protonic Holland
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* Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
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*/
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/dts-v1/;
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#include "imx6ul.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Protonic PRTI6G Board";
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compatible = "prt,prti6g", "fsl,imx6ul";
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chosen {
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stdout-path = &uart1;
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};
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clock_ksz8081_in: clock-ksz8081-in {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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clock_ksz8081_out: clock-ksz8081-out {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_leds>;
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led-0 {
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label = "debug0";
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gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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reg_3v2: regulator-3v2 {
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compatible = "regulator-fixed";
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regulator-name = "3v2";
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regulator-min-microvolt = <3200000>;
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regulator-max-microvolt = <3200000>;
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can2>;
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status = "okay";
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};
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&ecspi1 {
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cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <20000000>;
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};
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};
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&ecspi2 {
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cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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status = "okay";
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spi@0 {
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compatible = "spidev";
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reg = <0>;
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spi-max-frequency = <1000000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eth1>;
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phy-mode = "rmii";
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phy-handle = <&rmii_phy>;
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clocks = <&clks IMX6UL_CLK_ENET>,
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<&clks IMX6UL_CLK_ENET_AHB>,
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<&clks IMX6UL_CLK_ENET_PTP>,
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<&clock_ksz8081_out>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref";
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Microchip KSZ8081RNA PHY */
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rmii_phy: ethernet-phy@0 {
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reg = <0>;
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interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <300>;
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clocks = <&clock_ksz8081_in>;
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clock-names = "rmii-ref";
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};
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <100000>;
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status = "okay";
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/* additional i2c devices are added automatically by the boot loader */
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clock-frequency = <100000>;
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status = "okay";
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adc@49 {
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compatible = "ti,ads1015";
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reg = <0x49>;
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#address-cells = <1>;
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#size-cells = <0>;
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channel@4 {
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reg = <4>;
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ti,gain = <3>;
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ti,datarate = <3>;
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};
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channel@5 {
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reg = <5>;
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ti,gain = <3>;
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ti,datarate = <3>;
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};
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channel@6 {
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reg = <6>;
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ti,gain = <3>;
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ti,datarate = <3>;
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};
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channel@7 {
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reg = <7>;
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ti,gain = <3>;
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ti,datarate = <3>;
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};
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};
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rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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temperature-sensor@70 {
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compatible = "ti,tmp103";
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reg = <0x70>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_3v2>;
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no-1-8-v;
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disable-wp;
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cap-sd-highspeed;
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no-mmc;
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no-sdio;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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no-sd;
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no-sdio;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_can1: can1grp {
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fsl,pins = <
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MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
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MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
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/* SR */
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MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
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/* TERM */
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MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
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/* nSMBALERT */
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MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
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>;
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};
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pinctrl_can2: can2grp {
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fsl,pins = <
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MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
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MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
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/* SR */
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MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0
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MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1
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MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0
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MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0
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>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0
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MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1
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MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0
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MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0
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>;
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};
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pinctrl_eth1: eth1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x1b000
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/* PHY ENET1_RST */
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MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880
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/* PHY ENET1_IRQ */
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MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x00880
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* HW revision detect */
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/* REV_ID0 */
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MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
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/* REV_ID1 */
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MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0
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/* REV_ID2 */
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MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
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/* REV_ID3 */
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MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0
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/* BOARD_ID0 */
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MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0
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/* BOARD_ID1 */
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MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0
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/* BOARD_ID2 */
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MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0
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/* BOARD_ID3 */
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MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0
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/* Safety controller IO */
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/* WAKE_SC */
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MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0
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/* PROGRAM_SC */
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MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
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MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
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MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
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>;
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};
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pinctrl_leds: ledsgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
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/* SD1 CD */
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MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
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MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
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>;
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};
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};
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