drm/i915/cnl: Fix wrpll math for higher freqs.
Spec describe all values in MHz. We handle our clocks in KHz. This includes the best_dco_centrality that was forgot in the same unity as spec. Consequently we couldn't get a good divider for high frequenies. Hence HDMI 2.0 wasn't working. Spec tells 999999 for initial best_dco_centrality meaning the max value in MHz. Since we convert dco from MHz to KHz we also need to convert this initial best_doc_centrality to 999999000 or 999999999 or even better, to the max that its variable allow. This patch also replaces the use of "* KHz(1)" with the values directly on KHz to avoid future confusion. v2: Use U32_MAX instead of random 99999 as spec tells. (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171114234223.10600-1-rodrigo.vivi@intel.com
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@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
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struct skl_wrpll_params *wrpll_params)
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{
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u32 afe_clock = clock * 5;
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u32 dco_min = 7998 * KHz(1);
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u32 dco_max = 10000 * KHz(1);
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u32 dco_min = 7998000;
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u32 dco_max = 10000000;
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u32 dco_mid = (dco_min + dco_max) / 2;
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static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
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18, 20, 24, 28, 30, 32, 36, 40,
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@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
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84, 88, 90, 92, 96, 98, 100, 102,
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3, 5, 7, 9, 15, 21 };
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u32 dco, best_dco = 0, dco_centrality = 0;
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u32 best_dco_centrality = 999999;
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u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
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int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
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for (d = 0; d < ARRAY_SIZE(dividers); d++) {
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