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perf/x86/intel/uncore: Add Sapphire Rapids server PCU support

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The PCU is the primary power controller for the Sapphire Rapids.

Except the name, all the information can be retrieved from the discovery
tables.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-7-git-send-email-kan.liang@linux.intel.com
This commit is contained in:
Kan Liang 2021-06-30 14:08:30 -07:00 committed by Peter Zijlstra
parent f85ef898f8
commit 0654dfdc7e
1 changed files with 5 additions and 1 deletions
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6
arch/x86/events/intel/uncore_snbep.c
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@ -5633,6 +5633,10 @@ static struct intel_uncore_type spr_uncore_m2pcie = {
.name = "m2pcie",
};
static struct intel_uncore_type spr_uncore_pcu = {
.name = "pcu",
};
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@ -5640,7 +5644,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
&spr_uncore_iio,
&spr_uncore_irp,
&spr_uncore_m2pcie,
NULL,
&spr_uncore_pcu,
NULL,
NULL,
NULL,