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rtw89: 8852c: add 8852c specific BT-coexistence initial function

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Initialize registers to default values, such as PTA and GNT pin, and set
pin MUX according to number of antenna on hardware module.

Signed-off-by: Chia-Yuan Li <leo.li@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220408001353.17188-10-pkshih@realtek.com
This commit is contained in:
Chia-Yuan Li 2022-04-08 08:13:49 +08:00 committed by Kalle Valo
parent d264edb1cc
commit 065cf8f977
4 changed files with 122 additions and 0 deletions
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28
drivers/net/wireless/realtek/rtw89/mac.c
View File

@ -3973,6 +3973,34 @@ int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex
}
EXPORT_SYMBOL(rtw89_mac_coex_init);
int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
const struct rtw89_mac_ax_coex *coex)
{
rtw89_write32_set(rtwdev, R_AX_BTC_CFG,
B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL);
rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);
rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);
rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN);
switch (coex->pta_mode) {
case RTW89_MAC_AX_COEX_RTK_MODE:
rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
MAC_AX_RTK_MODE);
rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1,
B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE);
break;
case RTW89_MAC_AX_COEX_CSR_MODE:
rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
MAC_AX_CSR_MODE);
break;
default:
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL(rtw89_mac_coex_init_v1);
int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
{

2
drivers/net/wireless/realtek/rtw89/mac.h
View File

@ -829,6 +829,8 @@ int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable)
void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
const struct rtw89_mac_ax_coex *coex);
int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,

33
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -87,6 +87,8 @@
#define B_AX_BTMODE_MASK GENMASK(7, 6)
#define MAC_AX_BT_MODE_0_3 0
#define MAC_AX_BT_MODE_2 2
#define MAC_AX_RTK_MODE 0
#define MAC_AX_CSR_MODE 1
#define B_AX_ENBT BIT(5)
#define B_AX_EROM_EN BIT(4)
#define B_AX_ENUARTRX BIT(2)
@ -2962,11 +2964,40 @@
#define R_AX_TXPWR_ISR_C1 0xF9E4
#define R_AX_BTC_CFG 0xDA00
#define B_AX_BTC_EN BIT(31)
#define B_AX_EN_EXT_BT_PINMUX BIT(29)
#define B_AX_BTC_RST BIT(28)
#define B_AX_BTC_DBG_SRC_SEL BIT(27)
#define B_AX_BTC_MODE_MASK GENMASK(25, 24)
#define B_AX_INV_WL_ACT2 BIT(17)
#define B_AX_BTG_LNA1_GAIN_SEL BIT(16)
#define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8)
#define B_AX_IGN_GNT_BT2_RX BIT(7)
#define B_AX_IGN_GNT_BT2_TX BIT(6)
#define B_AX_IGN_GNT_BT2 BIT(5)
#define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
#define B_AX_DIS_BTC_CLK_G BIT(2)
#define B_AX_GNT_WL_RX_CTRL BIT(1)
#define B_AX_WL_SRC BIT(0)
#define R_AX_RTK_MODE_CFG_V1 0xDA04
#define R_AX_RTK_MODE_CFG_V1_C1 0xFA04
#define B_AX_BT_BLE_EN_V1 BIT(24)
#define B_AX_BT_ULTRA_EN BIT(16)
#define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14)
#define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12)
#define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10)
#define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
#define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
#define R_AX_WL_PRI_MSK 0xDA10
#define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8)
#define R_AX_BT_CNT_CFG 0xDA10
#define R_AX_BT_CNT_CFG_C1 0xFA10
#define B_AX_BT_CNT_RST_V1 BIT(1)
#define B_AX_BT_CNT_EN BIT(0)
#define R_AX_BTC_FUNC_EN 0xDA20
#define R_AX_BTC_FUNC_EN_C1 0xFA20
#define B_AX_PTA_WL_TX_EN BIT(1)
@ -2999,6 +3030,8 @@
#define B_AX_WL_ACT_MASK_ENABLE BIT(1)
#define B_AX_ENHANCED_BT BIT(0)
#define R_AX_BT_BREAK_TABLE 0xDA44
#define R_AX_BT_STAST_HIGH 0xDA44
#define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
#define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)

59
drivers/net/wireless/realtek/rtw89/rtw8852c.c
View File

@ -2,6 +2,7 @@
/* Copyright(c) 2019-2022 Realtek Corporation
*/
#include "coex.h"
#include "debug.h"
#include "fw.h"
#include "mac.h"
@ -528,6 +529,62 @@ void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
}
}
static
void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
{
rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
}
static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev)
{
struct rtw89_btc *btc = &rtwdev->btc;
struct rtw89_btc_module *module = &btc->mdinfo;
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_mac_ax_coex coex_params = {
.pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
.direction = RTW89_MAC_AX_COEX_INNER,
};
/* PTA init */
rtw89_mac_coex_init_v1(rtwdev, &coex_params);
/* set WL Tx response = Hi-Pri */
chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
/* set rf gnt debug off */
rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
/* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
if (module->ant.type == BTC_ANT_SHARED) {
rtw8852c_set_trx_mask(rtwdev,
RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
rtw8852c_set_trx_mask(rtwdev,
RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
/* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
rtw8852c_set_trx_mask(rtwdev,
RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
} else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
rtw8852c_set_trx_mask(rtwdev,
RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
rtw8852c_set_trx_mask(rtwdev,
RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
}
/* set PTA break table */
rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM);
/* enable BT counter 0xda10[1:0] = 2b'11 */
rtw89_write32_set(rtwdev,
R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN |
B_AX_BT_CNT_RST_V1);
btc->cx.wl.status.map.init_ok = true;
}
static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
{
int ret;
@ -588,6 +645,8 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
.mac_cfg_gnt = rtw89_mac_cfg_gnt_v1,
.stop_sch_tx = rtw89_mac_stop_sch_tx_v1,
.resume_sch_tx = rtw89_mac_resume_sch_tx_v1,
.btc_init_cfg = rtw8852c_btc_init_cfg,
};
const struct rtw89_chip_info rtw8852c_chip_info = {