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ARM: dts: r9a06g032: describe MII converter

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Add the MII converter node which describes the MII converter that is
present on the RZ/N1 SoC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Clément Léger 2022-06-24 16:39:57 +02:00 committed by David S. Miller
parent d7cc14bc98
commit 066c3bd358
1 changed files with 39 additions and 0 deletions
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39
arch/arm/boot/dts/r9a06g032.dtsi
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@ -304,6 +304,45 @@
data-width = <8>;
};
eth_miic: eth-miic@44030000 {
compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x44030000 0x10000>;
clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
<&sysctrl R9A06G032_CLK_RGMII_REF>,
<&sysctrl R9A06G032_CLK_RMII_REF>,
<&sysctrl R9A06G032_HCLK_SWITCH_RG>;
clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
power-domains = <&sysctrl>;
status = "disabled";
mii_conv1: mii-conv@1 {
reg = <1>;
status = "disabled";
};
mii_conv2: mii-conv@2 {
reg = <2>;
status = "disabled";
};
mii_conv3: mii-conv@3 {
reg = <3>;
status = "disabled";
};
mii_conv4: mii-conv@4 {
reg = <4>;
status = "disabled";
};
mii_conv5: mii-conv@5 {
reg = <5>;
status = "disabled";
};
};
gic: interrupt-controller@44101000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;