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drm/amd/display: Add SE_DCN3_REG_LIST for control SDP num

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[Why] New platform. Need to add corresponding register control

Signed-off-by: Max.Tseng <Max.Tseng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Max.Tseng 2021-04-16 10:04:51 +08:00 committed by Alex Deucher
parent 088bebc79e
commit 069a11cca5
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
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@ -85,7 +85,9 @@
SRI(DP_MSE_RATE_UPDATE, DP, id), \
SRI(DP_PIXEL_FORMAT, DP, id), \
SRI(DP_SEC_CNTL, DP, id), \
SRI(DP_SEC_CNTL1, DP, id), \
SRI(DP_SEC_CNTL2, DP, id), \
SRI(DP_SEC_CNTL5, DP, id), \
SRI(DP_SEC_CNTL6, DP, id), \
SRI(DP_STEER_FIFO, DP, id), \
SRI(DP_VID_M, DP, id), \