brcmfmac: move chip download state code to sdio_chip.c
enter/exit download state routine is going to diverge with new ARM core introduced. Move corresponding code to sdio_chip.c for new ARM core support. Reviewed-by: Arend van Spriel <arend@broadcom.com> Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Franky Lin
John W. Linville
parent
ba540b01a9
commit
069eddd926
@ -336,95 +336,6 @@ static uint prio2prec(u32 prio)
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(prio^2) : prio;
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}
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/* core registers */
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struct sdpcmd_regs {
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u32 corecontrol; /* 0x00, rev8 */
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u32 corestatus; /* rev8 */
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u32 PAD[1];
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u32 biststatus; /* rev8 */
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/* PCMCIA access */
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u16 pcmciamesportaladdr; /* 0x010, rev8 */
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u16 PAD[1];
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u16 pcmciamesportalmask; /* rev8 */
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u16 PAD[1];
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u16 pcmciawrframebc; /* rev8 */
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u16 PAD[1];
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u16 pcmciaunderflowtimer; /* rev8 */
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u16 PAD[1];
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/* interrupt */
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u32 intstatus; /* 0x020, rev8 */
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u32 hostintmask; /* rev8 */
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u32 intmask; /* rev8 */
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u32 sbintstatus; /* rev8 */
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u32 sbintmask; /* rev8 */
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u32 funcintmask; /* rev4 */
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u32 PAD[2];
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u32 tosbmailbox; /* 0x040, rev8 */
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u32 tohostmailbox; /* rev8 */
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u32 tosbmailboxdata; /* rev8 */
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u32 tohostmailboxdata; /* rev8 */
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/* synchronized access to registers in SDIO clock domain */
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u32 sdioaccess; /* 0x050, rev8 */
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u32 PAD[3];
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/* PCMCIA frame control */
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u8 pcmciaframectrl; /* 0x060, rev8 */
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u8 PAD[3];
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u8 pcmciawatermark; /* rev8 */
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u8 PAD[155];
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/* interrupt batching control */
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u32 intrcvlazy; /* 0x100, rev8 */
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u32 PAD[3];
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/* counters */
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u32 cmd52rd; /* 0x110, rev8 */
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u32 cmd52wr; /* rev8 */
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u32 cmd53rd; /* rev8 */
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u32 cmd53wr; /* rev8 */
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u32 abort; /* rev8 */
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u32 datacrcerror; /* rev8 */
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u32 rdoutofsync; /* rev8 */
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u32 wroutofsync; /* rev8 */
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u32 writebusy; /* rev8 */
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u32 readwait; /* rev8 */
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u32 readterm; /* rev8 */
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u32 writeterm; /* rev8 */
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u32 PAD[40];
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u32 clockctlstatus; /* rev8 */
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u32 PAD[7];
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u32 PAD[128]; /* DMA engines */
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/* SDIO/PCMCIA CIS region */
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char cis[512]; /* 0x400-0x5ff, rev6 */
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/* PCMCIA function control registers */
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char pcmciafcr[256]; /* 0x600-6ff, rev6 */
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u16 PAD[55];
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/* PCMCIA backplane access */
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u16 backplanecsr; /* 0x76E, rev6 */
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u16 backplaneaddr0; /* rev6 */
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u16 backplaneaddr1; /* rev6 */
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u16 backplaneaddr2; /* rev6 */
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u16 backplaneaddr3; /* rev6 */
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u16 backplanedata0; /* rev6 */
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u16 backplanedata1; /* rev6 */
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u16 backplanedata2; /* rev6 */
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u16 backplanedata3; /* rev6 */
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u16 PAD[31];
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/* sprom "size" & "blank" info */
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u16 spromstatus; /* 0x7BE, rev2 */
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u32 PAD[464];
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u16 PAD[0x80];
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};
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#ifdef DEBUG
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/* Device console log buffer state */
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struct brcmf_console {
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@ -3082,84 +2993,8 @@ brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
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return rxlen ? (int)rxlen : -ETIMEDOUT;
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}
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static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
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static bool brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
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{
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int bcmerror = 0;
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u32 varaddr;
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u32 varsizew;
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__le32 varsizew_le;
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#ifdef DEBUG
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char *nvram_ularray;
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#endif /* DEBUG */
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/* Even if there are no vars are to be written, we still
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need to set the ramsize. */
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varaddr = (bus->ramsize - 4) - bus->varsz;
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if (bus->vars) {
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/* Write the vars list */
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bcmerror = brcmf_sdio_ramrw(bus->sdiodev, true, varaddr,
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bus->vars, bus->varsz);
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#ifdef DEBUG
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/* Verify NVRAM bytes */
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brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n",
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bus->varsz);
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nvram_ularray = kmalloc(bus->varsz, GFP_ATOMIC);
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if (!nvram_ularray)
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return -ENOMEM;
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/* Upload image to verify downloaded contents. */
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memset(nvram_ularray, 0xaa, bus->varsz);
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/* Read the vars list to temp buffer for comparison */
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bcmerror = brcmf_sdio_ramrw(bus->sdiodev, false, varaddr,
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nvram_ularray, bus->varsz);
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if (bcmerror) {
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brcmf_err("error %d on reading %d nvram bytes at 0x%08x\n",
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bcmerror, bus->varsz, varaddr);
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}
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/* Compare the org NVRAM with the one read from RAM */
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if (memcmp(bus->vars, nvram_ularray, bus->varsz))
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brcmf_err("Downloaded NVRAM image is corrupted\n");
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else
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brcmf_err("Download/Upload/Compare of NVRAM ok\n");
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kfree(nvram_ularray);
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#endif /* DEBUG */
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}
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/* adjust to the user specified RAM */
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brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
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brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
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varaddr, bus->varsz);
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/*
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* Determine the length token:
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* Varsize, converted to words, in lower 16-bits, checksum
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* in upper 16-bits.
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*/
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if (bcmerror) {
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varsizew = 0;
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varsizew_le = cpu_to_le32(0);
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} else {
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varsizew = bus->varsz / 4;
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varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
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varsizew_le = cpu_to_le32(varsizew);
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}
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brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
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bus->varsz, varsizew);
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/* Write the length token to the last word */
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bcmerror = brcmf_sdio_ramrw(bus->sdiodev, true, (bus->ramsize - 4),
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(u8 *)&varsizew_le, 4);
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return bcmerror;
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}
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static int brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
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{
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int bcmerror = 0;
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struct chip_info *ci = bus->ci;
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/* To enter download state, disable ARM and reset SOCRAM.
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@ -3168,41 +3003,19 @@ static int brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
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if (enter) {
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bus->alp_only = true;
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ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
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ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
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/* Clear the top bit of memory */
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if (bus->ramsize) {
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u32 zeros = 0;
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brcmf_sdio_ramrw(bus->sdiodev, true, bus->ramsize - 4,
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(u8 *)&zeros, 4);
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}
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brcmf_sdio_chip_enter_download(bus->sdiodev, ci);
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} else {
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if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
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brcmf_err("SOCRAM core is down after reset?\n");
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bcmerror = -EBADE;
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goto fail;
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}
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bcmerror = brcmf_sdbrcm_write_vars(bus);
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if (bcmerror) {
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brcmf_err("no vars written to RAM\n");
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bcmerror = 0;
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}
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w_sdreg32(bus, 0xFFFFFFFF,
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offsetof(struct sdpcmd_regs, intstatus));
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ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
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if (!brcmf_sdio_chip_exit_download(bus->sdiodev, ci, bus->vars,
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bus->varsz))
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return false;
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/* Allow HT Clock now that the ARM is running. */
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bus->alp_only = false;
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bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD;
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}
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fail:
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return bcmerror;
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return true;
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}
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static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_sdio *bus)
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@ -3359,7 +3172,7 @@ static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
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int bcmerror = -1;
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/* Keep arm in reset */
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if (brcmf_sdbrcm_download_state(bus, true)) {
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if (!brcmf_sdbrcm_download_state(bus, true)) {
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brcmf_err("error placing ARM core in reset\n");
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goto err;
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}
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@ -3375,7 +3188,7 @@ static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
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}
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/* Take arm out of reset */
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if (brcmf_sdbrcm_download_state(bus, false)) {
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if (!brcmf_sdbrcm_download_state(bus, false)) {
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brcmf_err("error getting out of ARM core reset\n");
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goto err;
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}
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@ -356,8 +356,7 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
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{
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u32 regdata;
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/*
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* Get CC core rev
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/* Get CC core rev
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* Chipid is assume to be at offset 0 from regs arg
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* For different chiptypes or old sdio hosts w/o chipcommon,
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* other ways of recognition should be added here.
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@ -650,3 +649,140 @@ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
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drivestrength, cc_data_temp);
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}
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}
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#ifdef DEBUG
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static bool
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brcmf_sdio_chip_verifynvram(struct brcmf_sdio_dev *sdiodev, u32 nvram_addr,
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char *nvram_dat, uint nvram_sz)
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{
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char *nvram_ularray;
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int err;
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bool ret = true;
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/* read back and verify */
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brcmf_dbg(INFO, "Compare NVRAM dl & ul; size=%d\n", nvram_sz);
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nvram_ularray = kmalloc(nvram_sz, GFP_KERNEL);
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/* do not proceed while no memory but */
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if (!nvram_ularray)
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return true;
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/* Upload image to verify downloaded contents. */
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memset(nvram_ularray, 0xaa, nvram_sz);
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/* Read the vars list to temp buffer for comparison */
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err = brcmf_sdio_ramrw(sdiodev, false, nvram_addr, nvram_ularray,
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nvram_sz);
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if (err) {
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brcmf_err("error %d on reading %d nvram bytes at 0x%08x\n",
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err, nvram_sz, nvram_addr);
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} else if (memcmp(nvram_dat, nvram_ularray, nvram_sz)) {
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brcmf_err("Downloaded NVRAM image is corrupted\n");
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ret = false;
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}
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kfree(nvram_ularray);
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return ret;
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}
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#else /* DEBUG */
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static inline bool
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brcmf_sdio_chip_verifynvram(struct brcmf_sdio_dev *sdiodev, u32 nvram_addr,
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char *nvram_dat, uint nvram_sz)
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{
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return true;
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}
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#endif /* DEBUG */
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static bool brcmf_sdio_chip_writenvram(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci,
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char *nvram_dat, uint nvram_sz)
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{
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int err;
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u32 nvram_addr;
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u32 token;
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__le32 token_le;
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nvram_addr = (ci->ramsize - 4) - nvram_sz;
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/* Write the vars list */
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err = brcmf_sdio_ramrw(sdiodev, true, nvram_addr, nvram_dat, nvram_sz);
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if (err) {
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brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
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err, nvram_sz, nvram_addr);
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return false;
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}
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if (!brcmf_sdio_chip_verifynvram(sdiodev, nvram_addr,
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nvram_dat, nvram_sz))
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return false;
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/* generate token:
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* nvram size, converted to words, in lower 16-bits, checksum
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* in upper 16-bits.
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*/
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token = nvram_sz / 4;
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token = (~token << 16) | (token & 0x0000FFFF);
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token_le = cpu_to_le32(token);
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brcmf_dbg(INFO, "RAM size: %d\n", ci->ramsize);
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brcmf_dbg(INFO, "nvram is placed at %d, size %d, token=0x%08x\n",
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nvram_addr, nvram_sz, token);
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/* Write the length token to the last word */
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if (brcmf_sdio_ramrw(sdiodev, true, (ci->ramsize - 4),
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(u8 *)&token_le, 4))
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return false;
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return true;
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}
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static void
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brcmf_sdio_chip_cm3_enterdl(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci)
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{
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u32 zeros = 0;
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ci->coredisable(sdiodev, ci, BCMA_CORE_ARM_CM3);
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ci->resetcore(sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
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/* clear length token */
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brcmf_sdio_ramrw(sdiodev, true, ci->ramsize - 4, (u8 *)&zeros, 4);
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}
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static bool
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brcmf_sdio_chip_cm3_exitdl(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
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char *nvram_dat, uint nvram_sz)
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{
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u8 core_idx;
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u32 reg_addr;
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if (!ci->iscoreup(sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
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brcmf_err("SOCRAM core is down after reset?\n");
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return false;
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}
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if (!brcmf_sdio_chip_writenvram(sdiodev, ci, nvram_dat, nvram_sz))
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return false;
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/* clear all interrupts */
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core_idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_SDIO_DEV);
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reg_addr = ci->c_inf[core_idx].base;
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reg_addr += offsetof(struct sdpcmd_regs, intstatus);
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brcmf_sdio_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
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ci->resetcore(sdiodev, ci, BCMA_CORE_ARM_CM3);
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return true;
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}
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void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci)
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{
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brcmf_sdio_chip_cm3_enterdl(sdiodev, ci);
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}
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bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci, char *nvram_dat,
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uint nvram_sz)
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{
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return brcmf_sdio_chip_cm3_exitdl(sdiodev, ci, nvram_dat, nvram_sz);
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}
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@ -124,6 +124,95 @@ struct sbconfig {
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u32 sbidhigh; /* identification */
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};
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/* sdio core registers */
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struct sdpcmd_regs {
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u32 corecontrol; /* 0x00, rev8 */
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u32 corestatus; /* rev8 */
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u32 PAD[1];
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u32 biststatus; /* rev8 */
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/* PCMCIA access */
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u16 pcmciamesportaladdr; /* 0x010, rev8 */
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u16 PAD[1];
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u16 pcmciamesportalmask; /* rev8 */
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u16 PAD[1];
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u16 pcmciawrframebc; /* rev8 */
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u16 PAD[1];
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u16 pcmciaunderflowtimer; /* rev8 */
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u16 PAD[1];
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/* interrupt */
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u32 intstatus; /* 0x020, rev8 */
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u32 hostintmask; /* rev8 */
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u32 intmask; /* rev8 */
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u32 sbintstatus; /* rev8 */
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u32 sbintmask; /* rev8 */
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u32 funcintmask; /* rev4 */
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u32 PAD[2];
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u32 tosbmailbox; /* 0x040, rev8 */
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u32 tohostmailbox; /* rev8 */
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u32 tosbmailboxdata; /* rev8 */
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u32 tohostmailboxdata; /* rev8 */
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/* synchronized access to registers in SDIO clock domain */
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u32 sdioaccess; /* 0x050, rev8 */
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u32 PAD[3];
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/* PCMCIA frame control */
|
||||
u8 pcmciaframectrl; /* 0x060, rev8 */
|
||||
u8 PAD[3];
|
||||
u8 pcmciawatermark; /* rev8 */
|
||||
u8 PAD[155];
|
||||
|
||||
/* interrupt batching control */
|
||||
u32 intrcvlazy; /* 0x100, rev8 */
|
||||
u32 PAD[3];
|
||||
|
||||
/* counters */
|
||||
u32 cmd52rd; /* 0x110, rev8 */
|
||||
u32 cmd52wr; /* rev8 */
|
||||
u32 cmd53rd; /* rev8 */
|
||||
u32 cmd53wr; /* rev8 */
|
||||
u32 abort; /* rev8 */
|
||||
u32 datacrcerror; /* rev8 */
|
||||
u32 rdoutofsync; /* rev8 */
|
||||
u32 wroutofsync; /* rev8 */
|
||||
u32 writebusy; /* rev8 */
|
||||
u32 readwait; /* rev8 */
|
||||
u32 readterm; /* rev8 */
|
||||
u32 writeterm; /* rev8 */
|
||||
u32 PAD[40];
|
||||
u32 clockctlstatus; /* rev8 */
|
||||
u32 PAD[7];
|
||||
|
||||
u32 PAD[128]; /* DMA engines */
|
||||
|
||||
/* SDIO/PCMCIA CIS region */
|
||||
char cis[512]; /* 0x400-0x5ff, rev6 */
|
||||
|
||||
/* PCMCIA function control registers */
|
||||
char pcmciafcr[256]; /* 0x600-6ff, rev6 */
|
||||
u16 PAD[55];
|
||||
|
||||
/* PCMCIA backplane access */
|
||||
u16 backplanecsr; /* 0x76E, rev6 */
|
||||
u16 backplaneaddr0; /* rev6 */
|
||||
u16 backplaneaddr1; /* rev6 */
|
||||
u16 backplaneaddr2; /* rev6 */
|
||||
u16 backplaneaddr3; /* rev6 */
|
||||
u16 backplanedata0; /* rev6 */
|
||||
u16 backplanedata1; /* rev6 */
|
||||
u16 backplanedata2; /* rev6 */
|
||||
u16 backplanedata3; /* rev6 */
|
||||
u16 PAD[31];
|
||||
|
||||
/* sprom "size" & "blank" info */
|
||||
u16 spromstatus; /* 0x7BE, rev2 */
|
||||
u32 PAD[464];
|
||||
|
||||
u16 PAD[0x80];
|
||||
};
|
||||
|
||||
extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
|
||||
struct chip_info **ci_ptr, u32 regs);
|
||||
extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr);
|
||||
@ -131,6 +220,10 @@ extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
|
||||
struct chip_info *ci,
|
||||
u32 drivestrength);
|
||||
extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid);
|
||||
|
||||
extern void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev *sdiodev,
|
||||
struct chip_info *ci);
|
||||
extern bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev *sdiodev,
|
||||
struct chip_info *ci, char *nvram_dat,
|
||||
uint nvram_sz);
|
||||
|
||||
#endif /* _BRCMFMAC_SDIO_CHIP_H_ */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user