From 06aeb7533294d8a02383f2b248d04cd9a2731172 Mon Sep 17 00:00:00 2001 From: Xiaojian Du Date: Wed, 29 Dec 2021 15:03:11 +0800 Subject: [PATCH] drm/amdgpu: handle asics with 1 SDMA instance This patch will handle asics with 1 SDMA instance. Signed-off-by: Xiaojian Du Reviewed-by: Huang Rui Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 307a1da13557..29acc5573f56 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -252,8 +252,9 @@ static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, *value = 0; for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { en = &soc21_allowed_read_registers[i]; - if (reg_offset != - (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) + if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ + reg_offset != + (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) continue; *value = soc21_get_register_value(adev,