clk: qcom: Add TCSR clock driver for x1e80100
The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-9-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -49,6 +49,14 @@ config CLK_X1E80100_GPUCC
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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config CLK_X1E80100_TCSRCC
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tristate "X1E80100 TCSR Clock Controller"
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depends on ARM64 || COMPILE_TEST
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select QCOM_GDSC
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help
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Support for the TCSR clock controller on X1E80100 devices.
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Say Y if you want to use peripheral devices such as SD/UFS.
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config QCOM_A53PLL
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tristate "MSM8916 A53 PLL"
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help
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@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
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obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
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obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
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obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o
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obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
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obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
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obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
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obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
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285
drivers/clk/qcom/tcsrcc-x1e80100.c
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285
drivers/clk/qcom/tcsrcc-x1e80100.c
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@ -0,0 +1,285 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
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#include "clk-branch.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "reset.h"
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enum {
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DT_BI_TCXO_PAD,
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};
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static struct clk_branch tcsr_edp_clkref_en = {
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.halt_reg = 0x15130,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15130,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_edp_clkref_en",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_pcie_2l_4_clkref_en = {
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.halt_reg = 0x15100,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15100,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_pcie_2l_4_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_pcie_2l_5_clkref_en = {
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.halt_reg = 0x15104,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15104,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_pcie_2l_5_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_pcie_8l_clkref_en = {
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.halt_reg = 0x15108,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15108,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_pcie_8l_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_usb3_mp0_clkref_en = {
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.halt_reg = 0x1510c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1510c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_usb3_mp0_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_usb3_mp1_clkref_en = {
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.halt_reg = 0x15110,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15110,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_usb3_mp1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_usb2_1_clkref_en = {
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.halt_reg = 0x15114,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15114,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_usb2_1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_ufs_phy_clkref_en = {
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.halt_reg = 0x15118,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15118,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_ufs_phy_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_usb4_1_clkref_en = {
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.halt_reg = 0x15120,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15120,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_usb4_1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_usb4_2_clkref_en = {
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.halt_reg = 0x15124,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15124,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_usb4_2_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_usb2_2_clkref_en = {
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.halt_reg = 0x15128,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x15128,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_usb2_2_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_pcie_4l_clkref_en = {
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.halt_reg = 0x1512c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1512c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_pcie_4l_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *tcsr_cc_x1e80100_clocks[] = {
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[TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr,
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[TCSR_PCIE_2L_4_CLKREF_EN] = &tcsr_pcie_2l_4_clkref_en.clkr,
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[TCSR_PCIE_2L_5_CLKREF_EN] = &tcsr_pcie_2l_5_clkref_en.clkr,
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[TCSR_PCIE_8L_CLKREF_EN] = &tcsr_pcie_8l_clkref_en.clkr,
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[TCSR_USB3_MP0_CLKREF_EN] = &tcsr_usb3_mp0_clkref_en.clkr,
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[TCSR_USB3_MP1_CLKREF_EN] = &tcsr_usb3_mp1_clkref_en.clkr,
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[TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
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[TCSR_UFS_PHY_CLKREF_EN] = &tcsr_ufs_phy_clkref_en.clkr,
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[TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr,
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[TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr,
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[TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
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[TCSR_PCIE_4L_CLKREF_EN] = &tcsr_pcie_4l_clkref_en.clkr,
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};
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static const struct regmap_config tcsr_cc_x1e80100_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x2f000,
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.fast_io = true,
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};
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static const struct qcom_cc_desc tcsr_cc_x1e80100_desc = {
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.config = &tcsr_cc_x1e80100_regmap_config,
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.clks = tcsr_cc_x1e80100_clocks,
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.num_clks = ARRAY_SIZE(tcsr_cc_x1e80100_clocks),
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};
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static const struct of_device_id tcsr_cc_x1e80100_match_table[] = {
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{ .compatible = "qcom,x1e80100-tcsr" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tcsr_cc_x1e80100_match_table);
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static int tcsr_cc_x1e80100_probe(struct platform_device *pdev)
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{
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return qcom_cc_probe(pdev, &tcsr_cc_x1e80100_desc);
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}
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static struct platform_driver tcsr_cc_x1e80100_driver = {
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.probe = tcsr_cc_x1e80100_probe,
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.driver = {
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.name = "tcsrcc-x1e80100",
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.of_match_table = tcsr_cc_x1e80100_match_table,
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},
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};
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static int __init tcsr_cc_x1e80100_init(void)
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{
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return platform_driver_register(&tcsr_cc_x1e80100_driver);
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}
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subsys_initcall(tcsr_cc_x1e80100_init);
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static void __exit tcsr_cc_x1e80100_exit(void)
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{
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platform_driver_unregister(&tcsr_cc_x1e80100_driver);
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}
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module_exit(tcsr_cc_x1e80100_exit);
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MODULE_DESCRIPTION("QTI TCSR Clock Controller X1E80100 Driver");
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MODULE_LICENSE("GPL");
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