IOMMU Fixes for Linux v5.16-rc2:
Including: - Intel VT-d fixes: - Remove unused PASID_DISABLED - Fix RCU locking - Fix for the unmap_pages call-back - Rockchip RK3568 address mask fix - AMD IOMMUv2 log message clarification -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmGjhDgACgkQK/BELZcB GuMOiQ/+MPfnGSpKtEdID/p9d7yo97M/WKRhx5aT27hfW4gyyLtAO22vUTfZ/obK Mmwl/mthMm55BuzOes8/ka7zcrkaluJitFGWVLN6dzXZRTZc2nMdYQb1Y25IZVEP AwTDdfi8btPRYRrZ1vpXZtDzF5purGe0a5P0psUox7roSq+uWZcXOy3WZDbPNA9b pAwPTacnxbeSrElOF6rUyv5eXilvMDMG/1lF4/gFR89xAYcDIPpWNLuRWNYWxu2M qTbGBGXnSs/iIzRmBs5rhqbR5VQAb8tXQjjMBb5wWx9i6gaw217wHZPQrpS6ej3Z E8vpD/z/kxsMLBpiNM34an/3krgzm6alhA6dalZsvGdAvQHWj4LGma72lCBYsuM1 +Lre4MvMJ1kvONH9aWoMJWZEITnL2pS3Afu72vhg+7ank4xI/5Ej3bO7mYfN2MV+ XeEgIUv6HJioJ8ITwYyApJskDk0CLGvfmyHADwe+rj4A+YYzOgEv6kGQlZWzaNWa ISDibSMa4od4rw63CLS+rq4vK13MhfyerLZl9IMpvqcUKuWrb3SCiGjTLg5iWkL0 eqoIIvMuUavmTNG6HMOwfUMNN963osLJPXjwMYkzWbbpusLqb38KvLCed3xGS8tb KwhFggAF9Qt++bjo9V8zk5FdAovW0n4m5Nu6WDFcMwPCxccy3xc= =+B76 -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v5.16-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu fixes from Joerg Roedel: - Intel VT-d fixes: - Remove unused PASID_DISABLED - Fix RCU locking - Fix for the unmap_pages call-back - Rockchip RK3568 address mask fix - AMD IOMMUv2 log message clarification * tag 'iommu-fixes-v5.16-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/vt-d: Fix unmap_pages support iommu/vt-d: Fix an unbalanced rcu_read_lock/rcu_read_unlock() iommu/rockchip: Fix PAGE_DESC_HI_MASKs for RK3568 iommu/amd: Clarify AMD IOMMUv2 initialization messages iommu/vt-d: Remove unused PASID_DISABLED
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commit
0757ca01d9
@ -102,12 +102,6 @@ extern void switch_fpu_return(void);
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*/
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extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name);
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/*
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* Tasks that are not using SVA have mm->pasid set to zero to note that they
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* will not have the valid bit set in MSR_IA32_PASID while they are running.
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*/
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#define PASID_DISABLED 0
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/* Trap handling */
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extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
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extern void fpu_sync_fpstate(struct fpu *fpu);
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@ -929,10 +929,8 @@ static int __init amd_iommu_v2_init(void)
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{
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int ret;
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pr_info("AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>\n");
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if (!amd_iommu_v2_supported()) {
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pr_info("AMD IOMMUv2 functionality not available on this system\n");
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pr_info("AMD IOMMUv2 functionality not available on this system - This is not a bug.\n");
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/*
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* Load anyway to provide the symbols to other modules
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* which may use AMD IOMMUv2 optionally.
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@ -947,6 +945,8 @@ static int __init amd_iommu_v2_init(void)
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amd_iommu_register_ppr_notifier(&ppr_nb);
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pr_info("AMD IOMMUv2 loaded and initialized\n");
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return 0;
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out:
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@ -144,6 +144,7 @@ static int cap_audit_static(struct intel_iommu *iommu, enum cap_audit_type type)
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{
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struct dmar_drhd_unit *d;
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struct intel_iommu *i;
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int rc = 0;
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rcu_read_lock();
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if (list_empty(&dmar_drhd_units))
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@ -169,11 +170,11 @@ static int cap_audit_static(struct intel_iommu *iommu, enum cap_audit_type type)
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*/
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if (intel_cap_smts_sanity() &&
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!intel_cap_flts_sanity() && !intel_cap_slts_sanity())
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return -EOPNOTSUPP;
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rc = -EOPNOTSUPP;
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out:
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rcu_read_unlock();
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return 0;
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return rc;
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}
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int intel_cap_audit(enum cap_audit_type type, struct intel_iommu *iommu)
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@ -1339,13 +1339,11 @@ static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
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pte = &pte[pfn_level_offset(pfn, level)];
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do {
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unsigned long level_pfn;
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unsigned long level_pfn = pfn & level_mask(level);
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if (!dma_pte_present(pte))
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goto next;
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level_pfn = pfn & level_mask(level);
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/* If range covers entire pagetable, free it */
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if (start_pfn <= level_pfn &&
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last_pfn >= level_pfn + level_size(level) - 1) {
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@ -1366,7 +1364,7 @@ static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
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freelist);
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}
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next:
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pfn += level_size(level);
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pfn = level_pfn + level_size(level);
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} while (!first_pte_in_page(++pte) && pfn <= last_pfn);
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if (first_pte)
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@ -200,8 +200,8 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
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#define DTE_HI_MASK2 GENMASK(7, 4)
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#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
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#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
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#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
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#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
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#define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32)
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#define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36)
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static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
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{
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