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clk: rockchip: fix rk3188 sclk_smc gate data

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[ Upstream commit a9f0c0e563717b9f63b3bb1c4a7c2df436a206d9 ]

Fix sclk_smc gate data.
Change variable order, flags come before the register address.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx9999@hotmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Finley Xiao 2018-11-14 15:45:49 +00:00 committed by Greg Kroah-Hartman
parent 095d4dbe73
commit 0759b23e9e
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3188.c
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@ -391,8 +391,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
* Clock-Architecture Diagram 4
*/
GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
RK2928_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,