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drm/rockchip: vop2: set bg dly and prescan dly at vop2_post_config

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We need to setup background delay cycle and prescan
delay cycle when a mode is enable to avoid trigger
POST_BUF_EMPTY irq on rk3588.

Note: RK356x has no such requirement.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211115815.1785131-1-andyshrk@163.com
This commit is contained in:
Andy Yan 2023-12-11 19:58:15 +08:00 committed by Heiko Stuebner
parent dd49ee4614
commit 075a5b3969
1 changed files with 10 additions and 16 deletions
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26
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@ -1460,8 +1460,18 @@ static void vop2_post_config(struct drm_crtc *crtc)
u32 top_margin = 100, bottom_margin = 100;
u16 hsize = hdisplay * (left_margin + right_margin) / 200;
u16 vsize = vdisplay * (top_margin + bottom_margin) / 200;
u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
u16 hact_end, vact_end;
u32 val;
u32 bg_dly;
u32 pre_scan_dly;
bg_dly = vp->data->pre_scan_max_dly[3];
vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
vsize = rounddown(vsize, 2);
hsize = rounddown(hsize, 2);
@ -1956,11 +1966,6 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
u32 layer_sel = 0;
u32 port_sel;
unsigned int nlayer, ofs;
struct drm_display_mode *adjusted_mode;
u16 hsync_len;
u16 hdisplay;
u32 bg_dly;
u32 pre_scan_dly;
u32 ovl_ctrl;
int i;
struct vop2_video_port *vp0 = &vop2->vps[0];
@ -1968,17 +1973,6 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
struct vop2_video_port *vp2 = &vop2->vps[2];
struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
adjusted_mode = &vp->crtc.state->adjusted_mode;
hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
hdisplay = adjusted_mode->crtc_hdisplay;
bg_dly = vp->data->pre_scan_max_dly[3];
vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;
if (vcstate->yuv_overlay)