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wifi: rtw89: 8851b: configure to force 1 TX power value

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RTL8851B is a chip with only single RF path, and it must use 1 TX power
value for transmission, so force 1 TX power value to prevent hardware
logic gets wrong TX power values randomly in certain samples.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230615130442.18116-6-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2023-06-15 21:04:42 +08:00 committed by Kalle Valo
parent 76a7c7acaa
commit 076031a09a
2 changed files with 25 additions and 0 deletions
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22
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -3333,6 +3333,28 @@
#define R_AX_PWR_UL_CTRL2 0xD248
#define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
#define B_AX_PWR_UL_CTRL2_MASK 0x07700007
#define R_AX_PWR_NORM_FORCE1 0xD260
#define R_AX_PWR_NORM_FORCE1_C1 0xF260
#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29)
#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24)
#define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23)
#define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22)
#define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21)
#define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20)
#define B_AX_FORCE_BT_GRANT_EN BIT(19)
#define B_AX_FORCE_BT_GRANT_VALUE BIT(18)
#define B_AX_FORCE_RX_LTE_EN BIT(17)
#define B_AX_FORCE_RX_LTE_VALUE BIT(16)
#define B_AX_FORCE_TXBF_EN_EN BIT(15)
#define B_AX_FORCE_TXBF_EN_VALUE BIT(14)
#define B_AX_FORCE_TXSC_EN BIT(13)
#define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9)
#define B_AX_FORCE_NTX_EN BIT(6)
#define B_AX_FORCE_NTX_VALUE BIT(5)
#define B_AX_FORCE_PWR_MODE_EN BIT(3)
#define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0)
#define R_AX_PWR_UL_TB_CTRL 0xD288
#define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
#define R_AX_PWR_UL_TB_1T 0xD28C

3
drivers/net/wireless/realtek/rtw89/rtw8851b.c
View File

@ -1442,6 +1442,9 @@ static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
rtw8851b_bb_gpio_init(rtwdev);
rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
/* read these registers after loading BB parameters */
gain->offset_base[RTW89_PHY_0] =
rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);