hwrng: n2 - support new hardware register layout
Add the new register layout constants and the requisite logic for using them. Signed-off-by: Shannon Nelson <shannon.nelson@oracle.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Shannon Nelson
Herbert Xu
parent
becbc4940a
commit
07e25d43be
@ -302,26 +302,57 @@ static int n2rng_try_read_ctl(struct n2rng *np)
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return n2rng_hv_err_trans(hv_err);
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}
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#define CONTROL_DEFAULT_BASE \
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((2 << RNG_CTL_ASEL_SHIFT) | \
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(N2RNG_ACCUM_CYCLES_DEFAULT << RNG_CTL_WAIT_SHIFT) | \
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RNG_CTL_LFSR)
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static u64 n2rng_control_default(struct n2rng *np, int ctl)
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{
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u64 val = 0;
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#define CONTROL_DEFAULT_0 \
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(CONTROL_DEFAULT_BASE | \
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(1 << RNG_CTL_VCO_SHIFT) | \
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RNG_CTL_ES1)
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#define CONTROL_DEFAULT_1 \
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(CONTROL_DEFAULT_BASE | \
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(2 << RNG_CTL_VCO_SHIFT) | \
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RNG_CTL_ES2)
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#define CONTROL_DEFAULT_2 \
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(CONTROL_DEFAULT_BASE | \
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(3 << RNG_CTL_VCO_SHIFT) | \
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RNG_CTL_ES3)
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#define CONTROL_DEFAULT_3 \
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(CONTROL_DEFAULT_BASE | \
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RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3)
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if (np->data->chip_version == 1) {
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val = ((2 << RNG_v1_CTL_ASEL_SHIFT) |
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(N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v1_CTL_WAIT_SHIFT) |
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RNG_CTL_LFSR);
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switch (ctl) {
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case 0:
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val |= (1 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES1;
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break;
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case 1:
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val |= (2 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES2;
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break;
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case 2:
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val |= (3 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES3;
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break;
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case 3:
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val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3;
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break;
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default:
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break;
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}
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} else {
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val = ((2 << RNG_v2_CTL_ASEL_SHIFT) |
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(N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v2_CTL_WAIT_SHIFT) |
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RNG_CTL_LFSR);
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switch (ctl) {
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case 0:
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val |= (1 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES1;
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break;
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case 1:
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val |= (2 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES2;
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break;
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case 2:
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val |= (3 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES3;
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break;
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case 3:
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val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3;
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break;
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default:
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break;
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}
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}
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return val;
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}
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static void n2rng_control_swstate_init(struct n2rng *np)
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{
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@ -336,10 +367,10 @@ static void n2rng_control_swstate_init(struct n2rng *np)
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for (i = 0; i < np->num_units; i++) {
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struct n2rng_unit *up = &np->units[i];
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up->control[0] = CONTROL_DEFAULT_0;
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up->control[1] = CONTROL_DEFAULT_1;
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up->control[2] = CONTROL_DEFAULT_2;
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up->control[3] = CONTROL_DEFAULT_3;
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up->control[0] = n2rng_control_default(np, 0);
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up->control[1] = n2rng_control_default(np, 1);
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up->control[2] = n2rng_control_default(np, 2);
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up->control[3] = n2rng_control_default(np, 3);
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}
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np->hv_state = HV_RNG_STATE_UNCONFIGURED;
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@ -399,6 +430,7 @@ static int n2rng_data_read(struct hwrng *rng, u32 *data)
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} else {
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int err = n2rng_generic_read_data(ra);
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if (!err) {
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np->flags |= N2RNG_FLAG_BUFFER_VALID;
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np->buffer = np->test_data >> 32;
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*data = np->test_data & 0xffffffff;
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len = 4;
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@ -487,9 +519,21 @@ static void n2rng_dump_test_buffer(struct n2rng *np)
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static int n2rng_check_selftest_buffer(struct n2rng *np, unsigned long unit)
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{
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u64 val = SELFTEST_VAL;
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u64 val;
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int err, matches, limit;
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switch (np->data->id) {
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case N2_n2_rng:
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case N2_vf_rng:
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case N2_kt_rng:
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case N2_m4_rng: /* yes, m4 uses the old value */
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val = RNG_v1_SELFTEST_VAL;
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break;
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default:
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val = RNG_v2_SELFTEST_VAL;
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break;
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}
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matches = 0;
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for (limit = 0; limit < SELFTEST_LOOPS_MAX; limit++) {
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matches += n2rng_test_buffer_find(np, val);
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@ -512,14 +556,32 @@ static int n2rng_check_selftest_buffer(struct n2rng *np, unsigned long unit)
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static int n2rng_control_selftest(struct n2rng *np, unsigned long unit)
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{
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int err;
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u64 base, base3;
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np->test_control[0] = (0x2 << RNG_CTL_ASEL_SHIFT);
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np->test_control[1] = (0x2 << RNG_CTL_ASEL_SHIFT);
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np->test_control[2] = (0x2 << RNG_CTL_ASEL_SHIFT);
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np->test_control[3] = ((0x2 << RNG_CTL_ASEL_SHIFT) |
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RNG_CTL_LFSR |
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((SELFTEST_TICKS - 2) << RNG_CTL_WAIT_SHIFT));
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switch (np->data->id) {
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case N2_n2_rng:
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case N2_vf_rng:
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case N2_kt_rng:
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base = RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT;
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base3 = base | RNG_CTL_LFSR |
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((RNG_v1_SELFTEST_TICKS - 2) << RNG_v1_CTL_WAIT_SHIFT);
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break;
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case N2_m4_rng:
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base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT;
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base3 = base | RNG_CTL_LFSR |
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((RNG_v1_SELFTEST_TICKS - 2) << RNG_v2_CTL_WAIT_SHIFT);
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break;
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default:
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base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT;
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base3 = base | RNG_CTL_LFSR |
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(RNG_v2_SELFTEST_TICKS << RNG_v2_CTL_WAIT_SHIFT);
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break;
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}
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np->test_control[0] = base;
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np->test_control[1] = base;
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np->test_control[2] = base;
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np->test_control[3] = base3;
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err = n2rng_entropy_diag_read(np, unit, np->test_control,
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HV_RNG_STATE_HEALTHCHECK,
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@ -557,11 +619,19 @@ static int n2rng_control_configure_units(struct n2rng *np)
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struct n2rng_unit *up = &np->units[unit];
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unsigned long ctl_ra = __pa(&up->control[0]);
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int esrc;
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u64 base;
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u64 base, shift;
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base = ((np->accum_cycles << RNG_CTL_WAIT_SHIFT) |
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(2 << RNG_CTL_ASEL_SHIFT) |
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RNG_CTL_LFSR);
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if (np->data->chip_version == 1) {
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base = ((np->accum_cycles << RNG_v1_CTL_WAIT_SHIFT) |
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(RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT) |
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RNG_CTL_LFSR);
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shift = RNG_v1_CTL_VCO_SHIFT;
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} else {
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base = ((np->accum_cycles << RNG_v2_CTL_WAIT_SHIFT) |
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(RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT) |
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RNG_CTL_LFSR);
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shift = RNG_v2_CTL_VCO_SHIFT;
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}
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/* XXX This isn't the best. We should fetch a bunch
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* XXX of words using each entropy source combined XXX
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@ -570,7 +640,7 @@ static int n2rng_control_configure_units(struct n2rng *np)
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*/
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for (esrc = 0; esrc < 3; esrc++)
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up->control[esrc] = base |
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(esrc << RNG_CTL_VCO_SHIFT) |
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(esrc << shift) |
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(RNG_CTL_ES1 << esrc);
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up->control[3] = base |
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@ -6,18 +6,34 @@
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#ifndef _N2RNG_H
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#define _N2RNG_H
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#define RNG_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
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#define RNG_CTL_WAIT_SHIFT 9
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#define RNG_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
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#define RNG_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
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#define RNG_CTL_VCO_SHIFT 6
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#define RNG_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
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#define RNG_CTL_ASEL_SHIFT 4
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/* ver1 devices - n2-rng, vf-rng, kt-rng */
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#define RNG_v1_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
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#define RNG_v1_CTL_WAIT_SHIFT 9
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#define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
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#define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
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#define RNG_v1_CTL_VCO_SHIFT 6
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#define RNG_v1_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
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#define RNG_v1_CTL_ASEL_SHIFT 4
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#define RNG_v1_CTL_ASEL_NOOUT 2
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/* these are the same in v2 as in v1 */
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#define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */
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#define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */
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#define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */
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#define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */
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/* ver2 devices - m4-rng, m7-rng */
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#define RNG_v2_CTL_WAIT 0x0000000007fff800ULL /* Minimum wait time */
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#define RNG_v2_CTL_WAIT_SHIFT 12
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#define RNG_v2_CTL_BYPASS 0x0000000000000400ULL /* VCO voltage source */
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#define RNG_v2_CTL_VCO 0x0000000000000300ULL /* VCO rate control */
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#define RNG_v2_CTL_VCO_SHIFT 9
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#define RNG_v2_CTL_PERF 0x0000000000000180ULL /* Perf */
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#define RNG_v2_CTL_ASEL 0x0000000000000070ULL /* Analog MUX select */
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#define RNG_v2_CTL_ASEL_SHIFT 4
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#define RNG_v2_CTL_ASEL_NOOUT 7
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#define HV_FAST_RNG_GET_DIAG_CTL 0x130
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#define HV_FAST_RNG_CTL_READ 0x131
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#define HV_FAST_RNG_CTL_WRITE 0x132
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@ -112,8 +128,10 @@ struct n2rng {
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u64 scratch_control[HV_RNG_NUM_CONTROL];
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#define SELFTEST_TICKS 38859
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#define SELFTEST_VAL ((u64)0xB8820C7BD387E32C)
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#define RNG_v1_SELFTEST_TICKS 38859
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#define RNG_v1_SELFTEST_VAL ((u64)0xB8820C7BD387E32C)
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#define RNG_v2_SELFTEST_TICKS 64
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#define RNG_v2_SELFTEST_VAL ((u64)0xffffffffffffffff)
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#define SELFTEST_POLY ((u64)0x231DCEE91262B8A3)
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#define SELFTEST_MATCH_GOAL 6
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#define SELFTEST_LOOPS_MAX 40000
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