ARM: SoC: late DT updates for v4.7
This is a collection of a few late fixes and other misc. stuff that had dependencies on things being merged from other trees. The Renesas R-Car power domain handling, and the Nvidia Tegra USB support both hand notable changes that required changing the DT binding in a way that only provides compatibility with old DT blobs on new kernels but not vice versa. As a consequence, the DT changes are based on top of the driver changes and are now in this branch. For NXP i.MX and Samsung Exynos, the changes in here depend on other changes that got merged through the clk maintainer tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAV0Sse2CrR//JCVInAQJoOg//VQwAUxayKGfYVzhJjhHdYbVA9kWYczHb wizFbF51XPylQzfGgHxEZJgdO3y2Ks54J7xaCK7oSUPEBT0rHsLQunHhq0aVQpew 1c06vEysYMkRclG7C0zN7i4gwdig+L4r6kUguTvb+nyJS3RISg0LaSoANVU65dQ5 +g4DLRrX1QlZPBXR8Fc/S1gTFXU+dO1S0oJFnK9ZZTgmsGg4GA0qC60hdsv+WeSv uzS4FJoxSy9MzoAFqmnWIa4jBV9I1Rg5vi7dfoBbTW1XOAMpq+GVLLU+Lvso0Jqw xWjBSmPl6l/cZ7BhpzWq8knKOsEezh5LLrVRXViVCGfTIFdlObxyHzeKcJp25V1p mL98MBXobn9Rly9hJxyzpeNWITZ6qJYR+IQy3Lsuk5KrdZG2f4uTErtoqmYRI3Pn vuXoi13NUeoCrHZJZ+fNUGwx5a5/hgUQXP5u+98uucQSqIVxe0cGnQVnFm84X81r Sj/dXxFlFBZfqfE8rf1cFd+YEbKtpF13vEURAQWrnEzBmJSTu7Cp8qdA5hX5CeK4 DW9bsu5hkWwnzoC2Ox/ZQVms4aI3q8s2xuu28GEJJdCE2IUiSnag/5vhGBzd4dTm 9R69RhE9y4EOhw+0z1O0LfoKoo6YyUQa+OUNVIwEfFjcCdZiMQIdZWi2PLv4jeAR jBBbpcWtHLo= =I0Be -----END PGP SIGNATURE----- Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "This is a collection of a few late fixes and other misc stuff that had dependencies on things being merged from other trees. The Renesas R-Car power domain handling, and the Nvidia Tegra USB support both hand notable changes that required changing the DT binding in a way that only provides compatibility with old DT blobs on new kernels but not vice versa. As a consequence, the DT changes are based on top of the driver changes and are now in this branch. For NXP i.MX and Samsung Exynos, the changes in here depend on other changes that got merged through the clk maintainer tree" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (35 commits) ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 ARM: tegra: Enable XUSB on Nyan ARM: tegra: Enable XUSB on Jetson TK1 ARM: tegra: Enable XUSB on Venice2 ARM: tegra: Add Tegra124 XUSB controller ARM: tegra: Move Tegra124 to the new XUSB pad controller binding ARM: dts: r8a7794: Use SYSC "always-on" PM Domain ARM: dts: r8a7793: Use SYSC "always-on" PM Domain ...
This commit is contained in:
Linus Torvalds
commit
08344f3b43
@ -399,6 +399,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
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imx6ul-tx6ul-mainboard.dtb
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dtb-$(CONFIG_SOC_IMX7D) += \
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imx7d-cl-som-imx7.dtb \
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imx7d-nitrogen7.dtb \
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imx7d-sbc-imx7.dtb \
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imx7d-sdb.dtb
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dtb-$(CONFIG_SOC_LS1021A) += \
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@ -14,6 +14,7 @@
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/dts-v1/;
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#include "exynos3250.dtsi"
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#include "exynos4412-ppmu-common.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/samsung,s2mps11.h>
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@ -156,6 +157,12 @@
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};
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};
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&bus_dmc {
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devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
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vdd-supply = <&buck1_reg>;
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status = "okay";
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};
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&cpu0 {
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cpu0-supply = <&buck2_reg>;
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};
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@ -458,46 +465,6 @@
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status = "okay";
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};
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&ppmu_dmc0 {
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status = "okay";
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events {
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ppmu_dmc0_3: ppmu-event3-dmc0 {
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event-name = "ppmu-event3-dmc0";
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};
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};
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};
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&ppmu_dmc1 {
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status = "okay";
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events {
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ppmu_dmc1_3: ppmu-event3-dmc1 {
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event-name = "ppmu-event3-dmc1";
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};
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};
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};
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&ppmu_leftbus {
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status = "okay";
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events {
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ppmu_leftbus_3: ppmu-event3-leftbus {
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event-name = "ppmu-event3-leftbus";
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};
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};
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};
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&ppmu_rightbus {
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status = "okay";
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events {
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ppmu_rightbus_3: ppmu-event3-rightbus {
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event-name = "ppmu-event3-rightbus";
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};
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};
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};
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&xusbxti {
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clock-frequency = <24000000>;
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};
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@ -14,6 +14,7 @@
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/dts-v1/;
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#include "exynos3250.dtsi"
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#include "exynos4412-ppmu-common.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/samsung,s2mps11.h>
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@ -147,6 +148,53 @@
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};
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};
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&bus_dmc {
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devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
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vdd-supply = <&buck1_reg>;
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status = "okay";
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};
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&bus_leftbus {
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devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
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vdd-supply = <&buck3_reg>;
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status = "okay";
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};
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&bus_rightbus {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_lcd0 {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_fsys {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_mcuisp {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_isp {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_peril {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_mfc {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&cpu0 {
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cpu0-supply = <&buck2_reg>;
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};
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@ -635,46 +683,6 @@
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status = "okay";
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};
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&ppmu_dmc0 {
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status = "okay";
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events {
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ppmu_dmc0_3: ppmu-event3-dmc0 {
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event-name = "ppmu-event3-dmc0";
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};
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};
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};
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&ppmu_dmc1 {
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status = "okay";
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events {
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ppmu_dmc1_3: ppmu-event3-dmc1 {
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event-name = "ppmu-event3-dmc1";
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};
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};
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};
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&ppmu_leftbus {
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status = "okay";
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events {
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ppmu_leftbus_3: ppmu-event3-leftbus {
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event-name = "ppmu-event3-leftbus";
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};
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};
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};
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&ppmu_rightbus {
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status = "okay";
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events {
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ppmu_rightbus_3: ppmu-event3-rightbus {
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event-name = "ppmu-event3-rightbus";
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};
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};
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};
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&xusbxti {
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clock-frequency = <24000000>;
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};
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@ -713,6 +713,187 @@
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clock-names = "ppmu";
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status = "disabled";
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};
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bus_dmc: bus_dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu_dmc CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_dmc_opp_table: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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opp-microvolt = <800000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <800000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <800000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <825000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <875000>;
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};
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};
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bus_leftbus: bus_leftbus {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_GDL>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_rightbus: bus_rightbus {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_GDR>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_lcd0: bus_lcd0 {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_160>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_fsys: bus_fsys {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_200>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_mcuisp: bus_mcuisp {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_mcuisp_opp_table>;
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status = "disabled";
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};
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bus_isp: bus_isp {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_266>;
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clock-names = "bus";
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operating-points-v2 = <&bus_isp_opp_table>;
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status = "disabled";
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};
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bus_peril: bus_peril {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_100>;
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clock-names = "bus";
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operating-points-v2 = <&bus_peril_opp_table>;
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status = "disabled";
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};
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bus_mfc: bus_mfc {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_SCLK_MFC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_leftbus_opp_table: opp_table2 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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opp-microvolt = <900000>;
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};
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opp@80000000 {
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opp-hz = /bits/ 64 <80000000>;
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opp-microvolt = <900000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <1000000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <1000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <1000000>;
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};
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};
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bus_mcuisp_opp_table: opp_table3 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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};
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opp@80000000 {
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opp-hz = /bits/ 64 <80000000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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};
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};
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bus_isp_opp_table: opp_table4 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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};
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opp@80000000 {
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opp-hz = /bits/ 64 <80000000>;
|
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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||||
};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
|
||||
};
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||||
opp@300000000 {
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opp-hz = /bits/ 64 <300000000>;
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||||
};
|
||||
};
|
||||
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||||
bus_peril_opp_table: opp_table5 {
|
||||
compatible = "operating-points-v2";
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||||
opp-shared;
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||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -257,6 +257,165 @@
|
||||
power-domains = <&pd_lcd1>;
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
||||
bus_dmc: bus_dmc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_DMC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_dmc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_acp: bus_acp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_ACP>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_acp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_peri: bus_peri {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK100>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_peri_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys: bus_fsys {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK133>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_display: bus_display {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK160>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_display_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_lcd0: bus_lcd0 {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK200>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_leftbus: bus_leftbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_GDL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_rightbus: bus_rightbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_GDR>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mfc: bus_mfc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_SCLK_MFC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_dmc_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
};
|
||||
opp@267000000 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_acp_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_peri_opp_table: opp_table3 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@5000000 {
|
||||
opp-hz = /bits/ 64 <5000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_fsys_opp_table: opp_table4 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@10000000 {
|
||||
opp-hz = /bits/ 64 <10000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_display_opp_table: opp_table5 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_leftbus_opp_table: opp_table6 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gic {
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/clock/maxim,max77686.h>
|
||||
#include "exynos4412.dtsi"
|
||||
#include "exynos4412-ppmu-common.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
@ -108,6 +109,53 @@
|
||||
};
|
||||
};
|
||||
|
||||
&bus_dmc {
|
||||
devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
|
||||
vdd-supply = <&buck1_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_acp {
|
||||
devfreq = <&bus_dmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_c2c {
|
||||
devfreq = <&bus_dmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_leftbus {
|
||||
devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
|
||||
vdd-supply = <&buck3_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_rightbus {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_display {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_peri {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mfc {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&buck2_reg>;
|
||||
};
|
||||
@ -359,8 +407,8 @@
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
@ -375,8 +423,8 @@
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
50
arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
Normal file
50
arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Device tree sources for Exynos4412 PPMU common device tree
|
||||
*
|
||||
* Copyright (C) 2015 Samsung Electronics
|
||||
* Author: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&ppmu_dmc0 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_dmc1 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc1_3: ppmu-event3-dmc1 {
|
||||
event-name = "ppmu-event3-dmc1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_leftbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_leftbus_3: ppmu-event3-leftbus {
|
||||
event-name = "ppmu-event3-leftbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_rightbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_rightbus_3: ppmu-event3-rightbus {
|
||||
event-name = "ppmu-event3-rightbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -14,6 +14,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos4412.dtsi"
|
||||
#include "exynos4412-ppmu-common.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/maxim,max77686.h>
|
||||
@ -288,6 +289,53 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_dmc {
|
||||
devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
|
||||
vdd-supply = <&buck1_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_acp {
|
||||
devfreq = <&bus_dmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_c2c {
|
||||
devfreq = <&bus_dmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_leftbus {
|
||||
devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
|
||||
vdd-supply = <&buck3_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_rightbus {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_display {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_peri {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mfc {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&buck2_reg>;
|
||||
};
|
||||
@ -871,46 +919,6 @@
|
||||
assigned-clock-parents = <&clock CLK_XUSBXTI>;
|
||||
};
|
||||
|
||||
&ppmu_dmc0 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_dmc1 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc1_3: ppmu-event3-dmc1 {
|
||||
event-name = "ppmu-event3-dmc1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_leftbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_leftbus_3: ppmu-event3-leftbus {
|
||||
event-name = "ppmu-event3-leftbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_rightbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_rightbus_3: ppmu-event3-rightbus {
|
||||
event-name = "ppmu-event3-rightbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sleep0>;
|
||||
|
||||
@ -281,6 +281,180 @@
|
||||
clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
||||
bus_dmc: bus_dmc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_DMC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_dmc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_acp: bus_acp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_ACP>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_acp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_c2c: bus_c2c {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_C2C>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_dmc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_dmc_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@267000000 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_acp_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
opp@267000000 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_leftbus: bus_leftbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_GDL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_rightbus: bus_rightbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_GDR>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_display: bus_display {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK160>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_display_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys: bus_fsys {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK133>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_peri: bus_peri {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK100>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_peri_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mfc: bus_mfc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_SCLK_MFC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_leftbus_opp_table: opp_table3 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <925000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_display_opp_table: opp_table4 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_fsys_opp_table: opp_table5 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_peri_opp_table: opp_table6 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combiner {
|
||||
|
||||
@ -294,6 +294,42 @@
|
||||
};
|
||||
};
|
||||
|
||||
nocp_mem0_0: nocp@10CA1000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1000 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_mem0_1: nocp@10CA1400 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1400 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_mem1_0: nocp@10CA1800 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1800 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_mem1_1: nocp@10CA1C00 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1C00 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_g3d_0: nocp@11A51000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x11A51000 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_g3d_1: nocp@11A51400 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x11A51400 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsc_pd: power-domain@10044000 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044000 0x20>;
|
||||
@ -1188,6 +1224,377 @@
|
||||
power-domains = <&disp_pd>;
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
||||
bus_wcore: bus_wcore {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_wcore_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_noc: bus_noc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_noc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys_apb: bus_fsys_apb {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys_apb_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys: bus_fsys {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys_apb_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys2: bus_fsys2 {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys2_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mfc: bus_mfc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK333>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_mfc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_gen: bus_gen {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK266>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_gen_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_peri: bus_peri {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK66>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_peri_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_g2d: bus_g2d {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_g2d_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_g2d_acp: bus_g2d_acp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_g2d_acp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_jpeg: bus_jpeg {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_jpeg_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_jpeg_apb: bus_jpeg_apb {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK166>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_disp1_fimd: bus_disp1_fimd {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_disp1: bus_disp1 {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_disp1_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_gscl_scaler: bus_gscl_scaler {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_gscl_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mscl: bus_mscl {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_mscl_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_wcore_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <84000000>;
|
||||
opp-microvolt = <925000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <111000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <222000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <333000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <987500>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_noc_opp_table: opp_table3 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <67000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <86000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_fsys_apb_opp_table: opp_table4 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_fsys2_opp_table: opp_table5 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <150000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_mfc_opp_table: opp_table6 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <96000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <111000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <167000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <222000000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <333000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_gen_opp_table: opp_table7 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <89000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <133000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <178000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_peri_opp_table: opp_table8 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <67000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_g2d_opp_table: opp_table9 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <84000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <167000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <222000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <333000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_g2d_acp_opp_table: opp_table10 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <67000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <133000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <178000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_jpeg_opp_table: opp_table11 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <150000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_jpeg_apb_opp_table: opp_table12 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <84000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <111000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <167000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_disp1_fimd_opp_table: opp_table13 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <120000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_disp1_opp_table: opp_table14 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <120000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_gscl_opp_table: opp_table15 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <150000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_mscl_opp_table: opp_table16 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <84000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <167000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <222000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <333000000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dp {
|
||||
|
||||
@ -56,6 +56,89 @@
|
||||
};
|
||||
};
|
||||
|
||||
&bus_wcore {
|
||||
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
|
||||
<&nocp_mem1_0>, <&nocp_mem1_1>;
|
||||
vdd-supply = <&buck3_reg>;
|
||||
exynos,saturation-ratio = <100>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_noc {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys_apb {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys2 {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mfc {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_gen {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_peri {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_g2d {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_g2d_acp {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_jpeg {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_jpeg_apb {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_disp1_fimd {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_disp1 {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_gscl_scaler {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mscl {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clock_audss {
|
||||
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
|
||||
<&clock_audss EXYNOS_MOUT_I2S>,
|
||||
@ -361,6 +444,22 @@
|
||||
vqmmc-supply = <&ldo13_reg>;
|
||||
};
|
||||
|
||||
&nocp_mem0_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nocp_mem0_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nocp_mem1_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nocp_mem1_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
hdmi_hpd_irq: hdmi-hpd-irq {
|
||||
samsung,pins = "gpx3-7";
|
||||
|
||||
745
arch/arm/boot/dts/imx7d-nitrogen7.dts
Normal file
745
arch/arm/boot/dts/imx7d-nitrogen7.dts
Normal file
@ -0,0 +1,745 @@
|
||||
/*
|
||||
* Copyright 2016 Boundary Devices, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "imx7d.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Boundary Devices i.MX7 Nitrogen7 Board";
|
||||
compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
|
||||
|
||||
aliases {
|
||||
fb_lcd = &lcdif;
|
||||
t_lcd = &t_lcd;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
backlight-j9 {
|
||||
compatible = "gpio-backlight";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_backlight_j9>;
|
||||
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
default-on;
|
||||
};
|
||||
|
||||
backlight-j20 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg2_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_can2_3v3: regulator-can2-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "can2-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
reg_vref_1v8: regulator-vref-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vref-1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
reg_vref_3v3: regulator-vref-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vref-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_wlan: regulator-wlan {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
|
||||
clock-names = "slow";
|
||||
regulator-name = "reg_wlan";
|
||||
startup-delay-us = <70000>;
|
||||
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&adc1 {
|
||||
vref-supply = <®_vref_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&adc2 {
|
||||
vref-supply = <®_vref_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
|
||||
<&clks IMX7D_CLKO2_ROOT_DIV>;
|
||||
assigned-clock-parents = <&clks IMX7D_CKIL>;
|
||||
assigned-clock-rates = <0>, <32768>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
arm-supply = <&sw1a_reg>;
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
|
||||
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
|
||||
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
|
||||
assigned-clock-rates = <0>, <100000000>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&flexcan2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
xceiver-supply = <®_can2_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze3000@08 {
|
||||
compatible = "fsl,pfuze3000";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1a {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1475000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
/* use sw1c_reg to align with pfuze100/pfuze200 */
|
||||
sw1c_reg: sw1b {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1475000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1650000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vldo1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vldo2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vccsd {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: v33 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vldo3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vldo4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
rtc@68 {
|
||||
compatible = "rv4162";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_rv4162>;
|
||||
reg = <0x68>;
|
||||
interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
touch@48 {
|
||||
compatible = "ti,tsc2004";
|
||||
reg = <0x48>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
|
||||
interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
status = "okay";
|
||||
|
||||
codec: wm8960@1a {
|
||||
compatible = "wlf,wm8960";
|
||||
reg = <0x1a>;
|
||||
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
|
||||
clock-names = "mclk";
|
||||
wlf,shared-lrclk;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcdif_dat
|
||||
&pinctrl_lcdif_ctrl>;
|
||||
lcd-supply = <®_vref_3v3>;
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: lcd-display {
|
||||
bits-per-pixel = <16>;
|
||||
bus-width = <18>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&t_lcd>;
|
||||
t_lcd: t_lcd_default {
|
||||
/* default to Okaya display */
|
||||
clock-frequency = <30000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <40>;
|
||||
hback-porch = <40>;
|
||||
hsync-len = <48>;
|
||||
vback-porch = <29>;
|
||||
vfront-porch = <13>;
|
||||
vsync-len = <3>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
|
||||
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
|
||||
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
|
||||
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart6>;
|
||||
assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
|
||||
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
vbus-supply = <®_usb_otg2_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg2>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <&vgen3_reg>;
|
||||
bus-width = <4>;
|
||||
fsl,tuning-step = <2>;
|
||||
wakeup-source;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
vmmc-supply = <®_wlan>;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1271";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ref-clock-frequency = <38400000>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
bus-width = <8>;
|
||||
fsl,tuning-step = <2>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
|
||||
|
||||
pinctrl_hog_1: hoggrp-1 {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d
|
||||
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d
|
||||
MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
|
||||
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
|
||||
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3
|
||||
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
|
||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
|
||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
|
||||
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
|
||||
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
|
||||
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
|
||||
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71
|
||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
|
||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
|
||||
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
|
||||
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71
|
||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
|
||||
MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d
|
||||
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d
|
||||
MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
|
||||
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
|
||||
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_rv4162: i2c2-rv4162grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
|
||||
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79
|
||||
MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
|
||||
MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_j2: j2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d
|
||||
MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d
|
||||
MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d
|
||||
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d
|
||||
MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d
|
||||
MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d
|
||||
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d
|
||||
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d
|
||||
MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d
|
||||
MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d
|
||||
MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d
|
||||
MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d
|
||||
MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d
|
||||
MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d
|
||||
MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d
|
||||
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d
|
||||
MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d
|
||||
MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d
|
||||
MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d
|
||||
MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d
|
||||
MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d
|
||||
MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d
|
||||
MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d
|
||||
MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d
|
||||
MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d
|
||||
MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d
|
||||
MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d
|
||||
MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d
|
||||
MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d
|
||||
MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d
|
||||
MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d
|
||||
MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d
|
||||
MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d
|
||||
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d
|
||||
MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_dat: lcdifdatgrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
|
||||
MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
|
||||
MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
|
||||
MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
|
||||
MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
|
||||
MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
|
||||
MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
|
||||
MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
|
||||
MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
|
||||
MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
|
||||
MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
|
||||
MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
|
||||
MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
|
||||
MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
|
||||
MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
|
||||
MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
|
||||
MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
|
||||
MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
|
||||
MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
|
||||
MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
|
||||
MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
|
||||
MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
|
||||
MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
|
||||
MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LCD_CLK__LCD_CLK 0x79
|
||||
MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
|
||||
MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
|
||||
MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
|
||||
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
|
||||
MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
|
||||
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
|
||||
MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart6: uart6grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
|
||||
MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
|
||||
MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
|
||||
MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg2: usbotg2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d
|
||||
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
||||
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
||||
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
||||
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
||||
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
||||
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
||||
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75
|
||||
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
|
||||
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
|
||||
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
|
||||
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
|
||||
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
|
||||
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
|
||||
MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59
|
||||
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc_lpsr {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog_2>;
|
||||
|
||||
pinctrl_hog_2: hoggrp-2 {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x7d
|
||||
MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_backlight_j9: backlightj9grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x7d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1: usbotg1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x7d
|
||||
MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog1: wdog1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x75
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -651,6 +651,17 @@
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lcdif: lcdif@30730000 {
|
||||
compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
|
||||
reg = <0x30730000 0x10000>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
|
||||
<&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CLK_DUMMY>;
|
||||
clock-names = "pix", "axi", "disp_axi";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips3: aips-bus@30800000 {
|
||||
@ -693,6 +704,26 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
flexcan1: can@30a00000 {
|
||||
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
|
||||
reg = <0x30a00000 0x10000>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CAN1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
flexcan2: can@30a10000 {
|
||||
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
|
||||
reg = <0x30a10000 0x10000>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_CLK_DUMMY>,
|
||||
<&clks IMX7D_CAN2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#include <dt-bindings/clock/r8a7779-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7779-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7779";
|
||||
@ -34,18 +35,21 @@
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7779_PD_ARM1>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7779_PD_ARM2>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7779_PD_ARM3>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -173,7 +177,7 @@
|
||||
reg = <0xffc70000 0x1000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -184,7 +188,7 @@
|
||||
reg = <0xffc71000 0x1000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -195,7 +199,7 @@
|
||||
reg = <0xffc72000 0x1000>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -206,7 +210,7 @@
|
||||
reg = <0xffc73000 0x1000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -218,7 +222,7 @@
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -230,7 +234,7 @@
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -242,7 +246,7 @@
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -254,7 +258,7 @@
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -266,7 +270,7 @@
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -278,7 +282,7 @@
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
|
||||
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -300,7 +304,7 @@
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -315,7 +319,7 @@
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -330,7 +334,7 @@
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -342,7 +346,7 @@
|
||||
reg = <0xfc600000 0x2000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ffe4c000 {
|
||||
@ -350,7 +354,7 @@
|
||||
reg = <0xffe4c000 0x100>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -359,7 +363,7 @@
|
||||
reg = <0xffe4d000 0x100>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -368,7 +372,7 @@
|
||||
reg = <0xffe4e000 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -377,7 +381,7 @@
|
||||
reg = <0xffe4f000 0x100>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -388,7 +392,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -399,7 +403,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -410,7 +414,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -419,7 +423,7 @@
|
||||
reg = <0 0xfff80000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7779_CLK_DU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
@ -585,4 +589,10 @@
|
||||
"mmc1", "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@ffd85000 {
|
||||
compatible = "renesas,r8a7779-sysc";
|
||||
reg = <0xffd85000 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
#include <dt-bindings/clock/r8a7790-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7790";
|
||||
@ -52,6 +53,7 @@
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
clocks = <&cpg_clocks R8A7790_CLK_Z>;
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
|
||||
/* kHz - uV - OPPs unknown yet */
|
||||
@ -68,6 +70,7 @@
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
clock-frequency = <1300000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
@ -76,6 +79,7 @@
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <2>;
|
||||
clock-frequency = <1300000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
@ -84,6 +88,7 @@
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <3>;
|
||||
clock-frequency = <1300000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
@ -92,6 +97,7 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
clock-frequency = <780000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
@ -100,6 +106,7 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
clock-frequency = <780000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
@ -108,6 +115,7 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
clock-frequency = <780000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
@ -116,6 +124,7 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
clock-frequency = <780000000>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
};
|
||||
@ -141,12 +150,14 @@
|
||||
|
||||
L2_CA15: cache-controller@0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7790_PD_CA15_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
L2_CA7: cache-controller@1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7790_PD_CA7_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
@ -173,7 +184,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
@ -186,7 +197,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
@ -199,7 +210,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
@ -212,7 +223,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
@ -225,7 +236,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
@ -238,7 +249,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
thermal: thermal@e61f0000 {
|
||||
@ -248,7 +259,7 @@
|
||||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
@ -267,7 +278,7 @@
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
@ -287,7 +298,7 @@
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
@ -304,7 +315,7 @@
|
||||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
@ -333,7 +344,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -364,7 +375,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -393,7 +404,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -422,7 +433,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -434,7 +445,7 @@
|
||||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -446,7 +457,7 @@
|
||||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -458,7 +469,7 @@
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -470,7 +481,7 @@
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -482,7 +493,7 @@
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -494,7 +505,7 @@
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -508,7 +519,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -521,7 +532,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -534,7 +545,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
|
||||
dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -547,7 +558,7 @@
|
||||
clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
|
||||
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -558,7 +569,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
@ -571,7 +582,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
|
||||
dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
@ -590,7 +601,7 @@
|
||||
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
max-frequency = <195000000>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -602,7 +613,7 @@
|
||||
dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
|
||||
dma-names = "tx", "rx";
|
||||
max-frequency = <195000000>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -614,7 +625,7 @@
|
||||
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
max-frequency = <97500000>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -626,7 +637,7 @@
|
||||
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
max-frequency = <97500000>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -639,7 +650,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -652,7 +663,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -665,7 +676,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -678,7 +689,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -691,7 +702,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -704,7 +715,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -718,7 +729,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -732,7 +743,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -746,7 +757,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -760,7 +771,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -774,7 +785,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -783,7 +794,7 @@
|
||||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -796,7 +807,7 @@
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -807,7 +818,7 @@
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -816,7 +827,7 @@
|
||||
reg = <0 0xee500000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -828,7 +839,7 @@
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
@ -842,7 +853,7 @@
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
|
||||
clock-names = "usbhs";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
@ -860,7 +871,7 @@
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -869,7 +880,7 @@
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -878,7 +889,7 @@
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -887,7 +898,7 @@
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -896,7 +907,7 @@
|
||||
reg = <0 0xfe920000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-sru;
|
||||
renesas,#rpf = <5>;
|
||||
@ -909,7 +920,7 @@
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lut;
|
||||
renesas,has-sru;
|
||||
@ -923,7 +934,7 @@
|
||||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
@ -937,7 +948,7 @@
|
||||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
@ -992,7 +1003,7 @@
|
||||
clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1003,7 +1014,7 @@
|
||||
clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1012,7 +1023,7 @@
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_JPU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
@ -1447,6 +1458,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7790-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
qspi: spi@e6b10000 {
|
||||
compatible = "renesas,qspi-r8a7790", "renesas,qspi";
|
||||
reg = <0 0xe6b10000 0 0x2c>;
|
||||
@ -1454,7 +1471,7 @@
|
||||
clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -1468,7 +1485,7 @@
|
||||
clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1481,7 +1498,7 @@
|
||||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1494,7 +1511,7 @@
|
||||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
|
||||
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1507,7 +1524,7 @@
|
||||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
|
||||
dmas = <&dmac0 0x45>, <&dmac0 0x46>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1518,7 +1535,7 @@
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
phys = <&usb2 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
@ -1531,7 +1548,7 @@
|
||||
<0 0xee080000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0>;
|
||||
@ -1566,7 +1583,7 @@
|
||||
<0 0xee0a0000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <1 1>;
|
||||
@ -1584,7 +1601,7 @@
|
||||
compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
|
||||
device_type = "pci";
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
reg = <0 0xee0d0000 0 0xc00>,
|
||||
<0 0xee0c0000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -1637,7 +1654,7 @@
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1680,7 +1697,7 @@
|
||||
"mix.0", "mix.1",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
#include <dt-bindings/clock/r8a7791-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7791-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7791";
|
||||
@ -51,6 +52,7 @@
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
clocks = <&cpg_clocks R8A7791_CLK_Z>;
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
|
||||
/* kHz - uV - OPPs unknown yet */
|
||||
@ -67,6 +69,7 @@
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
clock-frequency = <1500000000>;
|
||||
power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
};
|
||||
@ -92,6 +95,7 @@
|
||||
|
||||
L2_CA15: cache-controller@0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7791_PD_CA15_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
@ -118,7 +122,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
@ -131,7 +135,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
@ -144,7 +148,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
@ -157,7 +161,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
@ -170,7 +174,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
@ -183,7 +187,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
@ -196,7 +200,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055800 {
|
||||
@ -209,7 +213,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
thermal: thermal@e61f0000 {
|
||||
@ -219,7 +223,7 @@
|
||||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
@ -238,7 +242,7 @@
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
@ -258,7 +262,7 @@
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
@ -281,7 +285,7 @@
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
@ -310,7 +314,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -341,7 +345,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -370,7 +374,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -399,7 +403,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -411,7 +415,7 @@
|
||||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -423,7 +427,7 @@
|
||||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -436,7 +440,7 @@
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -448,7 +452,7 @@
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -460,7 +464,7 @@
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -472,7 +476,7 @@
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -484,7 +488,7 @@
|
||||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -497,7 +501,7 @@
|
||||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -512,7 +516,7 @@
|
||||
clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
|
||||
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -525,7 +529,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -538,7 +542,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -554,7 +558,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
@ -567,7 +571,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
|
||||
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -578,7 +582,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
|
||||
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -589,7 +593,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
|
||||
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -602,7 +606,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -615,7 +619,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -628,7 +632,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -641,7 +645,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -654,7 +658,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -667,7 +671,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -680,7 +684,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -693,7 +697,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -706,7 +710,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -720,7 +724,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -734,7 +738,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -748,7 +752,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -762,7 +766,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -776,7 +780,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -790,7 +794,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -804,7 +808,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -818,7 +822,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -832,7 +836,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -841,7 +845,7 @@
|
||||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -854,7 +858,7 @@
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -865,7 +869,7 @@
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -874,7 +878,7 @@
|
||||
reg = <0 0xee500000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -886,7 +890,7 @@
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
@ -900,7 +904,7 @@
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
|
||||
clock-names = "usbhs";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
@ -918,7 +922,7 @@
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -927,7 +931,7 @@
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -936,7 +940,7 @@
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -945,7 +949,7 @@
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lut;
|
||||
renesas,has-sru;
|
||||
@ -959,7 +963,7 @@
|
||||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
@ -973,7 +977,7 @@
|
||||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
@ -1019,7 +1023,7 @@
|
||||
clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1030,7 +1034,7 @@
|
||||
clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1039,7 +1043,7 @@
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_JPU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
@ -1463,6 +1467,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7791-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
qspi: spi@e6b10000 {
|
||||
compatible = "renesas,qspi-r8a7791", "renesas,qspi";
|
||||
reg = <0 0xe6b10000 0 0x2c>;
|
||||
@ -1470,7 +1480,7 @@
|
||||
clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -1484,7 +1494,7 @@
|
||||
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1497,7 +1507,7 @@
|
||||
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1510,7 +1520,7 @@
|
||||
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
|
||||
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1521,7 +1531,7 @@
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
phys = <&usb2 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
@ -1534,7 +1544,7 @@
|
||||
<0 0xee080000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0>;
|
||||
@ -1569,7 +1579,7 @@
|
||||
<0 0xee0c0000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <1 1>;
|
||||
@ -1619,7 +1629,7 @@
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1722,7 +1732,7 @@
|
||||
"mix.0", "mix.1",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
#include <dt-bindings/clock/r8a7793-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7793-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7793";
|
||||
@ -43,6 +44,7 @@
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
clocks = <&cpg_clocks R8A7793_CLK_Z>;
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
|
||||
|
||||
/* kHz - uV - OPPs unknown yet */
|
||||
operating-points = <1500000 1000000>,
|
||||
@ -76,6 +78,7 @@
|
||||
|
||||
L2_CA15: cache-controller@0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7793_PD_CA15_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
@ -102,7 +105,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
@ -115,7 +118,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
@ -128,7 +131,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
@ -141,7 +144,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
@ -154,7 +157,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
@ -167,7 +170,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
@ -180,7 +183,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055800 {
|
||||
@ -193,7 +196,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
thermal: thermal@e61f0000 {
|
||||
@ -203,7 +206,7 @@
|
||||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
@ -222,7 +225,7 @@
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
@ -242,7 +245,7 @@
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
@ -265,7 +268,7 @@
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
@ -294,7 +297,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -325,7 +328,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -354,7 +357,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -383,7 +386,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -396,7 +399,7 @@
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -408,7 +411,7 @@
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -420,7 +423,7 @@
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -432,7 +435,7 @@
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -444,7 +447,7 @@
|
||||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -457,7 +460,7 @@
|
||||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -472,7 +475,7 @@
|
||||
clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
|
||||
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -485,7 +488,7 @@
|
||||
clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -498,7 +501,7 @@
|
||||
clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -514,7 +517,7 @@
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -525,7 +528,7 @@
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
|
||||
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -536,7 +539,7 @@
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
|
||||
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -549,7 +552,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -562,7 +565,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -575,7 +578,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -588,7 +591,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -601,7 +604,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -614,7 +617,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -627,7 +630,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -640,7 +643,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -653,7 +656,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -667,7 +670,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -681,7 +684,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -695,7 +698,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -709,7 +712,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -723,7 +726,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -737,7 +740,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -751,7 +754,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -765,7 +768,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -779,7 +782,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -788,7 +791,7 @@
|
||||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -802,7 +805,7 @@
|
||||
clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -846,7 +849,7 @@
|
||||
clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -857,7 +860,7 @@
|
||||
clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1221,6 +1224,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7793-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_sy0: mmu@e6280000 {
|
||||
compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6280000 0 0x1000>;
|
||||
@ -1316,7 +1325,7 @@
|
||||
"src.4", "src.3", "src.2", "src.1", "src.0",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#include <dt-bindings/clock/r8a7794-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7794-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7794";
|
||||
@ -42,6 +43,7 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
@ -50,12 +52,14 @@
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000000>;
|
||||
power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_CA7: cache-controller@1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7794_PD_CA7_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
@ -82,7 +86,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
@ -95,7 +99,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
@ -108,7 +112,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
@ -121,7 +125,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
@ -134,7 +138,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
@ -147,7 +151,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
@ -160,7 +164,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
cmt0: timer@ffca0000 {
|
||||
@ -170,7 +174,7 @@
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
@ -190,7 +194,7 @@
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
@ -221,7 +225,7 @@
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
@ -255,7 +259,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -286,7 +290,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -300,7 +304,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -313,7 +317,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -326,7 +330,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -339,7 +343,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -352,7 +356,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -365,7 +369,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -378,7 +382,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -391,7 +395,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -404,7 +408,7 @@
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -418,7 +422,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -432,7 +436,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -446,7 +450,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -460,7 +464,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -474,7 +478,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -488,7 +492,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -502,7 +506,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -516,7 +520,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -530,7 +534,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -539,7 +543,7 @@
|
||||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -552,7 +556,7 @@
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -564,7 +568,7 @@
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
@ -576,7 +580,7 @@
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
@ -588,7 +592,7 @@
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
@ -600,7 +604,7 @@
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
@ -612,7 +616,7 @@
|
||||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
@ -624,7 +628,7 @@
|
||||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
@ -638,7 +642,7 @@
|
||||
clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -651,7 +655,7 @@
|
||||
clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -664,7 +668,7 @@
|
||||
clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -674,7 +678,7 @@
|
||||
reg = <0 0xee100000 0 0x200>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -683,7 +687,7 @@
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -692,7 +696,7 @@
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -703,7 +707,7 @@
|
||||
clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -715,7 +719,7 @@
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -724,7 +728,7 @@
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -735,7 +739,7 @@
|
||||
<0 0xee080000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0>;
|
||||
@ -770,7 +774,7 @@
|
||||
<0 0xee0c0000 0 0x1100>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <1 1>;
|
||||
@ -803,7 +807,7 @@
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
@ -817,7 +821,7 @@
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
|
||||
clock-names = "usbhs";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
@ -865,7 +869,7 @@
|
||||
clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -876,7 +880,7 @@
|
||||
clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1213,6 +1217,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7794-sysc";
|
||||
reg = <0 0xe6180000 0 0x0200>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_sy0: mmu@e6280000 {
|
||||
compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6280000 0 0x1000>;
|
||||
|
||||
@ -38,11 +38,17 @@
|
||||
vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
|
||||
/* Mini PCIe */
|
||||
pci@1,0 {
|
||||
phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-4}>;
|
||||
phy-names = "pcie-0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Gigabit Ethernet */
|
||||
pci@2,0 {
|
||||
phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-2}>;
|
||||
phy-names = "pcie-0";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
@ -1677,6 +1683,9 @@
|
||||
sata@0,70020000 {
|
||||
status = "okay";
|
||||
|
||||
phys = <&{/padctl@0,7009f000/pads/sata/lanes/sata-0}>;
|
||||
phy-names = "sata-0";
|
||||
|
||||
hvdd-supply = <&vdd_3v3_lp0>;
|
||||
vddio-supply = <&vdd_1v05_run>;
|
||||
avdd-supply = <&vdd_1v05_run>;
|
||||
@ -1689,28 +1698,107 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
padctl@0,7009f000 {
|
||||
pinctrl-0 = <&padctl_default>;
|
||||
pinctrl-names = "default";
|
||||
usb@0,70090000 {
|
||||
phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
|
||||
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
|
||||
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
|
||||
<&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
|
||||
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
|
||||
|
||||
padctl_default: pinmux {
|
||||
usb3 {
|
||||
nvidia,lanes = "pcie-0", "pcie-1";
|
||||
nvidia,function = "usb3";
|
||||
nvidia,iddq = <0>;
|
||||
avddio-pex-supply = <&vdd_1v05_run>;
|
||||
dvddio-pex-supply = <&vdd_1v05_run>;
|
||||
avdd-usb-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-utmip-supply = <&vddio_1v8>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
|
||||
hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
|
||||
hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
padctl@0,7009f000 {
|
||||
status = "okay";
|
||||
|
||||
pads {
|
||||
usb2 {
|
||||
status = "okay";
|
||||
|
||||
lanes {
|
||||
usb2-0 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2-1 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2-2 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
nvidia,lanes = "pcie-2", "pcie-3",
|
||||
"pcie-4";
|
||||
nvidia,function = "pcie";
|
||||
nvidia,iddq = <0>;
|
||||
status = "okay";
|
||||
|
||||
lanes {
|
||||
pcie-0 {
|
||||
nvidia,function = "usb3-ss";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie-2 {
|
||||
nvidia,function = "pcie";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie-4 {
|
||||
nvidia,function = "pcie";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sata {
|
||||
nvidia,lanes = "sata-0";
|
||||
nvidia,function = "sata";
|
||||
nvidia,iddq = <0>;
|
||||
status = "okay";
|
||||
|
||||
lanes {
|
||||
sata-0 {
|
||||
nvidia,function = "sata";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
/* Micro A/B */
|
||||
usb2-0 {
|
||||
status = "okay";
|
||||
mode = "otg";
|
||||
};
|
||||
|
||||
/* Mini PCIe */
|
||||
usb2-1 {
|
||||
status = "okay";
|
||||
mode = "host";
|
||||
};
|
||||
|
||||
/* USB3 */
|
||||
usb2-2 {
|
||||
status = "okay";
|
||||
mode = "host";
|
||||
|
||||
vbus-supply = <&vdd_usb3_vbus>;
|
||||
};
|
||||
|
||||
usb3-0 {
|
||||
nvidia,usb2-companion = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -224,7 +224,7 @@
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo0 {
|
||||
avdd_1v05_run: ldo0 {
|
||||
regulator-name = "+1.05V_RUN_AVDD";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
@ -368,6 +368,99 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@0,70090000 {
|
||||
phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
|
||||
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
|
||||
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
|
||||
<&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
|
||||
<&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
|
||||
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
|
||||
|
||||
avddio-pex-supply = <&vdd_1v05_run>;
|
||||
dvddio-pex-supply = <&vdd_1v05_run>;
|
||||
avdd-usb-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-utmip-supply = <&vddio_1v8>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
|
||||
hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
|
||||
hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
padctl@0,7009f000 {
|
||||
status = "okay";
|
||||
|
||||
pads {
|
||||
usb2 {
|
||||
status = "okay";
|
||||
|
||||
lanes {
|
||||
usb2-0 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2-1 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2-2 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
status = "okay";
|
||||
|
||||
lanes {
|
||||
pcie-0 {
|
||||
nvidia,function = "usb3-ss";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie-1 {
|
||||
nvidia,function = "usb3-ss";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
usb2-0 {
|
||||
vbus-supply = <&vdd_usb1_vbus>;
|
||||
status = "okay";
|
||||
mode = "otg";
|
||||
};
|
||||
|
||||
usb2-1 {
|
||||
vbus-supply = <&vdd_run_cam>;
|
||||
status = "okay";
|
||||
mode = "host";
|
||||
};
|
||||
|
||||
usb2-2 {
|
||||
vbus-supply = <&vdd_usb3_vbus>;
|
||||
status = "okay";
|
||||
mode = "host";
|
||||
};
|
||||
|
||||
usb3-0 {
|
||||
nvidia,usb2-companion = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3-1 {
|
||||
nvidia,usb2-companion = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci0_pwrseq: sdhci0_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
|
||||
@ -414,33 +507,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
usb@0,7d000000 { /* Rear external USB port. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@0,7d000000 {
|
||||
status = "okay";
|
||||
vbus-supply = <&vdd_usb1_vbus>;
|
||||
};
|
||||
|
||||
usb@0,7d004000 { /* Internal webcam. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@0,7d004000 {
|
||||
status = "okay";
|
||||
vbus-supply = <&vdd_run_cam>;
|
||||
};
|
||||
|
||||
usb@0,7d008000 { /* Left external USB port. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@0,7d008000 {
|
||||
status = "okay";
|
||||
vbus-supply = <&vdd_usb3_vbus>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
|
||||
|
||||
@ -757,7 +757,7 @@
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo0 {
|
||||
avdd_1v05_run: ldo0 {
|
||||
regulator-name = "+1.05V_RUN_AVDD";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
@ -899,6 +899,105 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@0,70090000 {
|
||||
phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
|
||||
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
|
||||
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
|
||||
<&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
|
||||
<&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
|
||||
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
|
||||
|
||||
avddio-pex-supply = <&vdd_1v05_run>;
|
||||
dvddio-pex-supply = <&vdd_1v05_run>;
|
||||
avdd-usb-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-utmip-supply = <&vddio_1v8>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
|
||||
hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
|
||||
hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
padctl@0,7009f000 {
|
||||
pads {
|
||||
usb2 {
|
||||
status = "okay";
|
||||
|
||||
lanes {
|
||||
usb2-0 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2-1 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2-2 {
|
||||
nvidia,function = "xusb";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
status = "okay";
|
||||
|
||||
lanes {
|
||||
pcie-0 {
|
||||
nvidia,function = "usb3-ss";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie-1 {
|
||||
nvidia,function = "usb3-ss";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie-1 {
|
||||
nvidia,function = "usb3-ss";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
usb2-0 {
|
||||
status = "okay";
|
||||
mode = "otg";
|
||||
|
||||
vbus-supply = <&vdd_usb1_vbus>;
|
||||
};
|
||||
|
||||
usb2-1 {
|
||||
status = "okay";
|
||||
mode = "host";
|
||||
|
||||
vbus-supply = <&vdd_run_cam>;
|
||||
};
|
||||
|
||||
usb2-2 {
|
||||
status = "okay";
|
||||
mode = "host";
|
||||
|
||||
vbus-supply = <&vdd_usb3_vbus>;
|
||||
};
|
||||
|
||||
usb3-0 {
|
||||
nvidia,usb2-companion = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3-1 {
|
||||
nvidia,usb2-companion = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@0,700b0400 {
|
||||
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
|
||||
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
|
||||
|
||||
@ -2,7 +2,6 @@
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/memory/tegra124-mc.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset/tegra124-car.h>
|
||||
#include <dt-bindings/thermal/tegra124-soctherm.h>
|
||||
@ -51,9 +50,6 @@
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
status = "disabled";
|
||||
|
||||
phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
|
||||
phy-names = "pcie";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
||||
@ -622,8 +618,6 @@
|
||||
<&tegra_car 123>,
|
||||
<&tegra_car 129>;
|
||||
reset-names = "sata", "sata-oob", "sata-cold";
|
||||
phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -642,13 +636,172 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@0,70090000 {
|
||||
compatible = "nvidia,tegra124-xusb";
|
||||
reg = <0x0 0x70090000 0x0 0x8000>,
|
||||
<0x0 0x70098000 0x0 0x1000>,
|
||||
<0x0 0x70099000 0x0 0x1000>;
|
||||
reg-names = "hcd", "fpci", "ipfs";
|
||||
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
|
||||
<&tegra_car TEGRA124_CLK_CLK_M>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_E>;
|
||||
clock-names = "xusb_host", "xusb_host_src",
|
||||
"xusb_falcon_src", "xusb_ss",
|
||||
"xusb_ss_div2", "xusb_ss_src",
|
||||
"xusb_hs_src", "xusb_fs_src",
|
||||
"pll_u_480m", "clk_m", "pll_e";
|
||||
resets = <&tegra_car 89>, <&tegra_car 156>,
|
||||
<&tegra_car 143>;
|
||||
reset-names = "xusb_host", "xusb_ss", "xusb_src";
|
||||
|
||||
nvidia,xusb-padctl = <&padctl>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
padctl: padctl@0,7009f000 {
|
||||
compatible = "nvidia,tegra124-xusb-padctl";
|
||||
reg = <0x0 0x7009f000 0x0 0x1000>;
|
||||
resets = <&tegra_car 142>;
|
||||
reset-names = "padctl";
|
||||
|
||||
#phy-cells = <1>;
|
||||
pads {
|
||||
usb2 {
|
||||
status = "disabled";
|
||||
|
||||
lanes {
|
||||
usb2-0 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb2-1 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb2-2 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ulpi {
|
||||
status = "disabled";
|
||||
|
||||
lanes {
|
||||
ulpi-0 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hsic {
|
||||
status = "disabled";
|
||||
|
||||
lanes {
|
||||
hsic-0 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
hsic-1 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
status = "disabled";
|
||||
|
||||
lanes {
|
||||
pcie-0 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
pcie-1 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
pcie-2 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
pcie-3 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
pcie-4 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sata {
|
||||
status = "disabled";
|
||||
|
||||
lanes {
|
||||
sata-0 {
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
usb2-0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2-1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2-2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ulpi-0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsic-0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsic-1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3-0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3-1 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@0,700b0000 {
|
||||
|
||||
@ -50,6 +50,11 @@
|
||||
clock-frequency = <16000000>;
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "edt,et057090dhu";
|
||||
backlight = <&bl>;
|
||||
};
|
||||
|
||||
reg_3v3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3.3V";
|
||||
@ -83,6 +88,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcu0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dcu0_1>;
|
||||
fsl,panel = <&panel>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dspi1 {
|
||||
status = "okay";
|
||||
|
||||
@ -134,6 +146,10 @@
|
||||
vin-supply = <®_3v3>;
|
||||
};
|
||||
|
||||
&tcon0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -222,6 +222,39 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_dcu0_1: dcu0grp_1 {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTE0__DCU0_HSYNC 0x1902
|
||||
VF610_PAD_PTE1__DCU0_VSYNC 0x1902
|
||||
VF610_PAD_PTE2__DCU0_PCLK 0x1902
|
||||
VF610_PAD_PTE4__DCU0_DE 0x1902
|
||||
VF610_PAD_PTE5__DCU0_R0 0x1902
|
||||
VF610_PAD_PTE6__DCU0_R1 0x1902
|
||||
VF610_PAD_PTE7__DCU0_R2 0x1902
|
||||
VF610_PAD_PTE8__DCU0_R3 0x1902
|
||||
VF610_PAD_PTE9__DCU0_R4 0x1902
|
||||
VF610_PAD_PTE10__DCU0_R5 0x1902
|
||||
VF610_PAD_PTE11__DCU0_R6 0x1902
|
||||
VF610_PAD_PTE12__DCU0_R7 0x1902
|
||||
VF610_PAD_PTE13__DCU0_G0 0x1902
|
||||
VF610_PAD_PTE14__DCU0_G1 0x1902
|
||||
VF610_PAD_PTE15__DCU0_G2 0x1902
|
||||
VF610_PAD_PTE16__DCU0_G3 0x1902
|
||||
VF610_PAD_PTE17__DCU0_G4 0x1902
|
||||
VF610_PAD_PTE18__DCU0_G5 0x1902
|
||||
VF610_PAD_PTE19__DCU0_G6 0x1902
|
||||
VF610_PAD_PTE20__DCU0_G7 0x1902
|
||||
VF610_PAD_PTE21__DCU0_B0 0x1902
|
||||
VF610_PAD_PTE22__DCU0_B1 0x1902
|
||||
VF610_PAD_PTE23__DCU0_B2 0x1902
|
||||
VF610_PAD_PTE24__DCU0_B3 0x1902
|
||||
VF610_PAD_PTE25__DCU0_B4 0x1902
|
||||
VF610_PAD_PTE26__DCU0_B5 0x1902
|
||||
VF610_PAD_PTE27__DCU0_B6 0x1902
|
||||
VF610_PAD_PTE28__DCU0_B7 0x1902
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_dspi1: dspi1grp {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTD5__DSPI1_CS0 0x33e2
|
||||
|
||||
@ -311,6 +311,14 @@
|
||||
<20000000>;
|
||||
};
|
||||
|
||||
tcon0: timing-controller@4003d000 {
|
||||
compatible = "fsl,vf610-tcon";
|
||||
reg = <0x4003d000 0x1000>;
|
||||
clocks = <&clks VF610_CLK_TCON0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdoga5: wdog@4003e000 {
|
||||
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x4003e000 0x1000>;
|
||||
@ -416,6 +424,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcu0: dcu@40058000 {
|
||||
compatible = "fsl,vf610-dcu";
|
||||
reg = <0x40058000 0x1200>;
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks VF610_CLK_DCU0>,
|
||||
<&clks VF610_CLK_DCU0_DIV>;
|
||||
clock-names = "dcu", "pix";
|
||||
fsl,tcon = <&tcon0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@40066000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7795-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7795";
|
||||
@ -39,6 +40,7 @@
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
@ -47,6 +49,7 @@
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
@ -54,6 +57,7 @@
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x2>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
@ -61,6 +65,7 @@
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x3>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
@ -68,12 +73,14 @@
|
||||
|
||||
L2_CA57: cache-controller@0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller@1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7795_PD_CA53_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
@ -168,7 +175,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 912>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
@ -182,7 +189,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 911>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
@ -196,7 +203,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 910>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
@ -210,7 +217,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 909>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
@ -224,7 +231,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 908>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
@ -238,7 +245,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 907>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
@ -252,7 +259,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 906>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055800 {
|
||||
@ -266,7 +273,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 905>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
pmu_a57 {
|
||||
@ -302,6 +309,12 @@
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a7795-sysc";
|
||||
reg = <0 0xe6180000 0 0x0400>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
reg = <0 0xec700000 0 0x10000>;
|
||||
@ -329,7 +342,7 @@
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 502>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
@ -361,7 +374,7 @@
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 501>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
@ -383,7 +396,7 @@
|
||||
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
@ -414,7 +427,7 @@
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
@ -447,7 +460,7 @@
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
@ -480,7 +493,7 @@
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
@ -522,7 +535,7 @@
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
phy-mode = "rgmii-id";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -539,7 +552,7 @@
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -554,7 +567,7 @@
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -570,7 +583,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x31>, <&dmac1 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -586,7 +599,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x33>, <&dmac1 0x32>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -602,7 +615,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x35>, <&dmac1 0x34>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -618,7 +631,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x37>, <&dmac0 0x36>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -634,7 +647,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x38>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -649,7 +662,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x51>, <&dmac1 0x50>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -664,7 +677,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x53>, <&dmac1 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -679,7 +692,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -694,7 +707,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -709,7 +722,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -724,7 +737,7 @@
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -735,7 +748,7 @@
|
||||
reg = <0 0xe6500000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 931>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -747,7 +760,7 @@
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 930>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -759,7 +772,7 @@
|
||||
reg = <0 0xe6510000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 929>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -771,7 +784,7 @@
|
||||
reg = <0 0xe66d0000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 928>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -783,7 +796,7 @@
|
||||
reg = <0 0xe66d8000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 927>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -795,7 +808,7 @@
|
||||
reg = <0 0xe66e0000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 919>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -807,7 +820,7 @@
|
||||
reg = <0 0xe66e8000 0 0x40>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 918>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -857,7 +870,7 @@
|
||||
"src.1", "src.0",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
rcar_sound,dvc {
|
||||
@ -991,7 +1004,7 @@
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 328>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1000,7 +1013,7 @@
|
||||
reg = <0 0xee040000 0 0xc00>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 327>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1012,7 +1025,7 @@
|
||||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 330>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -1025,7 +1038,7 @@
|
||||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 331>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -1035,7 +1048,7 @@
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1044,7 +1057,7 @@
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1053,7 +1066,7 @@
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1063,7 +1076,7 @@
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1073,7 +1086,7 @@
|
||||
reg = <0 0xee080200 0 0x700>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1082,7 +1095,7 @@
|
||||
compatible = "renesas,usb2-phy-r8a7795";
|
||||
reg = <0 0xee0a0200 0 0x700>;
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1091,7 +1104,7 @@
|
||||
compatible = "renesas,usb2-phy-r8a7795";
|
||||
reg = <0 0xee0c0200 0 0x700>;
|
||||
clocks = <&cpg CPG_MOD 701>;
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1103,7 +1116,7 @@
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1114,7 +1127,7 @@
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1125,7 +1138,7 @@
|
||||
clocks = <&cpg CPG_MOD 701>;
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1136,7 +1149,7 @@
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1147,7 +1160,7 @@
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1158,7 +1171,7 @@
|
||||
clocks = <&cpg CPG_MOD 701>;
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
pciec0: pcie@fe000000 {
|
||||
@ -1182,7 +1195,7 @@
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1207,7 +1220,7 @@
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&cpg>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user