STM32 DT for v6.8, round 1

Highlights: ---------- - MCU: - Add SPI support on STM32F746. - Better describe vcc_3v3 for SD and DSI on stm32f469-disco. - MPU: - STM32MP13: - Add DCMIPP (Digital Camera Memory Interface Piwel Processor) on STM32MP135. - STMP32MP15: - Change "phys" affectation from board to Soc dtsi file for USB host as it is hard linked to the port 0 of usbphyc. - Fix SCMI and No-SCMI compatible in boards. - STM32MP25: - Add BSEC support to read the device part number OTP and the package data register OTP. -----BEGIN PGP SIGNATURE----- iQJRBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmV8IvwdHGFsZXhhbmRy ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIXczA/9FkqesUrCaQtNTvXu CAK4drh2MalVcE5puzRp1ibT1WgylMezuuKAdbOu24/Z/RkleoWZn5ytLOehT3JC s9d+77p/HtF5TuVWBPeyIeyDjwYxu9YWTrYzaWa4dMtW6bRHqGKfIZBVlUZgqr6V GfJBcVmKW1Od0KhS5gRQDh3aYa/Hgg1FK77yd+sTZhcGObkN1zUWV8FfRZXz1aGe Cmp06y/VAfXFEUsUUNk+gUFWHMeU/n6rcV1oJRYpqcNq7mCRxQ8PZpSWmZE7ieCH I8C4FJ5yBmDNESNyXaIdYVI9H7opscGooq4NWoIcZZdgUB4Y1x5XCQkgd2MUiF85 sGm1SCPpBd5BvE+G1o0h9Le3J6etls8Pq5clt4UcS4cs8QXPLUNxvbcQv1vJ3CCe UNLrwJJvISD5u64caxFKoxht556+j9U/w8P1JmU/SawugPWxnJuOcGlpvOjeaG9s ee2q7d8TfJveUbnMFlt1lZ0Q2Vt7jYjvUY94kVUshqOJB6PlI60WIJ2Py4mN6F6e 8lExh4HCbP4NLajYfiYWuHrxLXFICgNAVR7cbUgrC1eKWl/9Dgw6CvFfcCzWa4PP uG46MxakmDUXiL6MUhHpa0eVq8hQAHCjZdhVGzHR3QzBVs+UeXwSw8i3aYb3Vbx7 fLnVmZQpYfI1E8STqvPPHRcbwYM= =9ILX -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWEZUEACgkQYKtH/8kJ Uid9lhAAxSSBBCIrTKrKqgIVKcAlnvnIqHCnCMSAWm3jQwznHRjUyWFz1tt9pbiO ibR4nWjip2l9MHNojqdVLKtwWR6uOTVk5PTsCa5XGe90ZUZnxfyv7jocATndrGHS NUxXd9Wyaa5Fg0avj5ph3QYyfN0E9CbGmgpBFjZN7NUTzN39wjeaDWtlsdsCFmMi /Q0TQv3aT8FanYT3WapoDBMri9GyHJRC7d+MOW0lBRYVncCa4ziIiQDM6oG6bYT7 yHtHQp+grO8rfAAgdm8NHX1cOFF0xYE6XoN8iPETl0XLveBURo8BrIh4l13+H1au Jrpjtdbfa6C40xpDakrErBj5ZM+9kcMGEn9WYjDBYShjnh3+RhEt1aGrpni2iylo eK+OtJd/VFAybrKFeUzrOwNumLP0HHGTXCSHSCPi1XbXBlS4df+z9oO2e0bOHrSI iSZlGxCA1kUnJinRlXVPqyvDrfexeqz/httAbs/pzsOan5GkX+jr1oM+G1XaSjIT dKytUWEBL4iS7capoCgLTJjoMaIJulffRZMUhCb+abNB8AXItREQ1PEk2R0rIgUL n0zly2zRV8uwbAoKU51Nd3gDZ6REJNApkzsSNDR49Vrz+ZCM0cSrlpxlbQw0vH8M tvhnS2vkRdmjAc81T5BuPRxKPTSYVqPrB08UN9TG47Sudbmoa3E= =P9+p -----END PGP SIGNATURE----- Merge tag 'stm32-dt-for-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.8, round 1 Highlights: ---------- - MCU: - Add SPI support on STM32F746. - Better describe vcc_3v3 for SD and DSI on stm32f469-disco. - MPU: - STM32MP13: - Add DCMIPP (Digital Camera Memory Interface Piwel Processor) on STM32MP135. - STMP32MP15: - Change "phys" affectation from board to Soc dtsi file for USB host as it is hard linked to the port 0 of usbphyc. - Fix SCMI and No-SCMI compatible in boards. - STM32MP25: - Add BSEC support to read the device part number OTP and the package data register OTP. * tag 'stm32-dt-for-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: add dcmipp support to stm32mp135 arm64: dts: st: add bsec support to stm32mp25 ARM: dts: stm32: Consolidate usbh_[eo]hci phy properties on stm32mp15 ARM: dts: stm32: don't mix SCMI and non-SCMI board compatibles dt-bindings: arm: stm32: don't mix SCMI and non-SCMI board compatibles ARM: dts: stm32: minor whitespace cleanup around '=' ARM: dts: stm32: add SPI support on STM32F746 ARM: dts: stm32: add STM32F746 syscfg clock ARM: dts: stm32: use the same 3v3 for SD and DSI nodes on stm32f469-disco Link: https://lore.kernel.org/r/9363227b-1c44-4a20-b245-efbbbf9ab1dd@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-12-21 16:17:22 +00:00 · 2023-12-21 16:17:22 +00:00 · 084d415d21
commit 084d415d21
parent e0a220a3ad 2de1bb183a
24 changed files with 107 additions and 64 deletions
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@ -82,29 +82,19 @@ properties:
              - shiratech,stm32mp157a-iot-box # IoT Box
              - shiratech,stm32mp157a-stinger96 # Stinger96
              - st,stm32mp157c-ed1
+              - st,stm32mp157c-ed1-scmi
              - st,stm32mp157a-dk1
+              - st,stm32mp157a-dk1-scmi
              - st,stm32mp157c-dk2
+              - st,stm32mp157c-dk2-scmi
          - const: st,stm32mp157

-      - items:
-          - const: st,stm32mp157a-dk1-scmi
-          - const: st,stm32mp157a-dk1
-          - const: st,stm32mp157
-      - items:
-          - const: st,stm32mp157c-dk2-scmi
-          - const: st,stm32mp157c-dk2
-          - const: st,stm32mp157
-      - items:
-          - const: st,stm32mp157c-ed1-scmi
-          - const: st,stm32mp157c-ed1
-          - const: st,stm32mp157
      - items:
          - const: st,stm32mp157c-ev1
          - const: st,stm32mp157c-ed1
          - const: st,stm32mp157
      - items:
          - const: st,stm32mp157c-ev1-scmi
-          - const: st,stm32mp157c-ev1
          - const: st,stm32mp157c-ed1
          - const: st,stm32mp157

--- a/arch/arm/boot/dts/st/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f469-disco.dts
@ -69,16 +69,9 @@
 		serial0 = &usart3;
 	};

-	mmc_vcard: mmc_vcard {
+	vcc_3v3: vcc-3v3 {
 		compatible = "regulator-fixed";
-		regulator-name = "mmc_vcard";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	vdd_dsi: vdd-dsi {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_dsi";
+		regulator-name = "vcc_3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
@ -164,7 +157,7 @@
 		compatible = "orisetech,otm8009a";
 		reg = <0>; /* dsi virtual channel (0..3) */
 		reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
-		power-supply = <&vdd_dsi>;
+		power-supply = <&vcc_3v3>;
 		status = "okay";

 		port {
@ -219,7 +212,7 @@

 &sdio {
 	status = "okay";
-	vmmc-supply = <&mmc_vcard>;
+	vmmc-supply = <&vcc_3v3>;
 	cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
 	broken-cd;
 	pinctrl-names = "default", "opendrain";
--- a/arch/arm/boot/dts/st/stm32f746.dtsi
+++ b/arch/arm/boot/dts/st/stm32f746.dtsi
@ -274,6 +274,26 @@
 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
 		};

+		spi2: spi@40003800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f7-spi";
+			reg = <0x40003800 0x400>;
+			interrupts = <36>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
+			status = "disabled";
+		};
+
+		spi3: spi@40003c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f7-spi";
+			reg = <0x40003c00 0x400>;
+			interrupts = <51>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
+			status = "disabled";
+		};
+
 		usart2: serial@40004400 {
 			compatible = "st,stm32f7-uart";
 			reg = <0x40004400 0x400>;
@ -491,9 +511,30 @@
 			status = "disabled";
 		};

+		spi1: spi@40013000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f7-spi";
+			reg = <0x40013000 0x400>;
+			interrupts = <35>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
+			status = "disabled";
+		};
+
+		spi4: spi@40013400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f7-spi";
+			reg = <0x40013400 0x400>;
+			interrupts = <84>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
+			status = "disabled";
+		};
+
 		syscfg: syscon@40013800 {
 			compatible = "st,stm32-syscfg", "syscon";
 			reg = <0x40013800 0x400>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
 		};

 		exti: interrupt-controller@40013c00 {
@ -554,6 +595,26 @@
 			};
 		};

+		spi5: spi@40015000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f7-spi";
+			reg = <0x40015000 0x400>;
+			interrupts = <85>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
+			status = "disabled";
+		};
+
+		spi6: spi@40015400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f7-spi";
+			reg = <0x40015400 0x400>;
+			interrupts = <86>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
+			status = "disabled";
+		};
+
 		ltdc: display-controller@40016800 {
 			compatible = "st,stm32-ltdc";
 			reg = <0x40016800 0x200>;
--- a/arch/arm/boot/dts/st/stm32mp135.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp135.dtsi
@ -8,5 +8,16 @@

 / {
 	soc {
+		dcmipp: dcmipp@5a000000 {
+			compatible = "st,stm32mp13-dcmipp";
+			reg = <0x5a000000 0x400>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rcc DCMIPP_R>;
+			clocks = <&rcc DCMIPP_K>;
+			status = "disabled";
+
+			port {
+			};
+		};
 	};
 };
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@ -1521,6 +1521,8 @@
 			clocks = <&usbphyc>, <&rcc USBH>;
 			resets = <&rcc USBH_R>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usbphyc_port0>;
+			phy-names = "usb";
 			status = "disabled";
 		};

@ -1531,6 +1533,8 @@
 			resets = <&rcc USBH_R>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			companion = <&usbh_ohci>;
+			phys = <&usbphyc_port0>;
+			phy-names = "usb";
 			status = "disabled";
 		};

--- a/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi
@ -206,8 +206,6 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
@ -11,7 +11,7 @@

 / {
 	model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
-	compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
+	compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157";

 	reserved-memory {
 		optee@de000000 {
@ -59,7 +59,7 @@
 	/delete-property/ st,syscfg-holdboot;
 	resets = <&scmi_reset RST_SCMI_MCU>,
 		 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
-	reset-names =  "mcu_rst", "hold_boot";
+	reset-names = "mcu_rst", "hold_boot";
 };

 &rcc {
--- a/arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi
@ -313,8 +313,6 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
@ -11,7 +11,7 @@

 / {
 	model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
-	compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
+	compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157";

 	reserved-memory {
 		optee@de000000 {
@ -65,7 +65,7 @@
 	/delete-property/ st,syscfg-holdboot;
 	resets = <&scmi_reset RST_SCMI_MCU>,
 		 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
-	reset-names =  "mcu_rst", "hold_boot";
+	reset-names = "mcu_rst", "hold_boot";
 };

 &rcc {
--- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
@ -11,7 +11,7 @@

 / {
 	model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
-	compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
+	compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157";

 	reserved-memory {
 		optee@fe000000 {
@ -64,7 +64,7 @@
 	/delete-property/ st,syscfg-holdboot;
 	resets = <&scmi_reset RST_SCMI_MCU>,
 		 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
-	reset-names =  "mcu_rst", "hold_boot";
+	reset-names = "mcu_rst", "hold_boot";
 };

 &rcc {
--- a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi
@ -500,14 +500,10 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

 &usbh_ohci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
@ -11,8 +11,7 @@

 / {
 	model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
-	compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
-		     "st,stm32mp157";
+	compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";

 	reserved-memory {
 		optee@fe000000 {
@ -70,7 +69,7 @@
 	/delete-property/ st,syscfg-holdboot;
 	resets = <&scmi_reset RST_SCMI_MCU>,
 		 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
-	reset-names =  "mcu_rst", "hold_boot";
+	reset-names = "mcu_rst", "hold_boot";
 };

 &rcc {
--- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
@ -362,7 +362,6 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 	#address-cells = <1>;
 	#size-cells = <0>;
--- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts
@ -197,14 +197,10 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

 &usbh_ohci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi
@ -547,14 +547,10 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

 &usbh_ohci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi
@ -567,9 +567,6 @@ baseboard_eeprom: &sip_eeprom {
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
-
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi
@ -152,7 +152,6 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
@ -305,7 +305,6 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi
@ -119,12 +119,10 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 };

 &usbh_ohci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi
@ -489,8 +489,6 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi
@ -312,12 +312,10 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 };

 &usbh_ohci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi
@ -168,12 +168,10 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 };

 &usbh_ohci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 };

--- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
@ -680,7 +680,6 @@
 };

 &usbh_ehci {
-	phys = <&usbphyc_port0>;
 	status = "okay";
 	#address-cells = <1>;
 	#size-cells = <0>;
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@ -140,6 +140,22 @@
 			};
 		};

+		bsec: efuse@44000000 {
+			compatible = "st,stm32mp25-bsec";
+			reg = <0x44000000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			part_number_otp@24 {
+				reg = <0x24 0x4>;
+			};
+
+			package_otp@1e8 {
+				reg = <0x1e8 0x1>;
+				bits = <0 3>;
+			};
+		};
+
 		syscfg: syscon@44230000 {
 			compatible = "st,stm32mp25-syscfg", "syscon";
 			reg = <0x44230000 0x10000>;