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OMAPDSS: HDMI: fix regsd write

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HDMI PLL's REGSD field is only set by the driver if the PLL's output
clock is over 1GHz. This is clearly an error, as REGSD should be set
always.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen 2014-09-15 15:50:01 +03:00
parent 88e3c76a8a
commit 0856eba75c
1 changed files with 4 additions and 5 deletions
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9
drivers/video/fbdev/omap2/dss/hdmi_pll.c
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@ -124,16 +124,15 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll)
r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
if (fmt->dcofreq) {
/* divider programming for frequency beyond 1000Mhz */
REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
if (fmt->dcofreq)
r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
} else {
else
r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
}
hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
r = FLD_MOD(r, fmt->regm2, 24, 18);
r = FLD_MOD(r, fmt->regmf, 17, 0);