- ioremap: mask out the bits which are not part of the physical address
*after* the size computation is done to prevent and hypothetical ioremap failures - Change the MSR save/restore functionality during suspend to rely on flags denoting that the related MSRs are actually supported vs reading them and assuming they are (an Atom one allows reading but not writing, thus breaking this scheme at resume time.) - prevent IV reuse in the AES-GCM communication scheme between SNP guests and the AMD secure processor -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmODRegACgkQEsHwGGHe VUr3Fw//dZr1BpLA2PoHBWRKw+tJA7NZ5QgYPwYgpZysI3LiSd3wHiYx12AMYl/1 rvG0ELCwR5MUt3s0owqm4XlzmNbFG/ISsaR3d2mUlqgPrztYKZTHUP14LjzbCgdx 53FSWqxeK5+NkQcUXF/GsR5flbHHG40wM9PK6UDm+xZPvoTKkBlCNcId+5yMtq0J ZvemhZ9rMGoA6bRWvRIhzKdzz9+MRcKMMjcAULNtngIlE/CfdkkIGios0JmPshSB h10/CmYRz38U90sqFXF/9DJPo6oFB9DOxIZmyb6cTmJCasSwfuU4uEtTiIuNMw0Y zflc1vNnOkpdPvn8nXWwo/OWdjg9oh/TJOzthjyxjlVs4DYjBRnXykdO6lUQWjVI XWE4sP8lt2J4wsiURzcaroqfqpQu1Y/hlh/io5xp8vE2qZaOjgADYV1ZHgB/Y20I Opm4ICsMYN4ZQqejKfhq/Fu15Y6qqGIl0pNBjOJK0rdaDPthFd4+UEJGvd57RdNl RCWC8EvsI8LGWDkGJeR1sytVJT7adWsfy6bYg98BQ2rId4oj89kZYZNqJROf/hv5 aU7i9AMh8WodZTGh2bfwq+dLvACccc2rqbYh0Q7Uwm3IjaPTWiPHanqsvSo6+GrO aO4IUoUidXheVPJu3qfiNTJ4GtTUnqDiatpbfA+Do+Rva2wWBFw= =xYpH -----END PGP SIGNATURE----- Merge tag 'x86_urgent_for_v6.1_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Borislav Petkov: - ioremap: mask out the bits which are not part of the physical address *after* the size computation is done to prevent any hypothetical ioremap failures - Change the MSR save/restore functionality during suspend to rely on flags denoting that the related MSRs are actually supported vs reading them and assuming they are (an Atom one allows reading but not writing, thus breaking this scheme at resume time) - prevent IV reuse in the AES-GCM communication scheme between SNP guests and the AMD secure processor * tag 'x86_urgent_for_v6.1_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/ioremap: Fix page aligned size calculation in __ioremap_caller() x86/pm: Add enumeration check before spec MSRs save/restore setup x86/tsx: Add a feature bit for TSX control MSR support virt/sev-guest: Prevent IV reuse in the SNP guest driver
This commit is contained in:
Linus Torvalds
commit
08b0644126
@ -305,6 +305,9 @@
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#define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */
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#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
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#define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
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#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
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@ -58,24 +58,6 @@ static void tsx_enable(void)
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wrmsrl(MSR_IA32_TSX_CTRL, tsx);
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}
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static bool tsx_ctrl_is_supported(void)
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{
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u64 ia32_cap = x86_read_arch_cap_msr();
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/*
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* TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
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* MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
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*
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* TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
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* microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
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* bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
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* MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
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* tsx= cmdline requests will do nothing on CPUs without
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* MSR_IA32_TSX_CTRL support.
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*/
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return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
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}
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static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
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{
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if (boot_cpu_has_bug(X86_BUG_TAA))
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@ -135,7 +117,7 @@ static void tsx_clear_cpuid(void)
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rdmsrl(MSR_TSX_FORCE_ABORT, msr);
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msr |= MSR_TFA_TSX_CPUID_CLEAR;
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wrmsrl(MSR_TSX_FORCE_ABORT, msr);
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} else if (tsx_ctrl_is_supported()) {
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} else if (cpu_feature_enabled(X86_FEATURE_MSR_TSX_CTRL)) {
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rdmsrl(MSR_IA32_TSX_CTRL, msr);
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msr |= TSX_CTRL_CPUID_CLEAR;
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wrmsrl(MSR_IA32_TSX_CTRL, msr);
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@ -158,7 +140,8 @@ static void tsx_dev_mode_disable(void)
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u64 mcu_opt_ctrl;
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/* Check if RTM_ALLOW exists */
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if (!boot_cpu_has_bug(X86_BUG_TAA) || !tsx_ctrl_is_supported() ||
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if (!boot_cpu_has_bug(X86_BUG_TAA) ||
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!cpu_feature_enabled(X86_FEATURE_MSR_TSX_CTRL) ||
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!cpu_feature_enabled(X86_FEATURE_SRBDS_CTRL))
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return;
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@ -191,7 +174,20 @@ void __init tsx_init(void)
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return;
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}
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if (!tsx_ctrl_is_supported()) {
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/*
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* TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
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* MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
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*
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* TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
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* microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
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* bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
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* MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
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* tsx= cmdline requests will do nothing on CPUs without
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* MSR_IA32_TSX_CTRL support.
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*/
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if (x86_read_arch_cap_msr() & ARCH_CAP_TSX_CTRL_MSR) {
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setup_force_cpu_cap(X86_FEATURE_MSR_TSX_CTRL);
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} else {
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tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;
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return;
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}
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@ -217,9 +217,15 @@ __ioremap_caller(resource_size_t phys_addr, unsigned long size,
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* Mappings have to be page-aligned
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*/
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offset = phys_addr & ~PAGE_MASK;
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phys_addr &= PHYSICAL_PAGE_MASK;
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phys_addr &= PAGE_MASK;
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size = PAGE_ALIGN(last_addr+1) - phys_addr;
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/*
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* Mask out any bits not part of the actual physical
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* address, like memory encryption bits.
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*/
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phys_addr &= PHYSICAL_PAGE_MASK;
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retval = memtype_reserve(phys_addr, (u64)phys_addr + size,
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pcm, &new_pcm);
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if (retval) {
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@ -513,16 +513,23 @@ static int pm_cpu_check(const struct x86_cpu_id *c)
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static void pm_save_spec_msr(void)
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{
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u32 spec_msr_id[] = {
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MSR_IA32_SPEC_CTRL,
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MSR_IA32_TSX_CTRL,
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MSR_TSX_FORCE_ABORT,
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MSR_IA32_MCU_OPT_CTRL,
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MSR_AMD64_LS_CFG,
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MSR_AMD64_DE_CFG,
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struct msr_enumeration {
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u32 msr_no;
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u32 feature;
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} msr_enum[] = {
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{ MSR_IA32_SPEC_CTRL, X86_FEATURE_MSR_SPEC_CTRL },
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{ MSR_IA32_TSX_CTRL, X86_FEATURE_MSR_TSX_CTRL },
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{ MSR_TSX_FORCE_ABORT, X86_FEATURE_TSX_FORCE_ABORT },
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{ MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL },
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{ MSR_AMD64_LS_CFG, X86_FEATURE_LS_CFG_SSBD },
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{ MSR_AMD64_DE_CFG, X86_FEATURE_LFENCE_RDTSC },
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};
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int i;
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msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id));
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for (i = 0; i < ARRAY_SIZE(msr_enum); i++) {
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if (boot_cpu_has(msr_enum[i].feature))
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msr_build_context(&msr_enum[i].msr_no, 1);
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}
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}
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static int pm_check_save_msr(void)
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@ -67,8 +67,27 @@ static bool is_vmpck_empty(struct snp_guest_dev *snp_dev)
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return true;
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}
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/*
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* If an error is received from the host or AMD Secure Processor (ASP) there
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* are two options. Either retry the exact same encrypted request or discontinue
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* using the VMPCK.
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*
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* This is because in the current encryption scheme GHCB v2 uses AES-GCM to
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* encrypt the requests. The IV for this scheme is the sequence number. GCM
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* cannot tolerate IV reuse.
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*
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* The ASP FW v1.51 only increments the sequence numbers on a successful
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* guest<->ASP back and forth and only accepts messages at its exact sequence
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* number.
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*
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* So if the sequence number were to be reused the encryption scheme is
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* vulnerable. If the sequence number were incremented for a fresh IV the ASP
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* will reject the request.
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*/
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static void snp_disable_vmpck(struct snp_guest_dev *snp_dev)
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{
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dev_alert(snp_dev->dev, "Disabling vmpck_id %d to prevent IV reuse.\n",
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vmpck_id);
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memzero_explicit(snp_dev->vmpck, VMPCK_KEY_LEN);
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snp_dev->vmpck = NULL;
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}
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@ -321,34 +340,71 @@ static int handle_guest_request(struct snp_guest_dev *snp_dev, u64 exit_code, in
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if (rc)
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return rc;
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/* Call firmware to process the request */
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/*
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* Call firmware to process the request. In this function the encrypted
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* message enters shared memory with the host. So after this call the
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* sequence number must be incremented or the VMPCK must be deleted to
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* prevent reuse of the IV.
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*/
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rc = snp_issue_guest_request(exit_code, &snp_dev->input, &err);
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/*
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* If the extended guest request fails due to having too small of a
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* certificate data buffer, retry the same guest request without the
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* extended data request in order to increment the sequence number
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* and thus avoid IV reuse.
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*/
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if (exit_code == SVM_VMGEXIT_EXT_GUEST_REQUEST &&
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err == SNP_GUEST_REQ_INVALID_LEN) {
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const unsigned int certs_npages = snp_dev->input.data_npages;
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exit_code = SVM_VMGEXIT_GUEST_REQUEST;
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/*
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* If this call to the firmware succeeds, the sequence number can
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* be incremented allowing for continued use of the VMPCK. If
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* there is an error reflected in the return value, this value
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* is checked further down and the result will be the deletion
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* of the VMPCK and the error code being propagated back to the
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* user as an ioctl() return code.
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*/
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rc = snp_issue_guest_request(exit_code, &snp_dev->input, &err);
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/*
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* Override the error to inform callers the given extended
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* request buffer size was too small and give the caller the
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* required buffer size.
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*/
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err = SNP_GUEST_REQ_INVALID_LEN;
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snp_dev->input.data_npages = certs_npages;
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}
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if (fw_err)
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*fw_err = err;
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if (rc)
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return rc;
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if (rc) {
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dev_alert(snp_dev->dev,
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"Detected error from ASP request. rc: %d, fw_err: %llu\n",
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rc, *fw_err);
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goto disable_vmpck;
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}
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/*
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* The verify_and_dec_payload() will fail only if the hypervisor is
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* actively modifying the message header or corrupting the encrypted payload.
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* This hints that hypervisor is acting in a bad faith. Disable the VMPCK so that
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* the key cannot be used for any communication. The key is disabled to ensure
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* that AES-GCM does not use the same IV while encrypting the request payload.
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*/
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rc = verify_and_dec_payload(snp_dev, resp_buf, resp_sz);
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if (rc) {
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dev_alert(snp_dev->dev,
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"Detected unexpected decode failure, disabling the vmpck_id %d\n",
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vmpck_id);
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snp_disable_vmpck(snp_dev);
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return rc;
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"Detected unexpected decode failure from ASP. rc: %d\n",
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rc);
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goto disable_vmpck;
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}
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/* Increment to new message sequence after payload decryption was successful. */
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snp_inc_msg_seqno(snp_dev);
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return 0;
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disable_vmpck:
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snp_disable_vmpck(snp_dev);
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return rc;
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}
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static int get_report(struct snp_guest_dev *snp_dev, struct snp_guest_request_ioctl *arg)
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