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ath9k: Use PCI Express Capability accessors

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Use PCI Express Capability access functions to simplify ath9k driver.

Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Jiang Liu 2012-07-24 17:20:25 +08:00 committed by Bjorn Helgaas
parent eb0ff56366
commit 08bd108096
1 changed files with 6 additions and 15 deletions
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21
drivers/net/wireless/ath/ath9k/pci.c
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@ -112,41 +112,32 @@ static void ath_pci_aspm_init(struct ath_common *common)
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct pci_dev *pdev = to_pci_dev(sc->dev); struct pci_dev *pdev = to_pci_dev(sc->dev);
struct pci_dev *parent; struct pci_dev *parent;
int pos; u16 aspm;
u8 aspm;
if (!ah->is_pciexpress) if (!ah->is_pciexpress)
return; return;
pos = pci_pcie_cap(pdev);
if (!pos)
return;
parent = pdev->bus->self; parent = pdev->bus->self;
if (!parent) if (!parent)
return; return;
if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
/* Bluetooth coexistance requires disabling ASPM. */ /* Bluetooth coexistance requires disabling ASPM. */
pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm); pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
/* /*
* Both upstream and downstream PCIe components should * Both upstream and downstream PCIe components should
* have the same ASPM settings. * have the same ASPM settings.
*/ */
pos = pci_pcie_cap(parent); pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
return; return;
} }
pos = pci_pcie_cap(parent); pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
ah->aspm_enabled = true; ah->aspm_enabled = true;
/* Initialize PCIe PM and SERDES registers. */ /* Initialize PCIe PM and SERDES registers. */