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i915/dp/fec: Cache the FEC_CAPABLE DPCD register

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Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.

v2: Avoid using memset and array for a single
field. (Manasi,Jani)

v3: Print FEC CAPABILITY value. (Manasi)

Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181102041455.15818-1-anusha.srivatsa@intel.com
This commit is contained in:
Anusha Srivatsa 2018-11-01 21:14:54 -07:00 committed by Manasi Navare
parent 83b466b1dc
commit 08cadae8e1
2 changed files with 13 additions and 0 deletions
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12
drivers/gpu/drm/i915/intel_dp.c
View File

@ -3954,6 +3954,9 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
*/ */
memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
/* Clear fec_capable to avoid using stale values */
intel_dp->fec_capable = 0;
/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
intel_dp->edp_dpcd[0] >= DP_EDP_14) { intel_dp->edp_dpcd[0] >= DP_EDP_14) {
@ -3966,6 +3969,15 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("DSC DPCD: %*ph\n", DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
(int)sizeof(intel_dp->dsc_dpcd), (int)sizeof(intel_dp->dsc_dpcd),
intel_dp->dsc_dpcd); intel_dp->dsc_dpcd);
/* FEC is supported only on DP 1.4 */
if (!intel_dp_is_edp(intel_dp)) {
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
&intel_dp->fec_capable) < 0)
DRM_ERROR("Failed to read FEC DPCD register\n");
DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
intel_dp->fec_capable);
}
} }
} }

1
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1114,6 +1114,7 @@ struct intel_dp {
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
u8 fec_capable;
/* source rates */ /* source rates */
int num_source_rates; int num_source_rates;
const int *source_rates; const int *source_rates;