net: sparx5: Add support for ptp clocks
The sparx5 has 3 PHC. Enable each of them, for now all the timestamping is happening on the first PHC. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Horatiu Vultur
David S. Miller
parent
3193a61181
commit
0933bd0404
@ -7,4 +7,5 @@ obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
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sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
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sparx5_netdev.o sparx5_phylink.o sparx5_port.o sparx5_mactable.o sparx5_vlan.o \
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sparx5_switchdev.o sparx5_calendar.o sparx5_ethtool.o sparx5_fdma.o
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sparx5_switchdev.o sparx5_calendar.o sparx5_ethtool.o sparx5_fdma.o \
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sparx5_ptp.o
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@ -847,6 +847,12 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
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dev_err(sparx5->dev, "Start failed\n");
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goto cleanup_ports;
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}
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err = sparx5_ptp_init(sparx5);
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if (err) {
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dev_err(sparx5->dev, "PTP failed\n");
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goto cleanup_ports;
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}
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goto cleanup_config;
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cleanup_ports:
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@ -870,6 +876,7 @@ static int mchp_sparx5_remove(struct platform_device *pdev)
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disable_irq(sparx5->fdma_irq);
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sparx5->fdma_irq = -ENXIO;
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}
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sparx5_ptp_deinit(sparx5);
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sparx5_fdma_stop(sparx5);
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sparx5_cleanup_ports(sparx5);
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/* Unregister netdevs */
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@ -14,6 +14,8 @@
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#include <linux/if_vlan.h>
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#include <linux/bitmap.h>
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#include <linux/phylink.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/hrtimer.h>
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#include "sparx5_main_regs.h"
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@ -79,6 +81,9 @@ enum sparx5_vlan_port_type {
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#define FDMA_RX_DCB_MAX_DBS 15
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#define FDMA_TX_DCB_MAX_DBS 1
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#define SPARX5_PHC_COUNT 3
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#define SPARX5_PHC_PORT 0
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struct sparx5;
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struct sparx5_db_hw {
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@ -178,6 +183,14 @@ enum sparx5_core_clockfreq {
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SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */
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};
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struct sparx5_phc {
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struct ptp_clock *clock;
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struct ptp_clock_info info;
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struct hwtstamp_config hwtstamp_config;
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struct sparx5 *sparx5;
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u8 index;
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};
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struct sparx5 {
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struct platform_device *pdev;
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struct device *dev;
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@ -225,6 +238,10 @@ struct sparx5 {
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int fdma_irq;
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struct sparx5_rx rx;
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struct sparx5_tx tx;
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/* PTP */
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bool ptp;
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struct sparx5_phc phc[SPARX5_PHC_COUNT];
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spinlock_t ptp_clock_lock; /* lock for phc */
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};
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/* sparx5_switchdev.c */
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@ -294,6 +311,10 @@ int sparx5_register_netdevs(struct sparx5 *sparx5);
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void sparx5_destroy_netdevs(struct sparx5 *sparx5);
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void sparx5_unregister_netdevs(struct sparx5 *sparx5);
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/* sparx5_ptp.c */
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int sparx5_ptp_init(struct sparx5 *sparx5);
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void sparx5_ptp_deinit(struct sparx5 *sparx5);
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/* Clock period in picoseconds */
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static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
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{
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326
drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
Normal file
326
drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
Normal file
@ -0,0 +1,326 @@
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// SPDX-License-Identifier: GPL-2.0+
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/* Microchip Sparx5 Switch driver
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*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* The Sparx5 Chip Register Model can be browsed at this location:
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* https://github.com/microchip-ung/sparx-5_reginfo
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*/
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#include <linux/ptp_classify.h>
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#include "sparx5_main_regs.h"
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#include "sparx5_main.h"
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#define SPARX5_MAX_PTP_ID 512
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#define TOD_ACC_PIN 0x4
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enum {
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PTP_PIN_ACTION_IDLE = 0,
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PTP_PIN_ACTION_LOAD,
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PTP_PIN_ACTION_SAVE,
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PTP_PIN_ACTION_CLOCK,
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PTP_PIN_ACTION_DELTA,
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PTP_PIN_ACTION_TOD
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};
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static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5)
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{
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/* Represents 1ppm adjustment in 2^59 format with 1.59687500000(625)
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* 1.99609375000(500), 3.99218750000(250) as reference
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* The value is calculated as following:
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* (1/1000000)/((2^-59)/X)
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*/
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u64 res;
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switch (sparx5->coreclock) {
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case SPX5_CORE_CLOCK_250MHZ:
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res = 2301339409586;
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break;
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case SPX5_CORE_CLOCK_500MHZ:
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res = 1150669704793;
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break;
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case SPX5_CORE_CLOCK_625MHZ:
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res = 920535763834;
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break;
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default:
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WARN_ON("Invalid core clock");
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break;
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}
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return res;
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}
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static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5)
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{
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u64 res;
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switch (sparx5->coreclock) {
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case SPX5_CORE_CLOCK_250MHZ:
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res = 0x1FF0000000000000;
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break;
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case SPX5_CORE_CLOCK_500MHZ:
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res = 0x0FF8000000000000;
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break;
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case SPX5_CORE_CLOCK_625MHZ:
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res = 0x0CC6666666666666;
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break;
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default:
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WARN_ON("Invalid core clock");
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break;
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}
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return res;
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}
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static int sparx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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{
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struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info);
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struct sparx5 *sparx5 = phc->sparx5;
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unsigned long flags;
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bool neg_adj = 0;
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u64 tod_inc;
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u64 ref;
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if (!scaled_ppm)
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return 0;
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if (scaled_ppm < 0) {
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neg_adj = 1;
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scaled_ppm = -scaled_ppm;
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}
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tod_inc = sparx5_ptp_get_nominal_value(sparx5);
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/* The multiplication is split in 2 separate additions because of
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* overflow issues. If scaled_ppm with 16bit fractional part was bigger
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* than 20ppm then we got overflow.
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*/
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ref = sparx5_ptp_get_1ppm(sparx5) * (scaled_ppm >> 16);
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ref += (sparx5_ptp_get_1ppm(sparx5) * (0xffff & scaled_ppm)) >> 16;
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tod_inc = neg_adj ? tod_inc - ref : tod_inc + ref;
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spin_lock_irqsave(&sparx5->ptp_clock_lock, flags);
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spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(1 << BIT(phc->index)),
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PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS,
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sparx5, PTP_PTP_DOM_CFG);
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spx5_wr((u32)tod_inc & 0xFFFFFFFF, sparx5,
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PTP_CLK_PER_CFG(phc->index, 0));
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spx5_wr((u32)(tod_inc >> 32), sparx5,
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PTP_CLK_PER_CFG(phc->index, 1));
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spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0),
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PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, sparx5,
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PTP_PTP_DOM_CFG);
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spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags);
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return 0;
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}
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static int sparx5_ptp_settime64(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info);
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struct sparx5 *sparx5 = phc->sparx5;
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unsigned long flags;
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spin_lock_irqsave(&sparx5->ptp_clock_lock, flags);
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/* Must be in IDLE mode before the time can be loaded */
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spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(phc->index) |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(0),
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PTP_PTP_PIN_CFG_PTP_PIN_ACTION |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC,
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sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN));
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/* Set new value */
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spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)),
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sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN));
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spx5_wr(lower_32_bits(ts->tv_sec),
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sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN));
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spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN));
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/* Apply new values */
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spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(phc->index) |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(0),
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PTP_PTP_PIN_CFG_PTP_PIN_ACTION |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC,
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sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN));
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spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags);
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return 0;
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}
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static int sparx5_ptp_gettime64(struct ptp_clock_info *ptp,
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struct timespec64 *ts)
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{
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struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info);
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struct sparx5 *sparx5 = phc->sparx5;
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unsigned long flags;
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time64_t s;
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s64 ns;
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spin_lock_irqsave(&sparx5->ptp_clock_lock, flags);
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spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(phc->index) |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(0),
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PTP_PTP_PIN_CFG_PTP_PIN_ACTION |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC,
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sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN));
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s = spx5_rd(sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN));
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s <<= 32;
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s |= spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN));
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ns = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN));
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ns &= PTP_PTP_TOD_NSEC_PTP_TOD_NSEC;
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spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags);
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/* Deal with negative values */
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if ((ns & 0xFFFFFFF0) == 0x3FFFFFF0) {
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s--;
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ns &= 0xf;
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ns += 999999984;
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}
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set_normalized_timespec64(ts, s, ns);
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return 0;
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}
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static int sparx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info);
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struct sparx5 *sparx5 = phc->sparx5;
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if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) {
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unsigned long flags;
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spin_lock_irqsave(&sparx5->ptp_clock_lock, flags);
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/* Must be in IDLE mode before the time can be loaded */
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spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(phc->index) |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(0),
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PTP_PTP_PIN_CFG_PTP_PIN_ACTION |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC,
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sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN));
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spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta),
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sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN));
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/* Adjust time with the value of PTP_TOD_NSEC */
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spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_DELTA) |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(phc->index) |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(0),
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PTP_PTP_PIN_CFG_PTP_PIN_ACTION |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC,
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sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN));
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spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags);
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} else {
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/* Fall back using sparx5_ptp_settime64 which is not exact */
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struct timespec64 ts;
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u64 now;
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sparx5_ptp_gettime64(ptp, &ts);
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now = ktime_to_ns(timespec64_to_ktime(ts));
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ts = ns_to_timespec64(now + delta);
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sparx5_ptp_settime64(ptp, &ts);
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}
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return 0;
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}
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static struct ptp_clock_info sparx5_ptp_clock_info = {
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.owner = THIS_MODULE,
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.name = "sparx5 ptp",
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.max_adj = 200000,
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.gettime64 = sparx5_ptp_gettime64,
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.settime64 = sparx5_ptp_settime64,
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.adjtime = sparx5_ptp_adjtime,
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.adjfine = sparx5_ptp_adjfine,
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};
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static int sparx5_ptp_phc_init(struct sparx5 *sparx5,
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int index,
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struct ptp_clock_info *clock_info)
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{
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struct sparx5_phc *phc = &sparx5->phc[index];
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phc->info = *clock_info;
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phc->clock = ptp_clock_register(&phc->info, sparx5->dev);
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if (IS_ERR(phc->clock))
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return PTR_ERR(phc->clock);
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phc->index = index;
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phc->sparx5 = sparx5;
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/* PTP Rx stamping is always enabled. */
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phc->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
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return 0;
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}
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int sparx5_ptp_init(struct sparx5 *sparx5)
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{
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u64 tod_adj = sparx5_ptp_get_nominal_value(sparx5);
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int err, i;
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if (!sparx5->ptp)
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return 0;
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for (i = 0; i < SPARX5_PHC_COUNT; ++i) {
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err = sparx5_ptp_phc_init(sparx5, i, &sparx5_ptp_clock_info);
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if (err)
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return err;
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}
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spin_lock_init(&sparx5->ptp_clock_lock);
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/* Disable master counters */
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spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0), sparx5, PTP_PTP_DOM_CFG);
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/* Configure the nominal TOD increment per clock cycle */
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spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0x7),
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PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS,
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sparx5, PTP_PTP_DOM_CFG);
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for (i = 0; i < SPARX5_PHC_COUNT; ++i) {
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spx5_wr((u32)tod_adj & 0xFFFFFFFF, sparx5,
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PTP_CLK_PER_CFG(i, 0));
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spx5_wr((u32)(tod_adj >> 32), sparx5,
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PTP_CLK_PER_CFG(i, 1));
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}
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spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0),
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PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS,
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sparx5, PTP_PTP_DOM_CFG);
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|
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/* Enable master counters */
|
||||
spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0x7), sparx5, PTP_PTP_DOM_CFG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sparx5_ptp_deinit(struct sparx5 *sparx5)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < SPARX5_PHC_COUNT; ++i)
|
||||
ptp_clock_unregister(sparx5->phc[i].clock);
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user