Merge tag 'amd-drm-fixes-5.19-2022-07-13' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-5.19-2022-07-13: amdgpu: - DP MST blank screen fix for specific platforms - MEC firmware check fix for GC 10.3.7 - Deep color fix for DCE - Fix possible divide by 0 - Coverage blend mode fix - Fix cursor only commit timestamps Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220713172920.6037-1-alexander.deucher@amd.com
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commit
093f8d8f10
@ -184,6 +184,8 @@ static void kfd_device_info_init(struct kfd_dev *kfd,
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/* Navi2x+, Navi1x+ */
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if (gc_version == IP_VERSION(10, 3, 6))
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kfd->device_info.no_atomic_fw_version = 14;
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else if (gc_version == IP_VERSION(10, 3, 7))
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kfd->device_info.no_atomic_fw_version = 3;
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else if (gc_version >= IP_VERSION(10, 3, 0))
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kfd->device_info.no_atomic_fw_version = 92;
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else if (gc_version >= IP_VERSION(10, 1, 1))
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@ -72,6 +72,7 @@
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#include <linux/pci.h>
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#include <linux/firmware.h>
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#include <linux/component.h>
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#include <linux/dmi.h>
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#include <drm/display/drm_dp_mst_helper.h>
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#include <drm/display/drm_hdmi_helper.h>
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@ -462,6 +463,26 @@ static void dm_pflip_high_irq(void *interrupt_params)
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vrr_active, (int) !e);
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}
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static void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
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{
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struct drm_crtc *crtc = &acrtc->base;
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struct drm_device *dev = crtc->dev;
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unsigned long flags;
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drm_crtc_handle_vblank(crtc);
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spin_lock_irqsave(&dev->event_lock, flags);
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/* Send completion event for cursor-only commits */
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if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
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drm_crtc_send_vblank_event(crtc, acrtc->event);
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drm_crtc_vblank_put(crtc);
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acrtc->event = NULL;
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}
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static void dm_vupdate_high_irq(void *interrupt_params)
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{
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struct common_irq_params *irq_params = interrupt_params;
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@ -500,7 +521,7 @@ static void dm_vupdate_high_irq(void *interrupt_params)
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* if a pageflip happened inside front-porch.
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*/
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if (vrr_active) {
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drm_crtc_handle_vblank(&acrtc->base);
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dm_crtc_handle_vblank(acrtc);
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/* BTR processing for pre-DCE12 ASICs */
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if (acrtc->dm_irq_params.stream &&
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@ -552,7 +573,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
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* to dm_vupdate_high_irq after end of front-porch.
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*/
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if (!vrr_active)
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drm_crtc_handle_vblank(&acrtc->base);
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dm_crtc_handle_vblank(acrtc);
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/**
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* Following stuff must happen at start of vblank, for crc
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@ -1382,6 +1403,41 @@ static bool dm_should_disable_stutter(struct pci_dev *pdev)
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return false;
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}
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static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
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{
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
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},
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},
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{
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
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},
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},
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{
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
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},
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},
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{}
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};
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static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
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{
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const struct dmi_system_id *dmi_id;
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dm->aux_hpd_discon_quirk = false;
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dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
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if (dmi_id) {
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dm->aux_hpd_discon_quirk = true;
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DRM_INFO("aux_hpd_discon_quirk attached\n");
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}
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}
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static int amdgpu_dm_init(struct amdgpu_device *adev)
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{
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struct dc_init_data init_data;
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@ -1508,6 +1564,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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}
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INIT_LIST_HEAD(&adev->dm.da_list);
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retrieve_dmi_info(&adev->dm);
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/* Display Core create. */
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adev->dm.dc = dc_create(&init_data);
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@ -5407,7 +5466,7 @@ fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
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}
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}
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if (per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
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if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
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*pre_multiplied_alpha = false;
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}
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@ -9135,6 +9194,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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struct amdgpu_bo *abo;
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uint32_t target_vblank, last_flip_vblank;
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bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
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bool cursor_update = false;
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bool pflip_present = false;
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struct {
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struct dc_surface_update surface_updates[MAX_SURFACES];
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@ -9170,8 +9230,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
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/* Cursor plane is handled after stream updates */
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if (plane->type == DRM_PLANE_TYPE_CURSOR)
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if (plane->type == DRM_PLANE_TYPE_CURSOR) {
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if ((fb && crtc == pcrtc) ||
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(old_plane_state->fb && old_plane_state->crtc == pcrtc))
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cursor_update = true;
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continue;
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}
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if (!fb || !crtc || pcrtc != crtc)
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continue;
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@ -9334,6 +9399,17 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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bundle->stream_update.vrr_infopacket =
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&acrtc_state->stream->vrr_infopacket;
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}
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} else if (cursor_update && acrtc_state->active_planes > 0 &&
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!acrtc_state->force_dpms_off &&
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acrtc_attach->base.state->event) {
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drm_crtc_vblank_get(pcrtc);
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spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
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acrtc_attach->event = acrtc_attach->base.state->event;
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acrtc_attach->base.state->event = NULL;
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spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
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}
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/* Update the planes if changed or disable if we don't have any. */
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@ -540,6 +540,14 @@ struct amdgpu_display_manager {
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* last successfully applied backlight values.
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*/
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u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
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/**
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* @aux_hpd_discon_quirk:
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*
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* quirk for hpd discon while aux is on-going.
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* occurred on certain intel platform
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*/
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bool aux_hpd_discon_quirk;
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};
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enum dsc_clock_force_state {
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@ -56,6 +56,8 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
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ssize_t result = 0;
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struct aux_payload payload;
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enum aux_return_code_type operation_result;
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struct amdgpu_device *adev;
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struct ddc_service *ddc;
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if (WARN_ON(msg->size > 16))
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return -E2BIG;
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@ -74,6 +76,21 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
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result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
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&operation_result);
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/*
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* w/a on certain intel platform where hpd is unexpected to pull low during
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* 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
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* aux transaction is succuess in such case, therefore bypass the error
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*/
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ddc = TO_DM_AUX(aux)->ddc_service;
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adev = ddc->ctx->driver_context;
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if (adev->dm.aux_hpd_discon_quirk) {
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if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
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operation_result == AUX_RET_ERROR_HPD_DISCON) {
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result = 0;
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operation_result = AUX_RET_SUCCESS;
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}
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}
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if (payload.write && result >= 0)
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result = msg->size;
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@ -1117,12 +1117,13 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
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* on certain displays, such as the Sharp 4k. 36bpp is needed
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* to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
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* SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
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* precision on at least DCN display engines. However, at least
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* Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
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* so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3
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* did not show such problems, so this seems to be the exception.
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* precision on DCN display engines, but apparently not for DCE, as
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* far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
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* problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
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* neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
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* passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
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*/
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if (plane_state->ctx->dce_version > DCE_VERSION_11_0)
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if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
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pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
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else
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pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
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@ -1228,6 +1228,8 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
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uint32_t crystal_clock_freq = 2500;
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uint32_t tach_period;
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if (speed == 0)
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return -EINVAL;
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/*
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* To prevent from possible overheat, some ASICs may have requirement
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* for minimum fan speed:
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