media: mt9p031: Increase post-reset delay
The MT9P006 sensor driver sporadically fails to probe because the sensor responds with a NACK condition to I2C address on the bus during an attempt to read the sensor MT9P031_CHIP_VERSION register in mt9p031_registered(). Neither the MT9P006 nor MT9P031 datasheets are clear on reset signal timing. Older MT9M034 [1] datasheet provides those timing figures in Appendix-A and indicates it is necessary to wait 850000 EXTCLK cycles before starting any I2C communication. Add such a delay, which does make the sporadic I2C NACK go away, so it is likely similar constraint applies to this sensor. [1] https://www.onsemi.com/pdf/datasheet/mt9m034-d.pdf Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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@ -307,6 +307,7 @@ static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031)
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static int mt9p031_power_on(struct mt9p031 *mt9p031)
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{
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unsigned long rate, delay;
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int ret;
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/* Ensure RESET_BAR is active */
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@ -334,7 +335,12 @@ static int mt9p031_power_on(struct mt9p031 *mt9p031)
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/* Now RESET_BAR must be high */
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if (mt9p031->reset) {
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gpiod_set_value(mt9p031->reset, 0);
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usleep_range(1000, 2000);
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/* Wait 850000 EXTCLK cycles before de-asserting reset. */
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rate = clk_get_rate(mt9p031->clk);
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if (!rate)
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rate = 6000000; /* Slowest supported clock, 6 MHz */
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delay = DIV_ROUND_UP(850000 * 1000, rate);
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msleep(delay);
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}
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return 0;
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